72V51246L7-5BBG [IDT]
FIFO, 32KX36, 4ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256;型号: | 72V51246L7-5BBG |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | FIFO, 32KX36, 4ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 LTE 先进先出芯片 |
文件: | 总56页 (文件大小:536K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3VMULTI-QUEUEFLOW-CONTROLDEVICES
(4QUEUES)36BITWIDECONFIGURATION
589,824bits
1,179,648bits
2,359,296bits
IDT72V51236
IDT72V51246
IDT72V51256
•
•
•
4 bit parallel flag status on both read and write ports
FEATURES:
Provides continuous PAE and PAF status of up to 4 Queues
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
- x36in to x36out
- x18in to x36out
- x9in to x36out
- x36in to x18out
- x36in to x9out
•
Choose from among the following memory density options:
IDT72V51236
IDT72V51246
IDT72V51256
Total Available Memory = 589,824 bits
Total Available Memory = 1,179,648 bits
Total Available Memory = 2,359,296 bits
•
•
•
Configurable from 1 to 4 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 256 x 36
Independent Read and Write access per queue
User programmable via serial port
Default multi-queue device configurations
-IDT72V51236: 4,096 x 36 x 4Q
•
•
•
•
•
•
•
•
•
•
•
FWFT mode of operation on read port
Packet mode operation
Partial Reset, clears data in single Queue
Expansion of up to 8 multi-queue devices in parallel is available
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
-IDT72V51246: 8,192 x 36 x 4Q
-IDT72V51256: 16,384 x 36 x 4Q
•
•
•
•
100% Bus Utilization, Read and Write on every clock cycle
166 MHz High speed operation (6ns cycle time)
3.7ns access time
Individual, Active queue flags (OV, FF, PAE, PAF, PR)
FUNCTIONALBLOCKDIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
WADEN
FSTR
RADEN
ESTR
RDADD
REN
Q0
WRADD
WEN
6
5
RCLK
WCLK
OE
Q
out
D
in
x9, x18, x36
DATA OUT
x9, x18, x36
DATA IN
OV
FF
PAF
Q3
PR
PAE
PAFn
4
PAEn/PRn
4
5937 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc
JUNE 2003
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5937/9
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Apacketmode ofoperationis alsoprovidedwhenthe device is configured
for36bitinputand36bitoutputportsizes.ThePacketmodeprovidestheuser
withaflagoutputindicatingwhenatleastone(ormore)packetsofdatawithina
queueisavailableforreading.ThePacketReadyprovidestheuserwithameans
bywhichtomarkthestartandendofpacketsofdatabeingpassedthroughthe
queues. The multi-queue device then provides the user with an internally
generatedpacketreadystatus perqueue.
Theuserhasfullflexibilityconfiguringqueueswithinthedevice,beingable
toprogramthetotalnumberofqueues between1and4,theindividualqueue
depthsbeingindependentofeachother.Theprogrammableflagpositionsare
alsouserprogrammable.Allprogrammingisdoneviaadedicatedserialport.
Iftheuserdoesnotwishtoprogramthemulti-queuedevice,adefaultoptionis
availablethatconfiguresthedeviceinapredeterminedmanner.
DESCRIPTION:
The IDT72V51236/72V51246/72V51256 multi-queue flow-control de-
vicesaresinglechipwithinwhichanywherebetween1and4discreteFIFO
queuescanbesetup.Allqueueswithinthedevicehaveacommondatainput
bus,(writeport)andacommondataoutputbus,(readport).Datawritteninto
the write portis directedtoa respective queue via aninternalde-multiplex
operation,addressedbytheuser.Datareadfromthereadportisaccessed
froma respective queue via aninternalmultiplexoperation,addressedby
the user. Data writes and reads can be performed at high speeds up to
166MHz,withaccesstimesof3.7ns.Datawriteandreadoperationsaretotally
independent of each other, a queue maybe selected on the write port and
adifferentqueueonthereadportorbothportsmayselectthesamequeue
simultaneously.
BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster
Reset latches in all configuration setup pins and must be performed before
programmingofthedevicecantakeplace.APartialResetwillresetthereadand
writepointersofanindividualqueue,providedthatthequeueisselectedonboth
thewriteportandreadportatthetimeofpartialreset.
AJTAGtestportisprovided,herethemulti-queueflow-controldevicehasa
fullyfunctionalBoundaryScanfeature,compliantwithIEEE1149.1Standard
TestAccessPortandBoundaryScanArchitecture.
The device provides FullflagandOutputValidflagstatus forthe queue
selectedforwriteandreadoperations respectively.AlsoaProgrammable
AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.
Two 4 bit programmable flag busses are available, providing status of all
queues,includingqueuesnotselectedforwriteorreadoperations,theseflag
busses provide an individual flag per queue.
BusMatchingisavailableonthisdevice,eitherportcanbe9bits,18bits
or 36 bits wide provided that at least one port is 36 bits wide. When Bus
Matchingisusedthedeviceensuresthelogicaltransferofdatathroughput
inaLittleEndianmanner.
SeeFigure1,Multi-QueueFlow-ControlDeviceBlockDiagramforanoutline
ofthefunctionalblockswithinthedevice.
2
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D
D
= TEOP
= TSOP
D
35
34
in
x9, x18, x36
2
D - D
0
35
WCLK
WEN
TMS
TDI
INPUT
DEMUX
JTAG
TDO
TCK
Logic
5
WRADD
WADEN
Write Control
Logic
TRST
Write Pointers
PR
Packet Mode
Logic
4
PAF
General Flag
Monitor
PRn/PAEn
FSTR
PAFn
4
FSYNC
Upto 4
FIFO
Queues
FXO
FXI
OV
Active Q
Flags
PAE
0.5 Mbit
1.1 Mbit
2.3 Mbit
Dual Port
Memory
Active Q
Flags
FF
PAF
PAE
General Flag
Monitor
SI
SO
SCLK
Serial
Multi-Queue
Programming
ESTR
ESYNC
EXI
SENI
SENO
EXO
Read Pointers
FM
IW
OW
BM
Reset
Logic
6
RDADD
RADEN
Read Control
Logic
MAST
PKT
REN
RCLK
ID0
ID1
ID2
DF
Device ID
3 Bit
OUTPUT
MUX
PAE/ PAF
Offset
2
Q
Q
= REOP
= RSOP
DFM
35
34
OUTPUT
REGISTER
PRS
MRS
5937 drw02
OE
Q - Q
35
0
Q
x9, x18, x36
out
Figure 1. Multi-Queue Flow-Control Device Block Diagram
3
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINCONFIGURATION
A1 BALL PAD CORNER
A
D14
D15
D13
D16
D12
D11
D10
D9
D7
D6
D4
D3
D1
D0
TCK
TMS
TDO
TDI
ID1
ID0
Q3
Q2
Q6
Q9
Q8
Q7
Q12
Q11
Q14
Q13
Q15
Q19
B
C
D
E
F
Q5
TRST
VCC
VCC
GND
GND
GND
GND
GND
GND
D17
D18
D19
D8
D5
D2
GND
VCC
ID2
VCC
GND
GND
GND
GND
GND
GND
GND
Q0
VCC
VCC
GND
GND
GND
GND
GND
GND
Q1
Q4
Q10
Q16
Q24
Q27
Q30
Q33
PKT
GND
BM
Q17
Q21
Q23
Q26
Q29
Q32
Q35
MAST
IW
Q18
Q20
Q22
Q25
Q28
Q31
Q34
FM
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
D20
D23
D26
D21
D24
D27
D22
D25
D28
VCC
VCC
VCC
VCC
VCC
GND
VCC
VCC
GND
GND
VCC
VCC
G
H
J
D29
D32
GND
GND
SI
D30
D31
D34
D35
GND
DF
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
GND
GND
VCC
VCC
VCC
D33
VCC
VCC
GND
GND
DFM
K
VCC
VCC
L
OW
M
N
P
R
T
SENO
SENI
OE
SO
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
VCC
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RDADD0 RDADD1
WRADD1 WRADD0
SCLK
RDADD2 GND
GND
FF
OV
PAE
GND
GND
GND
WADEN
PAF3
DNC
DNC
DNC
DNC
PAE3 RDADD3 RDADD4 RDADD5
PAF
PRS
PR
WRADD3 WRADD2 FSYNC
FSTR
PAF2
PAF1
DNC
DNC
DNC
DNC
DNC
DNC
PAE2
PAE1
RADEN ESTR
ESYNC
EXI
WEN
MRS
REN
WRADD4
FXI
FXO
PAF0
WCLK
RCLK
PAE0
EXO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
5937 drw03
NOTE:
1. DNC - Do Not Connect.
PBGA (BB256-1, order code: BB)
TOP VIEW
4
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
provides a user programmable almost full flag for all 4 queues and when a
respectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus
for that queue. Conversely, the read port has an output valid flag, providing
statusofthedatabeingreadfromthequeueselectedonthereadport.Aswell
astheoutputvalidflagthedeviceprovidesadedicatedalmostemptyflag.This
almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.
Thedeviceprovidesauserprogrammablealmostemptyflagforall4queues
andwhenarespectivequeueisselectedonthereadport,thealmostemptyflag
providesstatusforthatqueue.
DETAILEDDESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
singledataoutputportwithupto4FIFOqueuesinparallelbufferingbetween
thetwoports.Theusercansetupbetween1and4Queueswithinthedevice.
Thesequeuescanbeconfiguredtoutilizethetotalavailablememory,providing
theuserwithfullflexibilityandabilitytoconfigurethequeuestobevariousdepths,
independentofoneanother.
PROGRAMMABLE FLAG BUSSES
MEMORYORGANIZATION/ALLOCATION
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost
fullflagstatusbusisprovided,thisbusis4bitswide.Also,analmostemptyflag
statusbusisprovided,againthisbusis4bitswide.Thepurposeoftheseflag
bussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels
withinqueuesthatmaynotbeselectedonthewriteorreadport.Asmentioned,
thedeviceprovidesalmostfullandalmostemptyregisters(programmableby
the user) for each of the 4 queues in the device.
The4bitPAEnand4bitPAFnbussesprovideadiscretestatusoftheAlmost
EmptyandAlmostFullconditionsofall4queue's.Ifthedeviceisprogrammed
for less than 4 queue's, then there will be a corresponding number of active
outputs onthePAEnandPAFnbusses.
Theflagbussescanprovideacontinuousstatusofallqueues.Ifdevicesare
connectedinexpansionmodetheindividualflagbussescanbeleftinadiscrete
form,providingconstantstatusofallqueues,orthebussesofindividualdevices
canbe connectedtogethertoproduce a single bus of4bits. The device can
then operate in a "Polled" or "Direct" mode.
Whenoperatinginpolledmodetheflagbusprovidesstatusofeachdevice
sequentially,thatis,oneachrisingedgeofaclocktheflagbusisupdatedtoshow
thestatusofeachdeviceinorder.Therisingedgeofthewriteclockwillupdate
theAlmostFullbusandarisingedgeonthereadclockwillupdatetheAlmost
Emptybus.
Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing
256x36bits.Whentheuserisconfiguringthenumberofqueuesandindividual
queuesizestheusermustallocatethememorytorespectivequeues,inunits
ofblocks,thatis,asinglequeuecanbemadeupfrom0tomblocks,wherem
isthetotalnumberofblocksavailablewithinadevice.Alsothetotalsizeofany
given queue must be in increments of 256 x36. For the IDT72V51236/
72V51246andIDT72V51256theTotalAvailableMemoryis64,128and256
blocks respectively(ablockbeing256x36). Queues canbebuiltfromthese
blocks to make any size queue desired and any number of queues desired.
BUS WIDTHS
Theinputportiscommontoallqueueswithinthedevice,asistheoutputport.
ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinputport
andoutputportcanbeeitherx9,x18orx36bitswideprovidedthatatleastone
of the ports is x36 bits wide, the read and write port widths being set
independentlyofoneanother.Becausetheportsarecommontoallqueuesthe
widthofthequeuesisnotindividuallyset,sothattheinputwidthofallqueues
are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete
queueviathewritequeueselectaddressinputs.Conversely,databeingread
fromthedevicereadportisreadfromaqueueselectedviathereadqueueselect
addressinputs.Datacanbesimultaneouslywrittenintoandreadfromthesame
queueordifferentqueues.Onceaqueueisselectedfordatawritesorreads,
the writing and reading operation is performed in the same manner as
conventionalIDTsynchronous FIFO,utilizingclocks andenables,thereis a
singleclockandenableperport.Whenaspecificqueueisaddressedonthe
writeport,dataplacedonthedatainputsiswrittentothatqueuesequentially
basedontherisingedgeofawriteclockprovidedsetupandholdtimesaremet.
Conversely,dataisreadontotheoutputportafteranaccesstimefromarising
edge on a read clock.
Theoperationofthewriteportiscomparabletothefunctionofaconventional
FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput
provides status of the selected queue. The operation of the read port is
comparabletothefunctionofaconventionalFIFOoperatinginFWFTmode.
Whenaqueueis selectedontheoutputport,thenextwordinthatqueuewill
automaticallyfallthroughtotheoutputregister.Allsubsequentwordsfromthat
queue require an enabled read cycle. Data cannot be read from a selected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
whendata readoutis valid. Ifthe userswitches toa queue thatis empty, the
lastwordfromtheprevious queuewillremainontheoutputregister.
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost
fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice
Whenoperatingindirectmodethedevicedrivingtheflagbusisselectedby
theuser.Theuseraddresses thedevicethatwilltakecontrolofarespective
flagbus, these PAFnand PAEnflagbusses operatingindependentlyofone
another.AddressingoftheAlmostFullflagbus is doneviathewriteportand
addressingoftheAlmostEmptyflagbus is doneviathereadport.
PACKETMODE
Themulti-queueflow-controldevicealsooffersa“PacketMode”operation.
PacketModeisuserselectableandrequiresthedevicetobeconfiguredwith
bothwrite andreadports as 36bits wide. Inpacketmode, users candefine
thelengthofpacketsorframebyusingthetwomostsignificantbitsofthe36-
bitword.Bit34isusedtomarktheStartofPacket(SOP)andbit35isusedto
markthe EndofPacket(EOP)as showninTable 5).Whenwritingdata into
agivenqueue,thefirstwordbeingwrittenismarked,bytheusersettingbit34
asthe“StartofPacket”(SOP)andthelastwordwrittenismarkedasthe“End
of Packet” (EOP) with all words written between the Start of Packet (SOP)
marker(bit34)andtheEndofpacket(EOP)packetmarker(bit35)constituting
theentirepacket.Apacketcanbeanylengththeuserdesires,uptothetotal
availablememoryinthemulti-queueflow-controldevice.Thedevicemonitors
theSOP(bit34)andlooksforthewordthatcontainstheEOP(bit35).Theread
port is supplied with an additional status flag, “Packet Ready”. The Packet
Ready(PR)flaginconjunctionwithOutputValid(OV)indicateswhenatleast
onepacket isavailabletoread.Wheninpacketmodethealmostemptyflag
status,providespacketreadyflagstatusforindividualqueues.
5
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
EXPANSION
deviceutilizingallmemoryblocksavailabletoproduceasinglequeue.Thisis
Expansionofmulti-queuedevicesisalsopossible,upto8devicescanbe thedeepestqueuethatcansetupwithinadevice.
connectedinaparallelfashionprovidingthepossibilityofbothdepthexpansion
For queue expansion of the 4 queue device, a maximum number of 32 (8
or queue expansion. Depth Expansion means expanding the depths of x4)queuesmaybesetup,eachqueuebeing2Kx36deep,iflessqueuesare
individual queues. Queue expansion means increasing the total number of setup,thenmorememoryblockswillbeavailabletoincreasequeuedepthsif
queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore desired.Whenconnectingmulti-queuedevicesinexpansionmodeallrespec-
memoryblocks withinamulti-queuedevicecanbeallocatedtoincreasethe tive input pins (data & control) and output pins (data & flags), should be
depth of a queue. For example, depth expansion of 8 devices provides the “connected”togetherbetweenindividualdevices.
possibilityof8queuesof64Kx36deep,eachqueuebeingsetupwithinasingle
6
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS
Symbol
Name
I/OTYPE
Description
BM
BusMatching
LVTTL ThispinissetupbeforeMasterResetandmustnottoggleduringanydeviceoperation.Thispinisused
INPUT alongwithIWandOWtosetupthemulti-queueflow-controldevicebuswidth.PleaserefertoTable3
fordetails.
D[35:0]
Din
DataInputBus
LVTTL These are the 36data inputpins. Data is writtenintothe device via these inputpins onthe rising edge
INPUT ofWCLKprovidedthatWEN is LOW.Note,thatinPacketmodeD32-D35maybeusedas packet
markers,pleaseseepacketreadyfunctionaldiscussionformoredetail.Duetobusmatchingnotallinputs
maybe used, anyunusedinputs shouldbe tiedLOW.
DF(1)
DefaultFlag
DefaultMode
LVTTL Iftheuserrequiresdefaultprogrammingofthemulti-queuedevice,thispinmustbesetupbeforeMaster
INPUT Resetandmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
(1)
DFM
LVTTL The multi-queue device requires programmingaftermasterreset. The usercandothis seriallyvia the
INPUT serialport,ortheusercanusethedefaultmethod.IfDFMisLOWatmasterresetthenserialmodewillbe
selected,ifHIGHthendefaultmodeisselected.
ESTR
PAEn Flag Bus
Strobe
LVTTL IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK
INPUT andtheRDADDbustoselectadeviceforitsqueuestobeplacedontothePAEnbusoutputs.Adevice
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polledoperationshasbeenselected,ESTRshouldbetiedinactive,LOW.Note,thataPAEnflagbus
selectioncannotbemade,(ESTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
andSENO has gone LOW.
ESYNC
EXI
PAEn Bus Sync
LVTTL ESYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAEnbus
OUTPUT duringPolledoperationofthePAEnbus.DuringPolledoperationeachdevicesqueuestatusflagsare
loadedontothePAEnbusoutputssequentiallybasedonRCLK.ThefirstRCLKrisingedgeloadsdevice1
ontoPAEn,thesecondRCLKrisingedgeloadsdevice2andsoon.DuringtheRCLKcyclethataselected
device is placed on to the PAEn bus, the ESYNC output will be HIGH.
PAEn/PRnBus
ExpansionIn
LVTTL The EXIinputis usedwhenmulti-queue devices are connectedinexpansionmode andPolled PAEn/
INPUT PRnbus operationhas beenselected. EXIofdevice ‘N’connects directlytoEXOofdevice ‘N-1’. The
EXI receives a token from the previous device in a chain. In single device mode the EXI input must be
tiedLOWifthePAEn/PRnbusisoperatedindirectmode.IfthePAEn/PRnbusisoperatedinpolledmode
theEXIinputmustbeconnectedtotheEXOoutputofthesamedevice.InexpansionmodetheEXIof
thefirstdeviceshouldbetiedLOW,whendirectmodeisselected.
EXO
PAEn/PRnBus
ExpansionOut
LVTTL EXOis anoutputthatis usedwhenmulti-queuedevices areconnectedinexpansionmodeandPolled
OUTPUT PAEn/PRnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.
ThispinpulsesHIGHwhendeviceNplacesitsPAEstatusontothePAEn/PRnbuswithrespecttoRCLK.
This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising
edgethefirstquadrantofdeviceN+1willbeloadedontothePAEn/PRnbus.Thiscontinuesthroughthe
chainandEXOofthelastdeviceisthenloopedbacktoEXIofthefirstdevice.TheESYNCoutputofeach
deviceinthechainprovides synchronizationtotheuserofthis loopingevent.
FF
Full Flag
LVTTL This pinprovides thefullflagoutputfortheactivequeue,thatis,thequeueselectedontheinputport
OUTPUT forwriteoperations,(selectedviaWCLK,WRADDbusandWADEN).OntheWCLKcycleafteraqueue
selection,thisflagwillshowthestatusofthenewlyselectedqueue.Datacanbewrittentothisqueueon
thenextcycleprovidedFF is HIGH.This flaghas High-Impedancecapability,this is importantduring
expansionofdevices,whentheFFflagoutputofupto8devicesmaybeconnectedtogetheronacommon
line.ThedevicewithaqueueselectedtakescontroloftheFFbus,allotherdevicesplacetheirFFoutput
intoHigh-Impedance.Whenaqueueselectionismadeonthewriteportthisoutputwillswitchfrom
High-ImpedancecontrolonthenextWCLKcycle.ThisflagissynchronizedtoWCLK.
(1)
FM
Flag Mode
LVTTL Thispinissetupbeforeamasterresetandmustnottoggleduringanydeviceoperation.Thestateofthe
INPUT FMpinduringMasterResetwilldetermine whetherthe PAFnandPAEnflagbusses operate ineither
PolledorDirectmode.Ifthis pinis HIGHthemodeis Polled,ifLOWthenitwillbeDirect.
FSTR
PAFn Flag Bus
Strobe
LVTTL IfdirectoperationofthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK
INPUT andtheWRADDbustoselectadeviceforitsqueuestobeplacedontothePAFnbusoutputs.Adevice
addressedviatheWRADDbus is selectedontherisingedgeofWCLKprovidedthatFSTRis HIGH.If
7
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
FSTR
(Continued) Strobe
PAFn Flag Bus
LVTTL Polledoperations has beenselected,FSTRshouldbetiedinactive,LOW.Note,thataPAFnflagbus
INPUT selectioncannotbemade,(FSTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
andSENO has gone LOW.
FSYNC
FXI
PAFn Bus Sync
LVTTL FSYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAFnbus
OUTPUT duringPolledoperationofthePAFnbus.DuringPolledoperationeachquadrantofqueuestatusflags
is loadedontothePAFnbus outputs sequentiallybasedonWCLK.ThefirstWCLKrisingedgeloads
device 1 on to the PAFn bus outputs, the second WCLK rising edge loads device 2 and so on. During
the WCLKcycle thata selecteddevice is placedontothe PAFnbus, the FSYNCoutputwillbe HIGH.
PAFnBus
ExpansionIn
LVTTL The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn
INPUT bus operation has been selected. FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receives a tokenfromthe previous device ina chain. Insingle device mode the FXIinputmustbe tied
LOWifthePAFnbusisoperatedindirectmode.IfthePAFnbusisoperatedinpolledmodetheFXIinput
mustbeconnectedtotheFXOoutputofthesamedevice.InexpansionmodetheFXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
FXO
PAFnBus
ExpansionOut
LVTTL FXOisanoutputthatisusedwhenmulti-queuedevicesareconnectedinexpansionmodeandPolled
OUTPUT PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This
pinpulsesHIGHwhendeviceNplacesitsPAFstatusontothePAFnbuswithrespecttoWCLK.Thispulse
(token)isthenpassedontothenextdeviceinthechain‘N+1’andonthenextWCLKrisingedgethefirst
quadrantofdevice N+1willbe loadedontothe PAFnbus. This continues throughthe chainandFXO
ofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdeviceinthe
chainprovidessynchronizationtotheuserofthisloopingevent.
(1)
ID[2:0]
Device ID Pins
LVTTL Forthe4Qmulti-queuedevicetheWRADDaddressbusis5bitsandRDADDaddressbusis6bitswide.
INPUT Whenaqueueselectiontakesplacethe3MSb’softhisaddressbusareusedtoaddressthespecificdevice
(theLSb’sareusedtoaddressthequeuewithinthatdevice).Duringwrite/readoperationsthe3MSb’s
oftheaddressarecomparedtothedeviceIDpins.ThefirstdeviceinachainofMulti-Queue’s(connected
inexpansionmode),maybesetupas‘000’,thesecondas‘001’andsoonthroughtodevice8whichis
‘111’,howevertheIDdoesnothavetomatchthedeviceorder.Insingledevicemodethesepinsshould
besetupas‘000’andthe3MSb’softheWRADDandRDADDaddressbussesshouldbetiedLOW.The
ID[2:0]inputssetuparespectivedevicesIDduringmasterreset.TheseIDpinsmustnottoggleduring
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
(1)
IW
InputWidth
LVTTL ThispinisusedinconjunctionwithOWandBMtosetuptheinputandoutputbuswidthstobeacombination
INPUT of x9, x18 or x36, (providing that one port is x36).
(1)
MAST
MasterDevice
LVTTL ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe
INPUT MasterdeviceoraSlave.IfthispinisHIGH,thedeviceisthemaster,ifitisLOWthenitisaSlave.Themaster
deviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgotoHigh-Impedance,
preventingbuscontention.Ifamulti-queuedeviceisbeingusedinsingledevicemode,thispinmust
be setHIGH.
MRS
OE
MasterReset
OutputEnable
LVTTL AmasterresetisperformedbytakingMRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired
INPUT aftermasterreset.
LVTTL TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontrolofthemulti-queue
INPUT dataoutputbus,Qout.Ifadevicehasbeenconfiguredasa“Master”device,theQoutdataoutputswill
beinaLowImpedanceconditioniftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbe
inHighImpedance.Ifadeviceisconfigureda“Slave”device,thentheQoutdataoutputswillalwaysbe
inHighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpointOEprovidesthree-
stateofthatrespectivedevice.
OV
OutputValidFlag
LVTTL Thisoutputflagprovidesoutputvalidstatusforthedatawordpresentonthemulti-queueflow-controldevice
OUTPUT dataoutputport,Qout.Thisflagistherefore,2-stagedelayedtomatchthedataoutputpathdelay.That
is,thereisa2RCLKcycledelayfromthetimeagivenqueueisselectedforreads,tothetimetheOVflag
representsthedatainthatrespectivequeue.Whenaselectedqueueonthereadportisreadtoempty,
the OV flagwillgoHIGH, indicatingthatdata onthe outputbus is notvalid. TheOV flagalsohas High-
Impedancecapability, requiredwhenmultipledevicesareusedandtheOVflagsaretiedtogether.
8
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
(1)
OW
OutputWidth
LVTTL ThispinissetupduringMasterResetandmustnottoggleduringanydeviceoperation.Thispinisused
INPUT inconjunctionwithIWandBMtosetupthedatainputandoutputbus widths tobeacombinationofx9,
x18 or x36, (providing that one port is x36).
PAE
Programmable
Almost-EmptyFlag
LVTTL ThispinprovidestheAlmost-Emptyflagstatusforthequeuethathasbeenselectedontheoutputport
OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queueisalmost-empty.ThisflagoutputmaybeduplicatedononeofthePAEnbuslines.Thisflagis
synchronizedtoRCLK.
PAEn/PRn Programmable
Almost-EmptyFlag
Bus/PacketReady
FlagBus
LVTTL On the 4Q device the PAEn/ PRn bus is 4 bits wide. During a Master Reset this bus is setup for either
OUTPUT AlmostEmptymodeorPacketmode.Thisoutputbusprovides PAE/PRnstatusofall4queues,within
aselecteddevice.DuringQueueread/writeoperationstheseoutputsprovideprogrammableempty
flagstatusorpacketreadystatus,ineitherdirectorpolledmode.Themodeofflagoperationisdetermined
duringmasterresetviathestateoftheFMinput.ThisflagbusiscapableofHigh-Impedancestate,this
isimportantduringexpansionofmulti-queuedevices.DuringdirectoperationthePAEn/PRnbusis
updatedtoshowthePAE/PRstatusofqueueswithinaselecteddevice.SelectionismadeusingRCLK,
ESTR and RDADD. During Polled operation the PAEn/PRn bus is loaded with the PAE/ PRn status
ofmulti-queueflow-controldevicessequentiallybasedontherisingedgeofRCLK.PAEorPRoperation
isdeterminedbythestateofPKTduringmasterreset.
PAF
Programmable
Almost-FullFlag
LVTTL ThispinprovidestheAlmost-Fullflagstatusforthequeuethathasbeenselectedontheinput portfor
OUTPUT writeoperations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselectedqueue
isalmost-full.ThisflagoutputmaybeduplicatedononeofthePAFnbuslines.Thisflagissynchronized
toWCLK.
PAFn
Programmable
LVTTL Onthe4QdevicethePAFnbusis4bitswide.ThisoutputbusprovidesPAFstatusofall4queues,within
Almost-FullFlagBus OUTPUT aselecteddevice.DuringQueueread/writeoperationstheseoutputsprovideprogrammablefullflag
status,ineitherdirectorpolledmode.Themodeofflagoperationisdeterminedduringmasterreset
viathestateoftheFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduring
expansionofmulti-queue devices. Duringdirectoperationthe PAFnbus is updatedtoshowthe PAF
statusofaqueueswithinaselecteddevice.SelectionismadeusingWCLK,FSTR,WRADDandWADEN.
DuringPolledoperationthePAFnbusisloadedwiththePAFstatusofmulti-queueflow-controldevices
sequentiallybasedontherisingedgeofWCLK.
(1)
PKT
PacketMode
LVTTL ThestateofthispinduringaMasterResetwilldeterminewhetherthepartisoperatinginPacketmode
INPUT providingbothaPacketReady(PR)outputandaProgrammableAlmostEmpty(PAE)discreteoutput,
or standard mode, providing a (PAE) output only. If this pin is HIGH during Master Reset the part will
operateinpacketmode,ifitisLOWthenalmostemptymode.Ifpacketmodehasbeenselectedtheread
portflagbusbecomespacketreadyflagbus,PRnandthediscretepacketreadyflag,PRisfunctional.
Ifalmostemptyoperationhasbeenselectedthentheflagbusprovidesalmostemptystatus,PAEnand
thediscretealmostemptyflag,PAEisfunctional,thePRflagisinactiveandshouldnotbeconnected.Packet
Readyutilizesusermarkedlocationstoidentifystartandendofpacketsbeingwrittenintothedevice.
PacketModecanonlybeselectedifboththeinputportwidthandoutputportwidthare36bits.
PR
PacketReadyFlag
LVTTL IfpacketmodehasbeenselectedthisflagoutputprovidesPacketReadystatusofthequeueselected
forreadoperations.DuringamasterresetthestateofthePKTinputdetermineswhetherPacketmode
ofoperationwillbeused.IfPacketmodeisselected,thentheconditionofthePRflagandOVsignalare
assertedindicates a packetis readyforreading. The usermustmarkthe startofa packetandthe end
ofapacketwhenwritingdataintoaqueue.UsingtheseStartOfPacket(SOP)andEndOfPacket
(EOP)markers,themulti-queuedevicesetsPRLOWifoneormore“complete”packetsareavailable
inthequeue.Acompletepacket(s)mustbewrittenbeforetheuserisallowedtoswitchqueues.
PRS
PartialReset
LVTTL APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial
INPUT Resetcanbe performedona queue, thatqueue mustbe selectedonboththe write portandreadport
2clockcycles beforetheresetis performed.APartialResetis thenperformedbytakingPRS LOWfor
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
thefirstmemorylocation,noneofthedevicesconfigurationwillbechanged.
9
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
Q[35:0]
Qout
DataOutputBus
LVTTL Thesearethe36dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge
OUTPUT ofRCLKprovidedthatRENis LOW,OEis LOWandthequeueis selected.Note,thatinPacketmode
Q32-Q35maybeusedaspacketmarkers,pleaseseepacketreadyfunctionaldiscussionformoredetail.
Duetobus matchingnotalloutputs maybeused,anyunusedoutputs shouldnotbeconnected.
RADEN
RCLK
ReadAddress
Enable
LVTTL The RADENinputis usedinconjunctionwithRCLKandthe RDADDaddress bus toselecta queue to
INPUT bereadfrom.AqueueaddressedviatheRDADDbusisselectedontherisingedgeofRCLKprovided
thatRADENisHIGH.RADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).RADEN
shouldnotbepermanentlytiedHIGH.RADENcannotbeHIGHforthesameRCLKcycleasESTR.Note,
thatareadqueueselectioncannotbemade,(RADENmustNOTgoactive)untilprogrammingofthepart
has beencompletedandSENO has goneLOW.
ReadClock
LVTTL Whenenabledby REN, the risingedge ofRCLKreads data fromthe selectedqueue via the output
INPUT bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
whileRADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthe
devicetobeplacedonthePAEn/PRnbusduringdirectflagoperation.Duringpolledflagoperationthe
PAEn/PRnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronizedtoRCLK.ThePAE,
PR andOV outputs are allsynchronizedtoRCLK. Duringdevice expansionthe EXOandEXIsignals
are based on RCLK. RCLK must be continuous and free-running.
RDADD
[5:0]
Read Address Bus
LVTTL For the 4Q device the RDADD bus is 6 bits. The RDADD bus is a dual purpose address bus. The first
INPUT functionofRDADDistoselectaqueuetobereadfrom.Theleastsignificant2bitsofthebus,RDADD[1:0]
areusedtoaddress1of4possiblequeueswithinamulti-queuedevice.Addresspin,RDADD[2]provides
the user with a Null-Q address. If the user does not wish to address one of the 4 queues, a Null-Q can
beaddressedusingthispin.TheNull-Qoperationisdiscussedinmoredetaillater.Themostsignificant
3bits,RDADD[5:3]areusedtoselect1of8possiblemulti-queuedevices thatmaybeconnectedin
expansionmode.These3MSb’swilladdressadevicewiththematchingIDcode.Theaddresspresent
ontheRDADDbuswillbeselectedonarisingedgeofRCLKprovidedthatRADENisHIGH,(note,that
datacanbeplacedontotheQoutbus,readfromthepreviouslyselectedqueueonthisRCLKedge).On
thenextrisingRCLKedgeafterareadqueueselect,adatawordfromthepreviousqueuewillbeplaced
ontotheoutputs,Qout,regardlessoftheRENinput.TwoRCLKrisingedgesafterreadqueueselect,data
willbeplacedontotheQoutoutputsfromthenewlyselectedqueue,regardlessofRENduetothefirst
wordfallthrougheffect.
The secondfunctionofthe RDADDbus is toselectthe device ofqueues tobe loadedontothe PAEn/
PRnbus duringstrobedflagmode.Themostsignificant3bits,RDADD[5:3]areagainusedtoselect1
of8possiblemulti-queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsRDADD[2:0]
aredon’t careduringdeviceselection.ThedeviceaddresspresentontheRDADDbuswillbeselected
onthe risingedge ofRCLKprovidedthatESTRis HIGH, (note, thatdata canbe placedontothe Qout
bus, read from the previously selected Queue on this RCLK edge). Please refer to Table 2for details
on RDADD bus.
REN
ReadEnable
LVTTL TheRENinputenablesreadoperationsfromaselectedqueuebasedonarisingedgeofRCLK.Aqueue
INPUT tobereadfromcanbeselectedviaRCLK,RADENandtheRDADDaddressbusregardlessofthestate
ofREN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecondRCLK
cycleafterqueueselectionregardlessofRENduetotheFWFToperation.Areadenableisnotrequired
to cycle the PAEn/PRn bus (in polled mode) or to select the device , (in direct mode).
SCLK
SerialClock
LVTTL Ifserialprogrammingofthemulti-queuedevicehasbeenselectedduringmasterreset,theSCLKinput
INPUT clockstheserialdatathroughthemulti-queuedevice.DatasetupontheSIinputisloadedintothedevice
ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed
theSCLKofalldevices shouldbeconnectedtothesamesource.
SENI
SerialInputEnable
LVTTL Duringserialprogrammingofamulti-queuedevice,dataloadedontotheSIinputwillbeclockedintothe
INPUT part(via a risingedge ofSCLK), providedthe SENI inputofthatdevice is LOW. Ifmultiple devices are
cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
loadingofagivendeviceiscomplete,itsSENOoutputgoesLOW,allowingthenextdeviceinthechain
tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.
10
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
SENO
SerialOutputEnable LVTTL Thisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingofthemulti-queuedevice
OUTPUT hasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO
willgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENOwillalso
goHIGH.WhentheSENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.
Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENOoutput
shouldbeconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogrammingofthe
firstdeviceiscomplete,SENOwillgoLOW,therebytakingthe SENIinputofthenextdeviceLOWand
soonthroughoutthe chain. Whena givendevice inthe chainis fullyprogrammedtheSENO output
essentiallyfollowstheSENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.
WhenthisoutputgoesLOW,serialloadingofalldeviceshasbeencompleted.
SI
SerialIn
LVTTL Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queue
INPUT devices. Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In
expansionmodetheserialdatainputisloadedintothefirstdeviceinachain.Whenthatdeviceisloaded
anditsSENOhasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpin
ofthefirstdeviceconnectstotheSIpinofthesecondandsoon.Themulti-queuedevicesetupregisters
areshiftregisters.
SO
SerialOut
LVTTL Thisoutputisusedinexpansionmodeandallowsserialdatatobepassedthroughdevicesinthechain
OUTPUT tocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdeviceinthe
chain. The SOofthe finaldevice ina chainshouldnotbe connected.
(2)
TCK
JTAGClock
LVTTL ClockinputforJTAGfunction.Oneoffourterminals requiredbyIEEEStandard1149.1-1990.Test
INPUT operationsofthedevicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedge
ofTCKandoutputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneeds
tobe tiedtoGND.
(2)
TDI
JTAGTestData
Input
LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
INPUT operation,testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,
IDRegisterandBypass Register.Aninternalpull-upresistorforces TDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData
Output
LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
OUTPUT operation,testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstruction
Register,IDRegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whilein
SHIFT-DR and SHIFT-IR controller states.
TMS(2)
JTAGModeSelect
JTAGReset
LVTTL TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthe
INPUT devicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST
LVTTL TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
INPUT resetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHforfiveTCKcycles.
IftheTAPcontrollerisnotproperlyresetthentheoutputswillalwaysbeinhigh-impedance.IftheJTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure
properqueue operation. Ifthe JTAGfunctionis notusedthenthis signalneeds tobe tiedtoGND. An
internalpull-upresistorforcesTRSTHIGHifleftunconnected.
WADEN
WCLK
WriteAddressEnable LVTTL TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto
INPUT bewritteninto.AqueueaddressedviatheWRADDbusisselectedontherisingedgeofWCLKprovided
thatWADENisHIGH.WADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).WADEN
shouldnotbepermanentlytiedHIGH.WADENcannotbeHIGHforthesameWCLKcycleasFSTR.Note,
thatawritequeueselectioncannotbemade,(WADENmustNOTgoactive)untilprogrammingofthe
parthas beencompletedandSENO has goneLOW.
WriteClock
LVTTL WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheselectedqueueviatheinputbus,
INPUT Din.ThequeuetobewrittentoisselectedviatheWRADDaddressbusandarisingedgeofWCLKwhile
WADENisHIGH.ArisingedgeofWCLKinconjunctionwithFSTRandWRADDwillalsoselectthedevice
tobeplacedonthePAFnbusduringdirectflagoperation.Duringpolledflagoperationthe PAFnbusis
cycledwithrespecttoWCLKandtheFSYNCsignalissynchronizedtoWCLK.ThePAFn,PAFandFF
outputsareallsynchronizedtoWCLK.DuringdeviceexpansiontheFXOandFXIsignalsarebasedon
WCLK.TheWCLKmustbecontinuousandfree-running.
11
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
WEN
WriteEnable
LVTTL The WEN input enables write operations to a selected queue based on a rising edge of WCLK.
INPUT AqueuetobewrittentocanbeselectedviaWCLK,WADENandtheWRADDaddress bus regardless
ofthestateofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLK
cycleafterqueueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFn
bus (in polled mode) or to select the device , (in direct mode).
WRADD
[4:0]
WriteAddressBus
LVTTL Forthe 4Qdevice the WRADDbus is 5bits. The WRADDbus is a dualpurpose address bus. The first
INPUT functionofWRADDistoselectaqueuetobewrittento.Theleastsignificant2bitsofthebus,WRADD[1:0]
areusedtoaddress1of4possiblequeueswithinamulti-queuedevice.Themostsignificant 3bits,
WRADD[4:2]areusedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansion
mode. These 3 MSb’s will address a device with the matching ID code. The address present on the
WRADDbuswillbeselectedonarisingedgeofWCLKprovidedthatWADENisHIGH,(note,thatdata
presentontheDinbuscanbewrittenintothepreviouslyselectedqueueonthisWCLKedgeandonthe
nextrisingWCLKalso,providingthatWENis LOW).TwoWCLKrisingedges afterwritequeueselect,
datacanbewrittenintothenewlyselectedqueue.
The secondfunctionofthe WRADDbus is toselectthe device ofqueues tobe loadedontothe PAFn
bus duringstrobedflagmode.Themostsignificant3bits,WRADD[4:2]areagainusedtoselect1of8
possiblemulti-queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsWRADD[1:0]
aredon’tcareduringdeviceselection.ThedeviceaddresspresentontheWRADDbuswillbeselected
ontherisingedgeofWCLKprovidedthatFSTRisHIGH,(note,thatdatacanbewrittenintothepreviously
selectedqueue onthis WCLKedge). Please refertoTable 1fordetails onthe WRADDbus.
VCC
GND
+3.3VSupply
GroundPin
Power These are VCC power supply pins and must all be connected to a +3.3V supply rail.
Ground These are Ground pins and must all be connected to the GND supply rail.
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 51-55 and Figures 31-33.
12
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Com'l & Ind'l
Unit
Symbol
Parameter
SupplyVoltage(Com'l/Ind'l)
Min. Typ.
Max.
3.45
0
Unit
V
VTERM
TerminalVoltage
with respect to GND
–0.5to+4.5
V
(1)
VCC
3.15
0
3.3
0
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
GND SupplyVoltage(Com'l/Ind'l)
V
VIH
VIL
TA
InputHighVoltage(Com'l/Ind'l)
InputLowVoltage(Com'l/Ind'l)
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
2.0
—
0
—
—
—
—
VCC+0.3
0.8
V
NOTE:
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
+70
°C
°C
TA
-40
+85
NOTE:
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant)
Symbol
Parameter
Min.
Max.
Unit
(1)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–10
–10
2.4
—
10
10
µA
µA
V
ILO(2)
VOH
Output Logic “1” Voltage, IOH = –8 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
StandbyCurrent
—
0.4
100
25
VOL
V
ICC1(3,4,5)
ICC2(3,6)
—
mA
mA
—
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 16 + 3.14*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
6. RCLK and WCLK, toggle at 20 MHz.
The following inputs should be pulled to GND: WRADD, RDADD, WADEN, RADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.
The following inputs should be pulled to VCC: WEN, REN, SENI, PRS, MRS, TDI, TMS and TRST.
All other inputs are don't care, and should be pulled HIGH or LOW.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
13
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AC TEST LOADS
6
V
CC/2
5
4
3
2
1
50
Ω
Z0 = 50Ω
I/O
5937 drw04
20 30 50 80 100
Capacitance (pF)
200
5937 drw04a
Figure 2a. AC Test Load
Figure 2b. Lumped Capacitive Load, Typical Derating
ACTESTCONDITIONS
InputPulseLevels
GND to 3.0V
1.5ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
1.5V
1.5V
See Figure 2a & 2b
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
V
IH
IL
OE
V
tOE &
tOLZ
tOHZ
Output
Normally
LOW
V
CC/2
V
CC/2
100mV
100mV
100mV
VOL
V
OH
Output
Normally
HIGH
100mV
VCC/2
VCC/2
5937 drw04b
14
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72V51236L6
IDT72V51246L6
IDT72V51256L6
IDT72V51236L7-5
IDT72V51246L7-5
IDT72V51256L7-5
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency (WCLK & RCLK)
DataAccessTime
—
0.6
6
166
3.7
—
—
—
—
—
—
—
—
—
—
—
—
3.7
3.7
3.7
10
—
0.6
7.5
3.5
3.5
2.0
0.5
2.0
0.5
10
133
4
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
—
—
—
—
—
—
—
—
—
—
—
—
4
Clock High Time
2.7
2.7
2
Clock Low Time
DataSetupTime
tDH
DataHoldTime
0.5
2
tENS
EnableSetupTime
tENH
tRS
EnableHoldTime
0.5
10
ResetPulseWidth
tRSS
ResetSetupTime
15
15
tRSR
tPRSS
tPRSH
tOLZ(OE-Qn)(2)
ResetRecoveryTime
10
10
PartialResetSetup
2.0
0.5
0.6
0.6
0.6
—
100
45
2.5
0.5
0.6
0.6
0.6
—
100
45
PartialResetHold
OutputEnabletoOutputinLow-Impedance
OutputEnabletoOutputinHigh-Impedance
OutputEnabletoDataOutputValid
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
(2)
tOHZ
4
tOE
4
fC
10
—
—
—
—
—
—
—
20
20
4
tSCLK
tSCKH
tSCKL
tSDS
—
—
—
—
—
—
—
20
Serial Clock High
Serial Clock Low
45
45
SerialDataInSetup
20
20
tSDH
tSENS
tSENH
tSDO
tSENO
tSDOP
tSENOP
tPCWQ
tPCRQ
tAS
Serial Data In Hold
1.2
20
1.2
20
SerialEnableSetup
SerialEnableHold
1.2
—
—
1.5
1.5
20
1.2
—
—
1.5
1.5
20
SCLK to Serial Data Out
SCLK to Serial Enable Out
SerialDataOutPropagationDelay
SerialEnablePropagationDelay
ProgrammingCompletetoWriteQueueSelection
ProgrammingCompletetoReadQueueSelection
AddressSetup
20
3.7
3.7
—
—
—
—
3.7
3.7
—
—
—
—
3.7
3.7
3.7
3.7
4
—
—
—
5
20
20
2.5
1
3.0
1
tAH
Address Hold
tWFF
tROV
tSTS
tSTH
tQS
Write Clock to Full Flag
ReadClocktoOutputValid
StrobeSetup
—
—
2
—
—
2
5
—
—
—
—
4
StrobeHold
0.5
2
0.5
2.5
0.5
0.6
0.6
0.6
0.6
QueueSetup
tQH
QueueHold
0.5
0.6
0.6
0.6
0.6
tWAF
tRAE
tPAF
tPAE
WCLK to PAF flag
RCLK to PAE flag
4
Write ClocktoSynchronous Almost-FullFlagBus
4
Read Clock to Synchronous Almost-Empty Flag Bus
4
NOTES:
1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order.
2. Values guaranteed by design, not currently tested.
15
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(CONTINUED)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72V51236L6
IDT72V51246L6
IDT72V51256L6
IDT72V51236L7-5
IDT72V51246L7-5
IDT72V51256L7-5
Symbol
Parameter
Min.
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
4.5
6
Max.
Min.
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
5.75
7.5
7.5
7.5
12
Max.
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
tPAELZ
RCLK to PAE Flag Bus to Low-Impedance
RCLK to PAE Flag Bus to High-Impedance
WCLK to PAF Flag Bus to Low-Impedance
WCLK to PAF Flag Bus to High-Impedance
WCLKtoFullFlagtoHigh-Impedance
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
—
—
—
—
—
—
—
(2)
tPAEHZ
4
(2)
tPAFLZ
4
(2)
tPAFHZ
4
(2)
tFFHZ
4
(2)
tFFLZ
WCLKtoFullFlagtoLow-Impedance
4
(2)
tOVLZ
RCLKtoOutputValidFlagtoLow-Impedance
RCLKtoOutputValidFlagtoHigh-Impedance
WCLK to PAF Bus Sync to Output
WCLK to PAF Bus Expansion to Output
RCLK to PAE Bus Sync to Output
4
(2)
tOVHZ
4
tFSYNC
tFXO
4
4
tESYNC
tEXO
4
RCLK to PAE Bus Expansion to Output
RCLK to Packet Ready Flag
4
tPR
4
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tSKEW5
tXIS
SKEW time between RCLK and WCLK for FF and OV
SKEW time between RCLK and WCLK for PAF and PAE
SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7]
SKEW time between RCLK and WCLK for PR and OV
SKEW time between RCLK and WCLK for OV when in Packet Mode
ExpansionInputSetup
—
—
—
—
—
—
—
6
6
10
1.0
0.5
1.3
0.5
tXIH
ExpansionInputHold
NOTES:
1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order.
2. Values guaranteed by design, not currently tested.
16
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
port on a rising edge of SCLK (serial clock), provided that SENI (serial in
enable),isLOW.Onceserialprogrammingofthedevicehasbeensuccessfully
completedthedevicewillindicatethisviatheSENO(serialoutputenable)going
active,LOW.Upondetectionofcompletionofprogramming,theusershould
ceaseallprogrammingandtakeSENIinactive,HIGH.Note,SENOfollowsSENI
onceprogrammingofadeviceiscomplete.Therefore,SENOwillgoLOWafter
programmingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENO
willalsogoHIGH.TheoperationoftheSOoutputissimilar,whenprogramming
ofagivendeviceiscomplete,theSOoutputwillfollowtheSIinput.
FUNCTIONALDESCRIPTION
MASTERRESET
AMasterResetisperformedbytogglingtheMRSinputfromHIGHtoLOW
toHIGH.Duringamasterresetallinternalmulti-queuedevicesetupandcontrol
registersareinitializedandrequireprogrammingeitherseriallybytheuservia
theserialport,orusingthedefaultsettings.Duringamasterresetthestateof
thefollowinginputsdeterminethefunctionalityofthepart,thesepinsshouldbe
held HIGH or LOW.
Ifdevicesarebeingusedinexpansionmodetheserialportsofdevicesshould
becascaded.Theusercanloadalldevicesviatheserialinputportcontrolpins,
SI & SENI, of the first device in the chain. Again, the user may utilize the ‘C’
programtogeneratetheserialbitstream,theprogrampromptingtheuserfor
the numberofdevices tobe programmed. The SENO andSO(serialout)of
thefirstdeviceshouldbeconnectedtotheSENI andSIinputs ofthesecond
devicerespectivelyandsoon,withtheSENO&SOoutputsconnectingtothe
SENI&SIinputsofalldevicesthroughthechain.Alldevicesinthechainshould
beconnectedtoacommonSCLK.Theserialoutputportofthefinaldeviceshould
be monitored by the user. When SENO of the final device goes LOW, this
indicates thatserialprogrammingofalldevices has beensuccessfullycom-
pleted.Upondetectionofcompletionofprogramming,theusershouldceaseall
programmingandtakeSENIofthefirstdeviceinthechaininactive,HIGH.
Asmentioned,thefirstdeviceinthechainhasitsserialinputportcontrolled
bytheuser,thisisthefirstdevicetohaveitsinternalregistersseriallyloaded
bytheserialbitstream.Whenprogrammingofthisdeviceiscompleteitwilltake
its SENOoutputLOWandbypasstheserialdataloadedontheSIinputtoits
SOoutput.Theserialinputoftheseconddeviceinthechainisnowloadedwith
thedatafromtheSOofthefirstdevice,whiletheseconddevicehasitsSENI
input LOW. This process continues through the chain until all devices are
programmedandtheSENO ofthefinaldevicegoesLOW.
PKT–PacketMode
FM – Flag bus Mode
IW,OW,BM–BusMatchingoptions
MAST – Master Device
ID0, 1, 2 – Device ID
DFM–Programmingmode,serialordefault
DF – Offset value for PAE and PAF
Onceamasterresethastakenplace,thedevicemustbeprogrammedeither
seriallyorviathedefaultmethodbeforeanyread/writeoperationscanbegin.
See Figure 4, Master Reset for relevant timing.
PARTIALRESET
APartialResetisameansbywhichtheusercanresetboththereadandwrite
pointers of a single queue that has been setup within a multi-queue device.
Beforeapartialresetcantakeplaceonaqueue,therespectivequeuemustbe
selectedonboththereadportandwriteportaminimumof2RCLKand2WCLK
cyclesbeforethePRSgoesLOW.Thepartialresetisthenperformedbytoggling
thePRSinputfromHIGHtoLOWtoHIGH,maintainingtheLOWstateforatleast
oneWCLKandoneRCLKcycle.Onceapartialresethastakenplaceaminimum
of3WCLKand3RCLKcyclesmustoccurbeforeenabledwritesorreadscan
occur.
Once all serial programming has been successfully completed, normal
operations,(queueselectionsonthereadandwriteports)maybegin.When
connectedinexpansionmode,theIDT72V51236/72V51246/72V51256de-
vicesrequireatotalnumberofseriallyloadedbitsperdevicetocompleteserial
programming,(SCLKcycleswithSENIenabled),calculatedby:n[19+(Qx72)]
whereQis thenumberofqueues theuserwishes tosetupwithinthedevice,
where n is the number of devices in the chain.
APartialResetonlyresets thereadandwritepointers ofagivenqueue,a
partialresetwillnoteffecttheoverallconfigurationandsetupofthemulti-queue
deviceandits queues.
See Figure 5, PartialReset for relevant timing.
SERIAL PROGRAMMING
Themulti-queueflow-controldeviceisafullyprogrammabledevice,provid-
ingtheuserwithflexibilityinhowqueuesareconfiguredintermsofthenumber
of queues, depth of each queue and position of the PAF/PAE flags within
respectivequeues.Alluserprogrammingisdoneviatheserialportafteramaster
resethas takenplace. Internallythe multi-queue device has setupregisters
whichmustbeseriallyloaded,theseregisterscontainvaluesforeveryqueue
within the device, such as the depth and PAE/PAF offset values. The
IDT72V51236/72V51246/72V51256devices are capable ofupto4queues
andthereforecontain4setsofregistersforthesetupofeachqueue.
DuringaMasterResetiftheDFM(DefaultMode)inputisLOW,thenthedevice
willrequire serialprogrammingbythe user. Itis recommendedthatthe user
utilizea‘C’programprovidedbyIDT,thisprogramwillprompttheuserforall
informationregardingthemulti-queuesetup.Theprogramwillthengenerate
aserialbitstreamwhichshouldbeseriallyloadedintothedeviceviatheserial
port.FortheIDT72V51236/72V51246/72V51256devicestheserialprogram-
mingrequiresatotalnumberofseriallyloadedbitsperdevice,(SCLKcycles
withSENIenabled),calculatedby:19+(Qx72)whereQisthenumberofqueues
the user wishes to setup within the device. Please refer to the separate
ApplicationNote,AN-303forrecommendedcontroloftheserialprogramming
port.
SeeFigure6,SerialPortConnectionandFigure7,SerialProgrammingfor
connectionandtiminginformation.
DEFAULTPROGRAMMING
Duringa MasterResetifthe DFM(DefaultMode)inputis HIGHthe multi-
queuedevicewillbeconfiguredfordefaultprogramming,(serialprogramming
is not permitted). Default programming provides the user with a simpler,
howeverlimitedmeansbywhichtosetupthemulti-queueflow-controldevice,
rather than using the serial programming method. The default mode will
configure a multi-queue device such that the maximum number of queues
possiblearesetup,withallofthepartsavailablememoryblocksbeingallocated
equallybetweenthequeues.ThevaluesofthePAE/PAFoffsetsisdetermined
bythe state ofthe DF(default)pinduringa masterreset.
FortheIDT72V51236/72V51246/72V51256devicesthedefaultmodewill
setup 4 queues, each queue being 4,096 x 36, 8,192 x 36 and 16,384 x 36
deep respectively. For both devices the value of the PAE/PAF offsets is
determinedatmasterresetbythestateoftheDFinput.IfDFisLOWthenboth
the PAE & PAF offset will be 8, if HIGH then the value is 128.
WhenconfiguringtheIDT72V51236/72V51246/72V51256devicesinde-
faultmodetheusersimplyhastoapplyWCLKcyclesafteramasterreset,until
SENOgoesLOW,thissignalsthatdefaultprogrammingiscomplete.Theseclock
Once the master reset is complete and MRS is HIGH, the device can be
seriallyloaded.DatapresentontheSI(serialin),inputisloadedintotheserial
17
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
cyclesarerequiredforthedevicetoloaditsinternalsetupregisters. Whena while write address enable (WADEN) is HIGH. The state of WEN does not
singlemulti-queueisused,thecompletionofdeviceprogrammingissignaled impactthequeueselection.Thequeueselectionisrequires2WCLKcycles.
bytheSENOoutputofadevicegoingfromHIGHtoLOW.Note,thatSENImust Allsubsequentdatawriteswillbetothisqueueuntilanotherqueueisselected.
beheldLOWwhenadeviceis setupfordefaultprogrammingmode.
Standardmodeoperationisdefinedasindividualwordswillbewrittentothe
Whenmulti-queuedevicesareconnectedinexpansionmode,theSENIof deviceasopposedtoPacketModewherecompletepacketsmaybewritten.
thefirstdeviceinachaincanbeheldLOW.TheSENOofadeviceshouldconnect Thewriteportisdesignedsuchthat100%busutilizationcanbeobtained.This
totheSENIofthenextdeviceinthechain.TheSENOofthefinaldeviceisused means that data can be written into the device on every WCLK rising edge
toindicatethatdefaultprogrammingofalldevicesiscomplete.Whenthefinal including the cycle that a new queue is being addressed.
SENO goes LOW normal operations may begin. Again, all devices will be
Changingqueuesrequiresaminimumof2WCLKcyclesonthewriteport
programmedwiththeirmaximumnumberofqueuesandthememorydivided (seeFigure9,WriteQueueSelect,WriteOperationandFullflagOperation).
equally between them. Please refer to Figure 8, DefaultProgramming.
WADENgoeshighsignalingachangeofqueue(clockcycle“A”).Theaddress
onWRADDatthattimedeterminesthenextqueue.Datapresentedduringthat
cycle (“A”) and the next cycle (“B”), will be written to the active (old) queue,
providedWEN is active LOW.IfWENis HIGH(inactive)forthese twoclock
READING AND WRITING TO THE IDT MULTI-QUEUE
FLOW-CONTROL DEVICE
The IDT72V51236/72V51346/72V51256 multi-queue flow-control de- cycles,datawillnotbewrittenintothepreviousqueue.Thewriteportdiscrete
vices canbe configuredintwodistinctmodes, namelyStandardMode and fullflagwillupdatetoshowthefullstatusofthenewlyselectedqueue(QX)at
PacketMode.
thislastcycle’srisingedge(“B”).Datapresentonthedatainputbus(Din),can
bewrittenintothenewlyselectedqueue(QX)ontherisingedgeofWCLKon
the secondcycle (“C”)followinga change ofqueue, provided WEN is LOW
andthenewqueueisnotfull.Ifthenewlyselectedqueueisfullatthepointof
itsselection,anywritestothatqueuewillbeprevented.Datacannotbewritten
intoafullqueue.
STANDARD MODE OPERATION (PKT = LOW on Master Reset)
WRITE QUEUE SELECTION AND WRITE OPERATION
(STANDARDMODE)
The IDT72V51236/72V51346/72V51256 multi-queue flow-control de-
Refer to Figure 9, Write Queue Select, Write Operation and Full flag
vicescanbeconfigureduptoamaximumof4queuesintowhichdatacanbe Operation,Figure10,WriteOperations&FirstWordFallThroughfortiming
writtenviaacommonwriteportusingthedatainputs(Din),writeclock(WCLK) diagrams and Figure 11, Full Flag Timing in Expansion Mode for timing
andwriteenable(WEN).Thequeuetobewrittenisselectedbytheaddress diagrams.
present on the write address bus (WRADD) during a rising edge on WCLK
TABLE 1 — WRITE ADDRESS BUS, WRADD[4:0]
Operation WCLK WADEN FSTR
WRADD[4:0]
4 3 2
Device Select
(Compared to
ID0,1,2)
1 0
Write Queue Address
(2 bits = 4 Queues)
Write Queue
1
0
Select
4 3 2
1 0
PAFn Flag Bus
Device Select
0
1
Device Select
(Compared to
ID0,1,2)
X
X
5937 drw05
18
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
READQUEUESELECTIONANDREADOPERATION(STANDARDMODE) queue(QF).Theinternalpipelineisalsoloadedatthistime(“D”)withthelast
The IDT72V51236/72V51346/72V51256 multi-queue flow-control de- wordfromtheprevious(old)queue(QP)aswellasthenextwordfromthenew
vicescanbeconfigureduptoamaximumof4queueswhichdatacanberead queue(QF).Bothofthesewordswillfallthroughtotheoutputregister(provided
viaacommonreadportusingthedataoutputs(Qout),readclock(RCLK)and theOEisasserted)consecutively(cycles“E”and“F”respectively)following
readenable(REN).Anoutputenable,OEcontrolpinisalsoprovidedtoallow theselectionofthenewqueueregardlessofthestateofREN,unlessthenew
High-ImpedanceselectionoftheQoutdataoutputs.Themulti-queuedevice queue(QF)isempty.Ifthenewlyselectedqueueisempty,anyreadsfromthat
read port operates in a mode similar to “First Word Fall Through” on a queuewillbeprevented.Datacannotbereadfromanemptyqueue.Thelast
SuperSyncIDTFIFO,butwiththeaddedfeatureofdataoutputpipelining(see wordinthedataoutputregister(fromthepreviousqueue),willremainonthe
Figure 10, Write Operations & First Word Fall Through). The queue to be data bus,butthe outputvalidflag, OV willgoHIGH,toindicate thatthe data
readisselectedbytheaddresspresentedonthereadaddressbus(RDADD) presentisnolongervalid.Thispipeliningeffectprovidestheuserwith100%
duringarisingedgeonRCLKwhilereadaddressenable(RADEN)isHIGH. bus utilization,andbrings aboutthepossibilitythata“NULL”queuemaybe
ThestateofRENdoesnotimpactthequeueselection.Thequeueselection requiredwithinamulti-queuedevice.Nullqueueoperationisdiscussedinthe
isrequires2RCLKcycles.Allsubsequentdatareadswillbefromthisqueue nextsection.RememberthatOEallowstheusertoplacethedataoutputbus
untilanotherqueueisselected.
(Qout)intoHigh-Impedanceandthedatacanbereadintotheoutputregister
Standardmodeoperationisdefinedasindividualwordswillbereadfrom regardlessofOE.
thedeviceasopposedtoPacketModewherecompletepacketsmayberead.
RefertoTable2,forReadAddressBusarrangement.Also,refertoFigures
Thereadportisdesignedsuchthat100%busutilizationcanbeobtained.This 12, 14, and 15 for read queue selection and read port operation timing
means that data can be read out of the device on every RCLK rising edge diagrams.
including the cycle that a new queue is being addressed.
ChangingqueuesrequiresaminimumoftwoRCLKcyclesonthereadport PACKET MODE OPERATION (PKT = HIGH on Master Reset)
(see Figure 12, Read Queue Select, Read Operation). RADEN goes high
The Packet mode operation provides the capability where, user defined
signalingachangeofqueue(clockcycle“D”).TheaddressonRDADDatthat packetsorframescanbewrittentothedeviceasopposedtoStandardmode
timedeterminesthenextqueue.Datapresentedduringthatcycle(“D”)willbe whereindividualwordsarewritten.Forclarification,inPacketMode,apacket
readat“D”(+tA),canbereadfromtheactive(old)queue(QP),providedREN canbewrittentothedevicewiththestartinglocationdesignatedasTransmit
isactiveLOW.IfRENisHIGH(inactive)forthisclockcycle,datawillnotberead StartofPacket(TSOP)andtheendinglocationdesignatedasTransmitEnd
from the previous queue. The next cycle’s rising edge (“E”), the read port of Packet (TEOP). In conjunction, a packet read from the device will be
discreteemptyflagwillupdatetoshowtheemptystatusofthenewlyselected designatedasReceiveStartofPacket(RSOP)andaReceiveEndofPacket
TABLE 2 — READ ADDRESS BUS, RDADD[5:0]
Operation RCLK RADEN ESTR
RDADD[5:0]
5 4 3
2
1 0
Read Queue
1
0
Device Select
(Compared to
ID0,1,2)
Null-Q
Read Queue Address
Select
Select Pin (2 bits = 4 Queues)
5 4 3
2
1 0
Flag Bus Device
Selection
0
1
Device Select
(Compared to
ID0,1,2)
X
X
X
5937 drw06
19
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
(REOP).Theminimumsizeforapacketisfourwords(SOP,twowordsofdata aqueuechangerequestismade(“B”).IfRENisHIGH(inactive)forthisclock
andEOP).Thealmostemptyflagbusbecomesthe“PacketReady”PRflag cycle(“I”),datawillnotbereadfromthepreviousqueue(QB).Inapplications
buswhenthedeviceisconfiguredforpacketmode.Validpacketsareindicated wherethemulti-queueflow-controldeviceis connectedtoasharedbus,an
when both PR and OV are asserted.
output enable, OE control pin is also provided to allow High-Impedance
selectionofthedataoutputs(Qout).WithreferencetoFigure17whenchanging
WRITEQUEUESELECTIONANDWRITEOPERATION(PACKETMODE) queues, a packetmarker(SOPorEOP)shouldnotbe readoncycle (“C”or
Itisrequiredthatafullpacketbewrittentoaqueuebeforemovingtoadifferent “I”). Readinga SOPorEOPshouldnotoccurduringthe cycles requiredfor
queue.Thedevicerequirestwocyclestochangequeues.Packetmode,has aqueuechange.Itisalsorecommendedthataqueuechangeshouldnotoccur
2restrictions:<1>Anextraword(orfillerword)isrequiredtobewrittenafter oncethereadingofthepackethascommenced.TheEOPmarkerofthepacket
eachpacketonthecyclefollowingthequeuechangetoensuretheRSOPin priortoaqueuechangeshouldbereadonorbeforethequeuechange.Ifthe
theoldqueueisnotreadoutonaqueuechangebecauseofthefirstwordfall EOPwordisreadbeforeaqueuechange,RENcanbepulledhightodisable
through.<2>NoSOP/EOPis allowedtoread/writtenatcycle(“C”or“I”)the furtherreads.Whenthequeuechangeisinitiated,thefillerwordwritteninto
nextcycleafteraqueuechange.Forclockfrequency(fs)of133MHzandbelow thecurrentqueueaftertheEOPwordwillfallthroughfollowedbyandthefirst
seeApplicationNoteAN-398.Inthismode,thewriteportmaynotobtain100% word from the new queue.
busutilization
Refer to Figure 17, Reading in Packet Mode during a Queue Change as
ChangingqueuesrequiresaminimumoftwoWCLKcyclesonthewriteport well as Figures 12, 14, and 15 for timing diagrams and Table 2, for Read
(see Figure 16, Writing in Packet Mode during a Queue Change). WADEN Addressbusarrangement.
goes highsignalingachangeofqueue(clockcycle“B”or“H”).Theaddress
Note,thealmostemptyflagbusbecomesthe“PacketReady”flagbuswhen
on WRADD at the rising edge of WCLK determines the next queue. Data thedeviceisconfiguredforpacketmode.
presented on Din during that cycle (“B” or “H”) can continue to be written to
theactive(old)queue(QA orQB respectively),providedWENisLOW(active). PACKETREADYFLAG
IfWENisHIGH(inactive)forthisclockcycle(H),datawillnotbewritteninto
Themulti-queueflow-controldeviceprovidestheuserwithaPacketReady
thepreviousqueue(QB).Thecyclefollowingarequestforqueuechange(“C” feature. Duringa MasterResetthe logic“1”(HIGH)onthe PKTinputsignal
or “I”) will require a filler word to be written to the device. This can be done (packetmodeselect),configuresthedeviceinpacketmode.ThePRdiscrete
byclockingtheTEOPtwiceorbywritingafillerword.Inpacketmode,themulti- flag,providesapacketreadystatusoftheactivequeueselectedontheread
queue is designed under the 2 restrictions listed previously. Note, an port.Apacketreadystatusisindividuallymaintainedonallqueues;however
erroneousPacketReadyflagmayoccuriftheEOPorSOPmarkershowsup onlythequeueselectedonthereadporthasitspacketreadystatusindicated
atthenextcycleafteraqueuechange.TopreventanerroneousPacketReady onthePRoutputflag.Apacketisavailableontheoutputforreadingwhenboth
flagfromoccurringafillerwordshouldbewrittenintotheoldqueueatthelast PRandOVareassertedLOW.Iflessthanafullpacketisavailable,thePRflag
clockcycleofwriting.ItisimportanttoknowthatnoSOPorEOPmaybewritten willbeHIGH(packetnotready).Inpacketmode,nowordscanbereadfrom
intothedeviceduringthiscycle(“C”or“I”).Thewriteportdiscretefullflagwill aqueueuntilacompletepackethasbeenwrittenintothatqueue,regardless
updatetoshowthefullstatusofthenewlyselectedqueue(QB)atthislastcycle’s ofREN.
rising edge (“C” or “I”). Data values presented on the data input bus (Din),
WhenpacketmodeisselectedtheProgrammableAlmostEmptybus,PAEn,
canbewrittenintothenewlyselectedqueue(QX)ontherisingedgeofWCLK becomesthePacketReadybus,PRn.WhenconfiguredinDirectBus(FM=
on the second cycle (“D” or “J”) following a request for change of queue, LOWduringa masterreset),the PRnbus provides packetreadystatus in8
providedWENisLOW(active)andthenewqueueisnotfull.Ifaselectedqueue queue increments. The PRn bus supports either Polled or Direct modes of
isfull(FFisLOW),thenwritestothatqueuewillbeprevented.Note,datacannot operation.ThePRnmodeofoperationisconfiguredthroughtheFlagMode
be writtenintoa fullqueue.
(FM) bit during a Master Reset.
Refer to Figure 16, Writing in Packet Mode during a Queue Change and
Whenthemulti-queueisconfiguredforpacketmodeoperation,thedevice
Figure18,DataInput(Transit)packetmodeofOperationfortimingdiagrams. mustalsobeconfiguredfor36bitwritedatabusand36bitreaddatabus.The
twomostsignificantbitsofthe36-bitdatabusareusedas“packetmarkers”.
READQUEUESELECTIONANDREADOPERATION(PACKETMODE) OnthewriteportthesearebitsD34(TransmitStartofPacket,)D35(Transmit
InPacketModeitisrequiredthatafullpacketisreadfromaqueuebefore EndofPacket)andonthereadportQ34,Q35.Allfourbitsaremonitoredby
movingtoadifferentqueue.Thedevicerequirestwocyclestochangequeues. thepacketcontrollogicas datais writtenintoandreadoutfromthequeues.
In Packet Mode, there are 2 restrictions <1> An extra word (or filler word) Thepacketreadystatusforindividualqueuesisthendeterminedbythepacket
shouldhavebeeninsertedintothedatastreamaftereachpackettoinsurethe ready logic.
RSOPintheoldqueueisnotreadoutonaqueuechangebecauseofthefirst
OnthewriteportD34isusedto“mark”thefirstwordbeingwrittenintothe
word fall through and this word should be discarded. <2> No EOP/SOP is selectedqueueasthe“TransmitStartofPacket”,TSOP.Tofurtherclarify,when
allowed to be read/written at cycle (“C” or “I”) the next cycle after a queue the userrequires a wordbeingwrittentobe markedas the startofa packet,
change).Forclockfrequencyof133MhzandbelowseeApplicationNoteAN- the TSOPinput(D34)mustbe HIGHforthe same WCLKrisingedge as the
398. Inthis mode, the readportmaynotobtain100%bus utilization
ChangingqueuesrequiresaminimumoftwoRCLKcyclesonthereadport dataitwas writteninuntilthewordis readoutofthequeueviathereadport.
(seeFigure17,ReadinginPacketModeduringaQueueChange).RADEN OnthewriteportD35isusedto“mark”thelastwordofthepacketcurrently
wordthatis written. The TSOPmarkeris storedinthe queue alongwiththe
goes high signaling a change of queue (clock cycle “B” or “I”). The address beingwrittenintotheselectedqueueasthe“TransmitEndofPacket”TEOP.
onRDADDatthe risingedge ofRCLKdetermines the queue.As illustrated When the user requires a word being written to be marked as the end of a
inFigure 17duringcycle (“B”),data canbe readfromthe active (old)queue packet,theTEOPinputmustbeHIGHforthesameWCLKrisingedgeasthe
(QA)), provided both REN and OE are LOW (active) simultaneously with wordthatiswrittenin.TheTEOPmarkerisstoredinthequeuealongwiththe
changingqueues.REOPforpacketlocatedinqueue(QA)mustbereadbefore dataitwas writteninuntilthewordis readoutofthequeueviathereadport.
20
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 5 — PACKET MODE VALID BYTE
BYTE D
BYTE C
BYTE B
BYTE A
TMOD1 (D33)
RMOD1 (Q33)
TMOD2 (D32)
RMOD2 (Q32)
VALID BYTES
0
0
1
1
0
1
0
1
A, B, C, D
A
A, B
A, B, C
5937 drw07
NOTE:
Packet Mode is only available when the Input Port and Output Port are 36 bits wide.
Thepacketreadylogicmonitorsallstartandendofpacketmarkersbothas thattheendofpacketisafixed(known)numberofreadsawayfromtheend
they enter respective queues via the write port and as they exit queues via of packet. This is a useful feature when due to latencies within the system,
the readport. The multi-queue internallogicincrements anddecrements a monitoringtheREOPmarkeralonedoesnotprevent“overreading”ofthedata
packet counter, which is provided for each queue. The functionality of the fromthequeueselected.Forexample,anAEOPmarkerset4writesbefore
packetreadylogicprovidesstatusastowhetheratleastonefullpacketofdata the TEOP marker provides the device connected to the read port with and
isavailablewithintheselectedqueue.Apartialpacketinaqueueisregarded “almostendofpacket”indication4cyclesbeforetheendofpacket.
asapacketnotreadyandPR(activeLOW)willbeHIGH.InPacketmode,no TheAEOPcanbesetanynumberofwordsbeforetheendofpacketdetermined
wordscanbereadfromaqueueuntilatleastonecompletepackethasbeen byuserrequirements orlatencies involvedinthe system.
writtenintothequeue,regardlessofREN.Forexample,ifaTSOPhasbeen
SeeFigure17, ReadinginPacketModeduringaQueueChange,Figure
writtenandsomenumberofwordslateraTEOPiswrittenafullpacketofdata 18, Data Input (Transmit) Packet Mode of Operation and Figure 19, Data
is deemed to be available, and the PR flag and OV will go active LOW. Output (Receive) Packet Mode of Operation.
Consequentlyifreadsbeginfromaqueuethathasonlyonecompletepacket
andtheRSOPisdetectedontheoutputportasdataisbeingreadout,PRwill PACKETMODE–MODULOOPERATION
goinactiveHIGH.OVwillremainLOWindicatingthereisstillvaliddatabeing
The internal packet ready control logic performs no operation on these
readoutofthatqueueuntiltheREOPisread.Theusermayproceedwiththe modulobits,theyareonlyinformationalbitsthatarepassedthroughwiththe
readingoperationuntilthe currentpackethas beenreadoutandnofurther respectivedatabyte(s).
completepacketsareavailable.Ifduringthattimeanothercompletepackethas
Whenutilizingthemulti-queueflow-controldeviceinpacketmode,theuser
beenwrittenintothequeueandthePRflagwillagaingoneactive,thenreads mayalsowanttoconsidertheimplementationof“Modulo”operationor“valid
fromthenewpacketmayfollowafterthecurrentpackethasbeencompletely byte marking”. Modulo operation may be useful when the packets being
readout.
transferredthroughaqueueareinaspecificbytearrangementeventhough
Thepacketcountersthereforelookforstartofpacketmarkersfollowedby thedatabuswidthis36bits.InModulooperationtheusercanconcatenatebytes
endofpacketmarkers andregarddata inbetweenthe TSOPandTEOPas toformaspecificdatastringthroughthemulti-queuedevice.Apossiblescenario
afullpacketofdata.Thepacketmonitoringhasnolimitationastohowmany is where a limited number of bytes are extracted from the packet for either
packetsarewrittenintoaqueue,theonlyconstraintisthedepthofthequeue. analysisorfilteredforsecurityprotection.Thiswillonlyoccurwhenthefirst36
Note,thereisaminimumallowablepacketsizeoffourwords,inclusiveofthe bitwordofapacketiswritteninandthelast36bitwordofpacketiswrittenin.
TSOP marker and TEOP marker.
The packet logic does expect a TSOP marker to be followed by a TEOP specificdatawithintheQueue.
marker. Onthewriteportdatainputbits,D32(transmitmodulobit2,TMOD2)and
The modulo operation is a means by which the user can mark and identify
If a second TSOP marker is written after a first, it is ignored and the logic D33(transmitmodulobit1,TMOD1)canbeusedasdatamarkers.Anexample
regardsdatabetweenthefirstTSOPandthefirstsubsequentTEOPasthefull of this could be to use D32 and D33 to code which bytes of a word are part
packet. The same is true for TEOP; a second consecutive TEOP mark is of the packet that is also being marked as the “Start of Marker” or “End of
ignored.Onthereadsidetheusershouldregardapacketasbeingbetween Marker”.Converselyonthereadportwhenreadingoutthesemarkedwords,
the first RSOP and the first subsequent REOP and disregard consecutive dataoutputsQ32(receivemodulobit2,RMOD2)andQ33(receivemodulo
RSOP markers and/or REOP markers. This is why a TEOP may be written bit1,RMOD1)willpassonthebytevalidityinformationforthatword.Referto
twice,usingthe secondTEOPas the fillerword.
Table5foroneexampleofhowthemodulobitsmaybesetupandused.See
Asanexample,theusermayalsowishtoimplementtheuseofan“Almost Figure 18, Data Input (Transmit) Packet Mode of OperationandFigure 19,
EndofPacket”(AEOP)marker.Forexample,theAEOPcanbeassignedto Data Output (Receive) Packet Mode of Operation.
datainputbitD33.ThepurposeofthisAEOPmarkeristoprovideanindicator
21
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NULL QUEUE OPERATION (OF THE READ PORT)
address.Whenlogicallyexpandedwithmultipleparts,eachdeviceisstatically
Pipeliningofdatatotheoutputportenablesthedevicetoprovide100%bus setupwitha unique chipIDcode onthe IDpins, ID0, ID1, andID2. Adevice
utilizationinstandardmode.Datacanbereadoutofthemulti-queueflow-control isselectedwhenthe3MostSignificantbitsoftheWRADDaddressbusmatches
device on every RCLK cycle regardless of queue switches or other opera- a 3-bit ID code. The maximum logical expansion is 32 queues (4 queues x
tions.Thedevicearchitectureissuchthatthepipelineisconstantlyfilledwith 8devices)oraminimumof8queues(1queueperdevicex8devices),each
thenextwordsinaselectedqueuetobereadout,againproviding100%bus ofthemaximumsizeoftheindividualmemorydevice.
utilization.Thistypeofarchitecturedoesassumethattheuserisconstantly
Note:TheWRADDbusisalsousedinconjunctionwithFSTR(almostfull
switchingqueuessuchthatduringaqueueswitch,thelastdatawordrequired flag bus strobe), to address the almost full flag bus during direct mode of
fromthepreviousqueuewillfallthroughthepipelinetotheoutput.
Note,thatifreadsceaseattheemptyboundaryofaqueue,thenthelastword
willautomaticallyflowthroughthepipelinetotheoutput.
operation.
RefertoTable1,forWriteAddressbusarrangement.Also,refertoFigure
11, Full Flag Timing Expansion Mode, Figure 13, Output Valid Flag Timing
The Null-Q is selected via read port address space RDADD[2]. The (In Expansion Mode), and Figure 30, Multi-Queue Expansion Diagram, for
RDADD[5:0]busshouldbeaddressedwithxxx1xx,thisaddressistheNull-Q. timingdiagrams.
A null queue can be selected when no further reads are required from a
previouslyselectedqueue.Changingtoanullqueuewillcontinuetopropagate BUS MATCHING OPERATION
data in the pipeline to the previous queue’s output. The Null Q can remain
selecteduntiladatabecomesavailableinanotherqueueforreading.TheNull- Duringamasterresetofthemulti-queuethestateofthethreesetuppins,BM
Qcanbe utilizedineitherstandardorpacketmode. (BusMatching),IW(InputWidth)andOW(OutputWidth)determinetheinputand
BusMatchingoperationbetweentheinputportandoutputportisavailable.
Note:Iftheuserswitchesthereadporttothenullqueue,thisqueueisseen outputportbuswidthsaspertheselectionsshowninTable3,“BusMatching
asandtreatedasanemptyqueue,thereforeafterswitchingtothenullqueue Set-up”.9bitbytes,18bitwordsand36bitlongwordscanbewrittenintoand
thelastwordfromthepreviousqueuewillremainintheoutputregisterandthe read from the queues provided that at least one of the ports is setup for x36
OV flagwillgoHIGH,indicatingdata is notvalid.
operation.Whenwritingtoorreadingfromthemulti-queueinabusmatching
TheNullqueueoperationonlyhassignificancetothereadportofthemulti- mode, the device orders data in a “Little Endian” format. See Figure 3, Bus
queue, it is a means to force data through the pipeline to the output. Null Q MatchingByteArrangementfordetails.
selectionandoperationhasnomeaningonthewriteportofthedevice.Also,
refer to Figure 20, Read Operation and Null Queue Select for diagram.
TheFullflagandAlmostFullflagoperationis always basedonwrites and
readsofdatawidthsdeterminedbythewriteportwidth.Forexample,iftheinput
portisx36andtheoutputportisx9,thenfourdatareadsfromafullqueuewill
berequiredtocausethefullflagtogoHIGH(queuenotfull).Conversely,the
PAFn FLAG BUS OPERATION
TheIDT72V51236/72V51246/72V51256multi-queueflow-controldevices OutputValidflagandAlmostEmptyflagoperationsarealwaysbasedonwrites
can be configured for up to 4 queues, each queue having its own almost full andreadsofdatawidthsdeterminedbythereadport.Forexample,iftheinput
status.Anactivequeuehasitsflagstatusoutputtothediscreteflags,FFandPAF, portis x18andthe outputportis x36, twowrite operations willbe requiredto
onthewriteport.Queuesthatarenotselectedforawriteoperationcanhave causetheoutputvalidflagofanemptyqueuetogoLOW,outputvalid(queue
theirPAFstatusmonitoredviathePAFnbus.ThePAFnflagbusis4bitswide, isnotempty).
so that all 4 queues can have their status output to the bus. When a single
Note,thattheinputportservesallqueueswithinadevice,asdoestheoutput
multi-queuedeviceisusedanywherefrom1to4queuesmaybeset-upwithin port,thereforetheinputbuswidthtoallqueuesisequal(determinedbytheinput
thepart,eachqueuehavingitsowndedicatedPAFflagoutputonthePAFnbus. portsize)andtheoutputbuswidthfromallqueuesisequal(determinedbythe
Queues 1 through 4 have their PAF status to PAF[0] through PAF[3] outputportsize).
respectively. If less than 4 queues are used then only the associated PAFn
outputswillberequired,unusedPAFnoutputswillbedon’tcareoutputs.When
TABLE 3 BUS-MATCHING SET-UP
devices are connected in expansion mode the PAFn flag bus can also be
BM
IW
OW
Write Port Read Port
expandedbeyond4bits toproduce a widerPAFnbus thatencompasses all
queues.
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
x36
x36
x36
x18
x9
x36
x18
x9
Alternatively,the4bitPAFnflagbusofeachdevicecanbeconnectedtogether
toformasingle4bitbus,i.e.PAF[0]ofdevice1willconnecttoPAF[0]ofdevice
2etc. Whenconnectingdevices inthis mannerthe PAFncanonlybe driven
byasingledeviceatanytime,(thePAFnoutputsofallotherdevicesmustbe
inhighimpedancestate).Therearetwomethodsbywhichtheusercanselect
whichdevicehas controlofthebus,theseare“Direct”(Addressed)modeor
x36
x36
“Polled”(Looped)mode,determinedbythestateoftheFM(flagMode)input FULL FLAG OPERATION
duringaMasterReset.
Themulti-queueflow-controldeviceprovidesasingleFullFlagoutput,FF.
TheFFflagoutputprovidesafullstatusofthequeuecurrentlyselectedonthe
writeportforwriteoperations.Internallythemulti-queueflow-controldevice
EXPANDING UP TO 32 QUEUES OR PROVIDING DEEPER QUEUES
Expansion can take place using either the standard mode or the packet monitorsandmaintainsastatusofthefullconditionofallqueueswithinit,however
mode.Inthe4queuemulti-queuedevice,theWRADDaddressbusis5bits onlythequeuethatisselectedforwriteoperationshasitsfullstatusoutputtothe
wide. The 2 Least Significant bits (LSbs) are used to address one of the 4 FF flag.This dedicatedflagis oftenreferredtoas the“activequeuefullflag”.
availablequeueswithinasinglemulti-queuedevice.The3MostSignificantbits
Whenqueueswitchesarebeingmadeonthewriteport,theFFflagoutput
(MSbs)are usedwhena device is connectedinexpansionmode withupto willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
8 devices connected in width expansion, each device having its own 3-bit onthecycleafteranewqueueselectionismade.Theuserthenhasafullstatus
22
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
forthenewqueueonecycleaheadoftheWCLKrisingedgethatdatacanbe
Thenatureofthefirstwordfallthroughoperationmeansthatwhenthelast
writtenintothenewqueue.Thatis,anewqueuecanbeselectedonthewrite datawordisreadfromaselectedqueue,theOVflagwillgoHIGHonthenext
portviatheWRADDbus,WADENenableandarisingedgeofWCLK.Onthe enabled read, that is, on the next rising edge of RCLK while REN is LOW.
nextrisingedgeofWCLK,theFFflagoutputwillshowthefullstatusofthenewly
Whenqueueswitchesarebeingmadeonthereadport,theOVflagwillswitch
selected queue. On the second rising edge of WCLK following the queue toshowstatusofthenewqueueinlinewiththedataoutputfromthenewqueue.
selection,datacanbewrittenintothenewlyselectedqueueprovidedthatdata Whenaqueueselectionismadethefirstdatafromthatqueuewillappearon
andenablesetup&holdtimesaremet.
theQoutdataoutputs2RCLKcycleslater,theOVwillchangestatetoindicate
Note,theFF flagwillprovidestatus ofanewlyselectedqueueoneWCLK validityofthedatafromthenewlyselectedqueueonthis2nd RCLKcyclealso.
cycleafterqueueselection,whichisonecyclebeforedatacanbewrittentothat Thepreviouscycleswillcontinuetooutputdatafromthepreviousqueueand
queue.Thispreventstheuserfromwritingdatatoaqueuethatisfull,(assuming theOVflagwillindicatethestatusofthoseoutputs.Again,theOVflagalways
thataqueueswitchhas beenmadetoaqueuethatis actuallyfull).
indicatesstatusforthedatacurrentlypresentontheoutputregister.
TheFFflagissynchronoustotheWCLKandalltransitionsoftheFFflagoccur
TheOVflagissynchronoustotheRCLKandalltransitionsoftheOVflagoccur
basedonarisingedgeofWCLK.Internallythemulti-queuedevicemonitorsand basedonarisingedgeofRCLK.Internallythemulti-queuedevicemonitorsand
keepsarecordofthefullstatusforallqueues.Itispossiblethatthestatusofa keepsarecordoftheoutputvalid(empty)statusforallqueues.Itispossiblethat
FFflagmaybechanginginternallyeventhoughthatflagisnottheactivequeue thestatusofanOVflagmaybechanginginternallyeventhoughthatrespective
flag (selected on the write port). A queue selected on the read port may flagisnottheactivequeueflag(selectedonthereadport).Aqueueselected
experienceachangeofitsinternalfullflagstatusbasedonreadoperations. onthewriteportmayexperienceachangeofitsinternalOVflagstatusbased
SeeFigure9,WriteQueueSelect,WriteOperationandFullFlagOperation on write operations, that is, data may be written into that queue causing it to
andFigure11, FullFlagTiminginExpansionModefortiminginformation.
become“notempty”.
SeeFigure12,ReadQueueSelect,ReadOperationandFigure13,Output
ValidFlagTimingfordetailsofthetiming.
EXPANSION MODE - FULL FLAG OPERATION
Whenmulti-queuedevicesareconnectedinExpansionmodetheFFflags
of all devices should be connected together, such that a system controller EXPANSION MODE – OUTPUT VALID FLAG OPERATION
monitoring and managing the multi-queue devices write port only looks at a
Whenmulti-queuedevicesareconnectedinExpansionmode,theOVflags
singleFFflag(asopposedtoadiscreteFFflagforeachdevice).ThisFFflag of all devices should be connected together, such that a system controller
isonlypertinenttothequeuebeingselectedforwriteoperationsatthattime. monitoring and managing the multi-queue devices read port only looks at a
Remember,thatwheninexpansionmodeonlyonemulti-queuedevicecanbe singleOVflag(asopposedtoadiscreteOVflagforeachdevice).ThisOVflag
writtentoatanymomentintime,thustheFFflagprovidesstatusoftheactive is onlypertinenttothequeuebeingselectedforreadoperations atthattime.
queue on the write port.
Remember,thatwheninexpansionmodeonlyonemulti-queuedevicecanbe
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheFFflag readfromatanymomentintime,thustheOVflagprovidesstatusoftheactive
outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis queue on the read port.
madeonlyasingledevicedrivestheFFflagbusandallotherFFflagoutputs
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheOVflag
connectedtotheFFflagbusareplacedintoHigh-Impedance.Theuserdoes outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control madeonlyasingledevicedrivestheOVflagbusandallotherOVflagoutputs
devicewillautomaticallyplaceitsFFflagoutputintoHigh-Impedancewhen connectedtotheOVflagbusareplacedintoHigh-Impedance.Theuserdoes
noneofitsqueuesareselectedforwriteoperations.
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control
Whenqueueswithinasingledeviceareselectedforwriteoperations,theFF devicewillautomaticallyplaceitsOVflagoutputintoHigh-Impedancewhen
flagoutputofthatdevicewillmaintaincontroloftheFFflagbus.ItsFFflagwill noneofits queues areselectedforreadoperations.
simplyupdatebetweenqueueswitchestoshowtherespectivequeuefullstatus.
Whenqueueswithinasingledeviceareselectedforreadoperations,theOV
Themulti-queuedeviceplacesitsFFflagoutputintoHigh-Impedancebased flagoutputofthatdevicewillmaintaincontroloftheOVflagbus.ItsOVflagwill
onthe3bitIDcodefoundinthe3mostsignificantbitsofthewritequeueaddress simplyupdatebetweenqueueswitchestoshowtherespectivequeueoutput
bus,WRADD.Ifthe3mostsignificantbitsofWRADDmatchthe3bitIDcodesetup validstatus.
onthestaticinputs,ID0,ID1andID2thentheFFflagoutputoftherespective
Themulti-queuedeviceplacesitsOVflagoutputintoHigh-Impedancebased
devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheFFflag onthe3bitIDcodefoundinthe3mostsignificantbitsofthereadqueueaddress
outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure bus,RDADD.Ifthe3mostsignificantbitsofRDADDmatchthe3bitIDcodesetup
11,FullFlagTiminginExpansionModefordetailsofflagoperation,including onthestaticinputs,ID0,ID1andID2thentheOVflagoutputoftherespective
when more than one device is connected in expansion.
devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheOVflag
outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure
13,OutputValidFlagTimingfordetailsofflagoperation,includingwhenmore
OUTPUTVALIDFLAGOPERATION
The multi-queue flow-control device provides a single Output Valid flag thanone device is connectedinexpansion.
output,OV.TheOVprovidesanemptystatusordataoutputvalidstatusforthe
datawordcurrentlyavailableontheoutputregisterofthereadport.Therising ALMOST FULL FLAG
edgeofanRCLKcyclethatplacesnewdataontotheoutputregisteroftheread
As previously mentioned the multi-queue flow-control device provides a
port, also updates the OV flag to show whether or not that new data word is singleProgrammableAlmostFullflagoutput,PAF.ThePAFflagoutputprovides
actuallyvalid.Internallythemulti-queueflow-controlmonitorsandmaintainsa astatusofthealmostfullconditionfortheactivequeuecurrentlyselectedonthe
statusoftheemptyconditionofallqueueswithinit,howeveronlythequeuethat writeportforwriteoperations.Internallythemulti-queueflow-controldevice
isselectedforreadoperationshasitsoutputvalid(empty)statusoutputtothe monitorsandmaintainsastatusofthealmostfullconditionofallqueueswithin
OV flag,givingavalidstatus forthewordbeingreadatthattime.
it,howeveronlythequeuethatisselectedforwriteoperationshasitsfullstatus
23
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
outputtothePAFflag.Thisdedicatedflagisoftenreferredtoasthe“activequeue selectedonthereadportforreadoperations.Internallythemulti-queueflow-
almostfullflag”.ThepositionofthePAFflagboundarywithinaqueuecanbe controlmonitorsandmaintainsastatusofthealmostemptyconditionofallqueues
atanypointwithinthatqueuesdepth.Thislocationcanbeuserprogrammed withinit,howeveronlythequeuethatisselectedforreadoperationshasitsempty
viatheserialportoroneofthedefaultvalues(8or128)canbeselectedifthe statusoutputtothePAEflag.Thisdedicatedflagisoftenreferredtoasthe“active
userhasperformeddefaultprogramming.
queuealmostemptyflag”.ThepositionofthePAEflagboundarywithinaqueue
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost can be at any point within that queues depth. This location can be user
fullstatus,whenaqueueisselectedonthewriteport,thisstatusisoutputviathe programmedvia the serialportorone ofthe defaultvalues (8or128)canbe
PAFflag.ThePAFflagvalueforeachqueueisprogrammedduringmulti-queue selectediftheuserhasperformeddefaultprogramming.
device programming (along with the number of queues, queue depths and
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost
almostemptyvalues).ThePAFoffsetvalue,m,forarespectivequeuecanbe emptystatus,whenaqueueisselectedonthereadport,thisstatusisoutputvia
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory thePAEflag.ThePAEflagvalueforeachqueueisprogrammedduringmulti-
depthforthatqueue.ThePAFvalueofdifferentqueueswithinthesamedevice queuedeviceprogramming(alongwiththenumberofqueues,queuedepths
canbedifferentvalues.
andalmostfullvalues).ThePAEoffsetvalue,n,forarespectivequeuecanbe
Whenqueueswitchesarebeingmadeonthewriteport,thePAFflagoutput programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus, depthforthatqueue.ThePAEvalueofdifferentqueueswithinthesamedevice
onthesecondcycleafteranewqueueselectionismade,onthesameWCLK canbedifferentvalues.
cyclethatdatacanactuallybewrittentothenewqueue.Thatis,anewqueue
Whenqueueswitchesarebeingmadeonthereadport,thePAEflagoutput
canbeselectedonthewriteportviatheWRADDbus,WADENenableanda willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
risingedgeofWCLK.OnthesecondrisingedgeofWCLKfollowingaqueue onthesecondcycleafteranewqueueselectionismade,onthesameRCLK
selection,thePAFflagoutputwillshowthefullstatusofthenewlyselectedqueue. cyclethatdataactuallyfallsthroughtotheoutputregisterfromthenewqueue.
The PAF is flagoutputis doubleregisterbuffered,sowhenawriteoperation That is, a new queue can be selected on the read port via the RDADD bus,
occursatthealmostfullboundarycausingtheselectedqueuestatustogoalmost RADENenableandarisingedgeofRCLK.OnthesecondrisingedgeofRCLK
fullthePAFwillgoLOW2WCLKcyclesafterthewrite.Thesameistruewhen followingaqueueselection,thedatawordfromthenewqueuewillbeavailable
a read occurs, there will be a 2 WCLK cycle delay after the read operation. attheoutputregisterandthePAEflagoutputwillshowtheemptystatusofthe
So the PAF flag delays are:
newlyselectedqueue.ThePAEis flagoutputis doubleregisterbuffered,so
froma write operationtoPAF flagLOWis 2WCLK+tWAF
when a read operation occurs at the almost empty boundary causing the
ThedelayfromareadoperationtoPAFflagHIGHistSKEW2+WCLK+tWAF selectedqueuestatustogoalmostemptythePAEwillgoLOW2RCLKcycles
Note, if tSKEW is violated there will be one added WCLK cycle delay.
after the read. The same is true when a write occurs, there will be a 2 RCLK
ThePAFflagissynchronoustotheWCLKandalltransitionsofthePAFflag cycledelayafterthewriteoperation.
occur based on a rising edge of WCLK. Internally the multi-queue device
monitorsandkeepsarecordofthealmostfullstatusforallqueues.Itispossible
thatthestatusofaPAFflagmaybechanginginternallyeventhoughthatflagis
nottheactivequeueflag(selectedonthewriteport).Aqueueselectedonthe
readportmayexperienceachangeofitsinternalalmostfullflagstatusbased
So the PAE flag delays are:
from a read operation toPAE flag LOW is 2 RCLK + tRAE
ThedelayfromawriteoperationtoPAEflagHIGHistSKEW2+RCLK+tRAE
Note, if tSKEW is violated there will be one added RCLK cycle delay.
ThePAEflagissynchronoustotheRCLKandalltransitionsofthePAEflag
on read operations. The multi-queue flow-control device also provides a occur based on a rising edge of RCLK. Internally the multi-queue device
duplicateofthePAFflagonthePAF[3:0]flagbus,thiswillbediscussedindetail monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible
inalatersectionofthedatasheet.
SeeFigures 22and23forAlmostFullflagtimingandqueueswitching.
thatthestatusofaPAEflagmaybechanginginternallyeventhoughthatflagis
nottheactivequeueflag(selectedonthereadport).Aqueueselectedonthe
writeportmayexperienceachangeofitsinternalalmostemptyflagstatusbased
on write operations. The multi-queue flow-control device also provides a
ALMOSTEMPTYFLAG
As previously mentioned the multi-queue flow-control device provides a duplicateofthePAEflagonthePAE[3:0]flagbus,thiswillbediscussedindetail
single Programmable Almost Empty flag output, PAE. The PAE flag output inalatersectionofthedatasheet.
providesastatusofthealmostemptyconditionfortheactivequeuecurrently
SeeFigures24and25forAlmostEmptyflagtimingandqueueswitching.
24
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING
Full Flag, FF Boundary
FF Boundary Condition
Output Valid, OV Flag Boundary
I/O Set-Up
In36 to out36
I/O Set-Up
OV Boundary Condition
In36 to out36 (Almost Empty Mode)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenote1belowfortiming)
FF Goes LOW after D+1 Writes
(Bothportsselectedforsamequeue
(seenotebelowfortiming)
when the 1st Word is written in)
In36 to out36
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after D Writes
(seenotebelowfortiming)
In36toout36(PacketMode)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenote2belowfortiming)
In36 to out18
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after D Writes
(seenotebelowfortiming)
In36 to out18
OV Goes LOW after 1st Write
(seenote1belowfortiming)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
In36 to out18
FF Goes LOW after D Writes
In36 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(Writeportonlyselectedforqueue
(seenotebelowfortiming)
(seenote1belowfortiming)
when the 1st Word is written in)
In36 to out9
FF Goes LOW after D Writes
(seenotebelowfortiming)
In18 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenote1belowfortiming)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
In36 to out9
FF Goes LOW after D Writes
(seenotebelowfortiming)
In9 to out36
OV Goes LOW after 1st Write
(seenote1belowfortiming)
(Writeportonlyselectedforqueue
(Bothportsselectedforsamequeue
when the 1st Word is written in)
when the 1st Word is written in)
In18 to out36
FF Goes LOW after ([D+1] x 2) Writes
(seenotebelowfortiming)
NOTE:
1. OV Timing
Assertion:
(Bothportsselectedforsamequeue
when the 1st Word is written in)
In18 to out36
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after (D x 2) Writes
Write to OV LOW: tSKEW1 + RCLK + tROV
If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tROV
De-assertion:
(seenotebelowfortiming)
Read Operation to OV HIGH: tROV
In9 to out36
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after ([D+1] x 4) Writes
(seenotebelowfortiming)
2. OV Timing when in Packet Mode (36 in to 36 out only)
Assertion:
Write to OV LOW: tSKEW4 + RCLK + tROV
If tSKEW4 is violated there may be 1 added clock: tSKEW4 + 2 RCLK + tROV
De-assertion:
In9 to out36
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after (D x 4) Writes
(seenotebelowfortiming)
Read Operation to OV HIGH: tROV
NOTE:
D = Queue Depth
FF Timing
Assertion:
Write Operation to FF LOW: tWFF
De-assertion:
Read to FF HIGH: tSKEW1 + tWFF
If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
I/O Set-Up
PAF & PAFn Boundary
in36 to out36
PAF/PAFn Goes LOW after
(Bothportsselectedforsamequeuewhenthe1st D+1-mWrites
Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)
in36 to out36
PAF/PAFn Goes LOW after
NOTE:
D = Queue Depth
m = Almost Full Offset value.
(Writeportonlyselectedforsamequeuewhenthe D-mWrites
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
Default values: if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
PAF Timing
in36 to out18
in36 to out9
in18 to out36
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
Assertion:
Write Operation to PAF LOW: 2 WCLK + tWAF
De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF
PAFn Timing
PAF/PAFn Goes LOW after
([D+1-m] x 2) Writes
(seenotebelowfortiming)
Assertion:
Write Operation to PAFn LOW: 2 WCLK* + tPAF
De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
in9 to out36
PAF/PAFn Goes LOW after
([D+1-m] x 4) Writes
(seenotebelowfortiming)
25
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Programmable Almost Empty Flag Bus, PAEn Boundary
I/O Set-Up PAEn Boundary Condition
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st n+2Writes
Programmable Almost Empty Flag, PAE Boundary
I/O Set-Up PAE Assertion
PAE Goes HIGH after n+2
(Bothportsselectedforsamequeuewhenthe1st Writes
in36 to out36
in36 to out36
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
in36 to out36
PAEn Goes HIGH after
in36 to out18
PAE Goes HIGH after n+1
(Writeportonlyselectedforsamequeuewhenthe n+1Writes
(Bothportsselectedforsamequeuewhenthe1st Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
in36 to out18
in36 to out9
in18 to out36
PAEn Goes HIGH after n+1
in36 to out9
PAE Goes HIGH after n+1
Writes (seebelowfortiming)
(Bothportsselectedforsamequeuewhenthe1st Writes
PAEn Goes HIGH after n+1
Writes(seebelowfortiming)
Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)
in18 to out36
PAE Goes HIGH after
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
PAE Goes HIGH after
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
in9 to out36
in18 to out36
PAEn Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 4) Writes
(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 2) Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
in9 to out36
PAEn Goes HIGH after
NOTE:
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 4) Writes
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAE Timing
Assertion:
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
PAEn Goes HIGH after
in9 to out36
(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 4) Writes
Read Operation to PAE LOW: 2 RCLK + tRAE
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAEn Timing
Assertion:
Read Operation to PAEn LOW: 2 RCLK* + tPAE
De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
PACKET READY FLAG BUS, PRn BOUNDARY
Assertion:
PACKETREADYFLAG,PRBOUNDARY
Assertion:
Both the rising and falling edges of PRn are synchronous to RCLK.
PRn Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assumingaTSOPmarker,oninputD34has previouslybeenwritten).i.e.a
completepacketisavailablewithinaqueue.
Both the rising and falling edges of PR are synchronous to RCLK.
PR Falling Edge occurs upon writing the first TEOP marker, on input D35,
(assumingaTSOPmarker,oninputD34has previouslybeenwritten).i.e.a
completepacketisavailablewithinaqueue.
Timing:
Timing:
FromWCLKrisingedgewritingtheTEOPwordPRgoes LOWafter:tSKEW4
+ 2 RCLK* + tPAE
FromWCLKrisingedgewritingtheTEOPwordPRgoes LOWafter:tSKEW4
+ 2 RCLK + tPR
If tSKEW4 is violated PRn goes LOW after tSKEW4 + 3 RCLK* + tPAE
*Ifaqueueswitchisoccurringonthereadportatthepointofflagassertionthere
may be one additional RCLK clock cycle delay.
De-assertion:
IftSKEW4isviolated:
PR goes LOW after tSKEW4 + 3 RCLK + tPR
(Please refertoFigure 18, Data Input(Transmit)PacketMode ofOperation
fortimingdiagram).
PRRisingEdgeoccursuponreadingthelastRSOPmarker,fromoutputQ34.
i.e.therearenomorecompletepacketsavailablewithinthequeue.
Timing:
FromRCLKrisingedgeReadingtheRSOPwordthe PR goes HIGHafter:2
RCLK* + tPAE
De-assertion:
PRRisingEdgeoccursuponreadingthelastRSOPmarker,fromoutputQ34.
i.e.therearenomorecompletepacketsavailablewithinthequeue.
Timing:
From RCLK rising edge Reading the RSOP word the PR goes HIGH after:
2 RCLK + tPR
*Ifaqueueswitchisoccurringonthereadportatthepointofflagassertionor
de-assertionthere maybe one additionalRCLKclockcycle delay.
(PleaserefertoFigure19,DataOutput(Receive)PacketModeofOperation
fortimingdiagram).
26
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PAFn BUS EXPANSION - DIRECT MODE
outputonthePAEn/PRnbus.Queues1through4havetheirPAE/PRstatus
If FM is LOW at Master Reset then the PAFn bus operates in Direct toPAE[0]throughPAE[3]respectively.Iflessthan4queuesareusedthenonly
(addressed)mode.Indirectmodetheusercanaddressthedevicetheyrequire theassociatedPAEn/PRnoutputswillberequired,unusedPAEn/PRn outputs
tocontrolthePAFnbus.Theaddresspresentonthe3mostsignificantbitsof willbedon’tcareoutputs.Whendevicesareconnectedinexpansionmodethe
the WRADD[4:0] address bus with FSTR (PAF flag strobe), HIGH will be PAEn/PRn flagbus canalsobe expandedbeyond4bits toproduce a wider
selectedasthedeviceonarisingedgeofWCLK.Sotoaddressthefirstdevice PAEn/PRnbusthatencompassesallqueues.
inabankofdevicestheWRADD[4:0]addressshouldbe“000xx”thesecond
Alternatively,the4bitPAEn/PRn flagbusofeachdevicecanbeconnected
device“001xx”andsoon.The3mostsignificantbitsoftheWRADD[4:0]address togethertoformasingle4bitbus,i.e.PAE[0]ofdevice1willconnecttoPAE[0]
buscorrespondtothedeviceIDinputsID[2:0].ThePAFnbuswillchangestatus ofdevice2etc.WhenconnectingdevicesinthismannerthePAEn/PRnbuscan
toshowthenewdeviceselected1WCLKcycleafterdeviceselection.Note,that onlybedrivenbyasingledeviceatanytime,(thePAEn/PRn outputsofallother
if a read or write operation is occurring to a specific queue, say queue ‘x’ on devicesmustbeinhighimpedancestate).Therearetwomethodsbywhichthe
thesamecycleasaPAFnbusswitchtothedevicecontainingqueue‘x’,then user can select which device has control of the bus, these are “Direct”
theremaybeanextraWCLKcycledelaybeforethatqueuesstatusiscorrectly (Addressed)modeor“Polled”(Looped)mode,determinedbythestateofthe
shownontherespectiveoutputofthe PAFnbus.However,the“active”PAF FM (flag Mode) input during a Master Reset.
flagwillshowcorrectstatusatalltimes.
Devices can be selected on consecutive WCLK cycles, that is the device PAEn/PRn BUS EXPANSION- DIRECT MODE
controllingthe PAFnbus canchangeeveryWCLKcycle. Also, datapresent
If FM is LOW at Master Reset then the PAEn/PRn bus operates in Direct
ontheinputbus,Din,canbewrittenintoaqueueonthesameWLCKrisingedge (addressed)mode.Indirectmodetheusercanaddressthedevicetheyrequire
thatadeviceisbeingselectedonthePAFnbus,theonlyrestrictionbeingthat tocontrolthePAEn/PRnbus.Theaddresspresentonthe3mostsignificantbits
awritequeueselectionandPAFnbusselectioncannotbemadeonthesamecycle. ofthe RDADD[5:0]address bus withESTR(PAE/PRflagstrobe), HIGHwill
beselectedasthedeviceonarisingedgeofRCLK.Sotoaddressthefirstdevice
PAFn BUS EXPANSION– POLLED MODE
inabankofdevices theRDADD[5:0]address shouldbe“000xx”thesecond
IfFMisHIGHatMasterResetthenthePAFnbusoperatesinPolled(Looped) device“001xx”andsoon.The3mostsignificantbitsoftheRDADD[5:0]address
mode.InpolledmodethePAFnbusautomaticallycyclesthroughthedevices buscorrespondtothedeviceIDinputsID[2:0].ThePAEn/PRnbuswillchange
connected in expansion. In expansion mode one device will be set as the status toshowthenewdeviceselected1RCLKcycleafterdeviceselection.
Master,MASTinputtiedHIGH,allotherdeviceswillhaveMASTtiedLOW.The Note,thatifareadorwriteoperationisoccurringtoaspecificqueue,sayqueue
masterdeviceisthefirstdevicetotakecontrolofthePAFnbusandplacethe ‘x’onthesamecycleasaPAEn/PRnbusswitchtothedevicecontainingqueue
PAFstatusofitsqueuesontothebusonthefirstrisingedgeofWCLKafterthe ‘x’,thentheremaybeanextraRCLKcycledelaybeforethatqueuesstatusis
MRSinputgoesHIGHonceaMasterResetiscomplete.TheFSYNC(PAFsync correctlyshownontherespectiveoutputofthePAEn/PRnbus.However,the
pulse)outputofthefirstdevice(masterdevice),willbeHIGHforonecycleof “active”PAEand/orPRflagwillshowcorrectstatusatalltimes.
WCLKindicatingthatitishascontrolofthePAFnbusforthatcycle.
Devices can be selected on consecutive RCLK cycles, that is the device
Thedevicealsopassesa“token”ontothenextdeviceinthechain,thenext controllingthePAEn/PRnbuscanchangeeveryRCLKcycle.Also,datacan
deviceassumingcontrolofthePAFnbusonthenextWCLKcycle.Thistoken be read out of a queue on the same RCLK rising edge that a device is being
passing is done via the FXO outputs and FXI inputs of the devices (“PAFn selected on the PAEn/PRn bus, the only restriction being that a read queue
ExpansionOut”and“PAFnExpansionIn”).TheFXOoutputofthefirstdevice selectionandPAEn/PRnbusselectioncannotbemadeonthesamecycle.
connectingtothe FXIinputofthe seconddevice inthe chain, the FXOofthe
seconddeviceconnects totheFXIofthethirddeviceandsoon.TheFXOof PAEn/PRn BUS EXPANSION- POLLED MODE
thefinaldeviceinachainconnectstotheFXIofthefirstdevice,sothatoncethe
PAFn bus has cycled through all devices control is again passed to the first (Looped)mode.InpolledmodethePAEn/PRnbusautomaticallycyclesthrough
device.TheFXOoutputofadevicewillbeHIGHfortheWCLKcycleithascontrol thedevicesconnectedinexpansion.Inexpansionmodeonedevicewillbeset
IfFMis HIGHatMasterResetthenthe PAEn/PRnbus operates inPolled
ofthebus.
astheMaster,MASTinputtiedHIGH,allotherdeviceswillhaveMASTtiedLOW.
PleaserefertoFigure28,PAFnBus–PolledModefortiminginformation. ThemasterdeviceisthefirstdevicetotakecontrolofthePAEn/PRnbusand
placethePAE/PRstatusofitsqueuesontothebusonthefirstrisingedgeofRCLK
PAEn/PRn FLAG BUS OPERATION
aftertheMRSinputgoesHIGHonceaMasterResetiscomplete.TheESYNC
TheIDT72V51236/72V51246/72V51256multi-queueflow-controldevices (PAE/PRsyncpulse)outputofthefirstdevice(masterdevice),willbeHIGHfor
canbeconfiguredforupto4queues,eachqueuehavingitsownalmostempty/ onecycleofRCLKindicatingthatitishascontrolofthePAEn/PRnbusforthat
packetreadystatus.Anactivequeuehasitsflagstatusoutputtothediscreteflags, cycle.
OV, PAE and PR, on the read port. Queues that are not selected for a read
Thedevicealsopassesa“token”ontothenextdeviceinthechain,thenext
operationcanhavetheirPAE/PRstatusmonitoredviathePAEn/PRnbus.The deviceassumingcontrolofthePAEn/PRnbus onthenextRCLKcycle.This
PAEn/PRnflagbusis4bitswide,sothatall4queuescanhavetheirstatusoutput tokenpassingisdoneviatheEXOoutputsandEXIinputsofthedevices(“PAEn/
tothebus.Themulti-queuedevicecanprovideeither“AlmostEmpty”statusor PRnExpansionOut”and“PAEn/PRnExpansionIn”).TheEXOoutputofthe
“PacketReady”statusviathePAEn/PRnbusofitsqueues,dependingonwhich firstdeviceconnectingtotheEXIinputoftheseconddeviceinthechain,theEXO
hasbeenselectedviathePKT(Packet)inputduringamasterreset.IfPKTis oftheseconddeviceconnectstotheEXIofthethirddeviceandsoon.TheEXO
HIGHthenpacketmodeisselectedandthePAEn/PRnbuswillprovide“Packet ofthefinaldeviceinachainconnectstotheEXIofthefirstdevice,sothatonce
Ready”status.IfitisLOWthenthePAEn/PRnbuswillprovide“AlmostEmpty” thePAEn/PRnbus has cycledthroughalldevices controlis againpassedto
status.Ineithercasetheoperationofthebusisthesamethedifferencebeing the firstdevice. The EXOoutputofa device willbe HIGHforthe RCLKcycle
thatthebusisproviding“PacketReady”statusversus“AlmostEmpty”status. ithascontrolofthebus.
Whenasinglemulti-queuedeviceisusedanywherefrom1to4queuesmay
beset-upwithinthepart,eachqueuehavingitsowndedicatedPAEn/PRnflag information.
Please refer to Figure 29, PAEn/PRn Bus – Polled Mode for timing
27
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
Write to Queue
A
B
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BM
L
IW OW
A
B
C
D
Read from Queue
L
L
(a) x36 INPUT to x36 OUTPUT
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q8-Q0
BM
H
IW OW
1st: Read from Queue
2nd: Read from Queue
C
D
L
L
Q17-Q9
Q8-Q0
A
B
(b) x36 INPUT to x18 OUTPUT
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BM
H
IW OW
D
1st: Read from Queue
2nd: Read from Queue
L
H
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q17-Q9
Q8-Q0
C
Q8-Q0
B
3rd: Read from Queue
4th: Read from Queue
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
A
(c) x36 INPUT to x9 OUTPUT
D35-D27
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
A
1st: Write to Queue
2nd: Write to Queue
B
D26-D18
D17-D9
D8-D0
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BM
H
IW OW
D
B
C
A
Read from Queue
H
L
(d) x18 INPUT to x36 OUTPUT
BYTE ORDER ON INPUT PORT:
D35-D27
D35-D27
D35-D27
D35-D27
D26-D18
D26-D18
D26-D18
D26-D18
D17-D9
D17-D9
D17-D9
D17-D9
D8-D0
A
1st: Write to Queue
2nd: Write to Queue
D8-D0
B
D8-D0
C
3rd: Write to Queue
4th: Write to Queue
D8-D0
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BM
H
IW OW
D
C
B
A
Read from Queue
5937 drw08
H
H
(e) x9 INPUT to x36 OUTPUT
Figure 3. Bus-Matching Byte Arrangement
28
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
MRS
t
RSS
RSS
WEN
REN
t
tRSR
SENI
tRSS
FSTR,
ESTR
tRSS
WADEN,
RADEN
t
RSS
RSS
RSS
ID0, ID1,
ID2
t
OW, IW,
BM
t
HIGH = Looped
LOW = Strobed (Direct)
FM
MAST
PKT
t
RSS
HIGH = Master Device
LOW = Slave Device
tRSS
HIGH = Packet Ready Mode
LOW = Almost Empty
t
RSS
RSS
HIGH = Default Programming
LOW = Serial Programming
DFM
t
HIGH = Offset Value is 128
LOW = Offset value is 8
DF
t
t
t
t
RSF
HIGH-Z if Slave Device
FF
LOGIC “0" if Master Device
RSF
RSF
RSF
LOGIC "1" if Master Device
OV
PAF
PAE
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
HIGH-Z if Slave Device
LOGIC "0" if Master Device
tRSF
tRSF
tRSF
tRSF
tRSF
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PAFn
PAEn
PR
HIGH-Z if Slave Device
LOGIC "0" if Master Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PRn
LOGIC "1" if OE is LOW and device is Master
Qn
HIGH-Z if OE is HIGH or Device is Slave
5937 drw09
NOTES:
1. OE can toggle during this period.
2. PRS should be HIGH during a MRS.
Figure 4. Master Reset
29
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
w-2
w-1
w
w+1
w+2
w+3
WCLK
tQH
tQS
WADEN
WEN
tENS
tENS
t
AS
tAH
WRADD
Qx
t
WFF
FF
tWAF
PAF
t
PAF
Active Bus
PAF-Qx(5)
tPRSS
tPRSH
PRS
tPRSH
tPRSS
RCLK
tENS
tENS
REN
tQH
tQS
RADEN
t
AS
tAH
RDADD
Qx
tROV
OV
tRAE
PAE
t
PAE
Active Bus
PAE-Qx(6)
r-2
r-1
r
r+1
r+2
r+3
5937 drw10
NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 2 clock cycles before the Partial Reset takes place, on both the write and read ports.
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
Figure 5. Partial Reset
Master Reset
Default Mode
DFM = 0
MRS
MRS
DFM
DFM
MRS
DFM
MQ2
MQn
MQ1
Serial Loading
Complete
SENI
SI
SENO
SO
SENI
SI
SENI
SI
SENO
SO
SENO
SO
Serial Enable
Serial Input
SCLK
SCLK
SCLK
5937 drw11
Serial Clock
Figure 6. Serial Port Connection for Serial Programming
30
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
31
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
32
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
33
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
tENH
tENS
WEN
tDS
tDH
tDS
tDH
tDS
tDH
W1
W2
W3
Dn
RCLK
REN
t
SKEW1
1
2
tENS
tA
tA
tA
Last Word Read Out of Queue
W1 Qy
FWFT
W2 Qy
FWFT
W3 Qy
Qout
OV
tROV
tROV
5937 drw13a
NOTES:
1. Qy has previously been selected on both the write and read ports.
2. OE is LOW.
3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.
Figure 10. Write Operations & First Word Fall Through
34
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
35
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
36
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK
REN
tENS
tAS
tAH
tAS
tAH
RDADD
RADEN
D1
Q3
D1 Q2
Addr=001011
QH
Addr=001010
tQS
t
tQH
tQS
tA
tA
tA
tA
tOLZ
Qout
D
1
Q
3
WD
Last Word
D1 Q2
PFT We-1
D1
Q2
We
Last Word
W0 Q2
D1
(Device 1)
t
ROV
tROV
tROV
tROV
tOVLZ
HIGH-Z
OV
(Device 1)
tOVHZ
OV
(Device 2)
tSKEW1
WCLK
tENS
tENH
WEN
tAS
tAH
WRADD
D1 Q2
tQS
tQH
WADEN
Din
tDS
t
DH
D1 Q2
W0
5937 drw16
Cycle:
*A* Queue 3 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control
of Qout bus, its Qout outputs are in Low-Impedance. This diagram only shows the Qout outputs of device 1. (Reads are disabled).
*B* Reads are now enabled. A word from the previously selected queue of Device 2 will be read out.
*C* The Qout of Device 1 goes to Low-Impedance and word Wd is read from Q3 of D1. This happens to be the last word of Q3. Device 2 places its Qout outputs into
High-Impedance, device 1 has control of the Qout bus. The OV flag of Device 2 goes to High-Impedance and Device 1 takes control of OV. The OV flag of Device 1 goes LOW
to show that Wd of Q3 is valid.
*D* Queue 2 of device 1 is selected for read operations. The last word of Q3 was read on the previous cycle, therefore OV goes HIGH to indicate that the data on the Qout is
not valid (Q3 was read to empty). Word, Wd remains on the output bus.
*E* The last word of Q3 remains on the Qout bus, OV is HIGH, indicating that this word has been previously read.
*F* The next word (We-1), available from the newly selected queue, Q2 of device 1 is now read out. This will occur regardless of REN, 2 RCLK cycles after queue selection
due to the FWFT operation. The OV flag now goes LOW to indicate that this word is valid.
*G* The last word, We is read from Q2, this queue is now empty.
*H* The OV flag goes HIGH to indicate that Q2 was read to empty on the previous cycle.
*I* Due to a write operation the OV flag goes LOW and data word W0 is read from Q2. The latency is: tSKEW1 + 1*RCLK + tROV.
Figure 13. Output Valid Flag Timing (In Expansion Mode)
37
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
*J*
RCLK
tENS
tENH
tENS
tENH
REN
tAS
tAH
tAH
tAS
RDADD
Qn
QP
tQS
tQH
tQS
tQH
RADEN
tA
tA
tA
tA
tA
tA
QOUT
QP
WD
QP WD+1
Q
P
WD+2
Qn
WX
Qn
WX+1
Q
P
WD+3
QP WD+4
OV
5937 drw17
Cycle:
*A* Word Wd+1 is read from the previously selected queue, Qp.
*B* Reads are disabled, word Wd+1 remains on the output bus.
*C* A new queue, Qn is selected for read port operations.
*D* Due to FWFT operation Word, Wd+2 of Qp is read out regardless of REN.
*E* The next available word Wx of Qn is read out regardless of REN, 2 RCLK cycles after queue selection. This is FWFT operation.
*F* The queue, Qp is again selected.
*G* Word Wx+1 is read from Qn regardless of REN, this is due to FWFT.
*H* Word Wd+3 is read from Qp, this read occurs regardless of REN due to FWFT operation.
*I* Word Wd+4 is read from Qp.
*J* Reads are disabled on this cycle, therefore no further reads occur.
Figure 14. Read Queue Selection with Reads Disabled
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK
REN
tENS
tENH
tENS
tAS
tAH
tAS
tAH
RDADD
RADEN
QB
QA
tQS
tQH
tQS
tQH
OE
tA
tA
tA
tA
tOHZ
tA
tOE
tOLZ
Qout
Previous Data in O/P Register
Q
A
PFT
W
0
QA
W1
QA
W2
QA
W3
QA W4
No Read
QB is Empty
ROV
tROV
t
OV
5937 drw18
NOTES:
1. The Output Valid flag, OV is HIGH therefore the previously selected queue has been read to empty. The Output Enable input is Asynchronous, therefore the Qout output bus
will go to Low-Impedance after time tOLZ.
The data currently on the output register will be available on the output after time tOE. This data is the previous data on the output register, this is the last word read out of the
previous queue.
2. In expansion mode the OE inputs of all devices should be connected together. This allows the output busses of all devices to be High-Impedance controlled.
Cycle:
*A* Queue A is selected for reads. No data will fall through on this cycle, the previous queue was read to empty.
*B* No data will fall through on this cycle, the previous queue was read to empty.
*C* Word, W0 from Qa is read out regardless of REN due to FWFT operation. The OV flag goes LOW indicating that Word W0 is valid.
*D* Reads are disabled therefore word, W0 of Qa remains on the output bus.
*E* Reads are again enabled so word W1 is read from Qa.
*F* Word W2 is read from Qa.
*G* Queue, Qb is selected on the read port. This queue is actually empty. Word, W3 is read from Qa.
*H* Word, W4 falls through from Qa.
*I* Output Valid flag, OV goes HIGH to indicate that Qb is empty. Data on the output port is no longer valid.
Output Enable is taken HIGH, this is Asynchronous so the output bus goes to High-Impedance after time, tOHZ.
Figure 15. Read Queue Select, Read Operation and OE Timing
38
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
39
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
40
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
41
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
42
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
SELECT
NEW QUEUE
*D*
NULL QUEUE
SELECT
*A*
*B*
*C*
*E*
*F*
RCLK
tAS
tAH
tAS
tAH
0001xx
000011
D0 Q3
RDADD
RADEN
tQS
tQH
tQS
tQH
tENS
tENH
REN
Qout
OV
tA
tA
tA
tA
Q3 W0
FWFT
Q1 Wn-3
Q1 Wn-2
Q1 Wn-1
Q1 Wn
tROV
tROV
5937 drw23
NOTES:
1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words
from that queue.
2. Please see Figure 21, Null Queue Flow Diagram.
Cycle:
*A* Null Q of device 0 is selected, when word Wn-1 from previously selected Q1 is read.
*B* REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register.
Note: *B* and *C* are a minimum 2 RCLK cycles between Q selects.
*C* The Null Q is seen as an empty Queue on the read side, therefore Wn of Q1 remains in the O/P register and OV goes HIGH.
*D* A new Q, Q3 is selected and the 1st word of Q3 will fall through present on the O/P register on cycle *F*.
Figure 20. Read Operation and Null Queue Select
*A*
*B*
*C*
*D*
*E*
*F*
Null
Queue
Queue 3
Memory
Queue 3
Memory
Queue 1
Memory
Null
Queue
Null
Queue
Q1
Q1
Q1
Q1
Q3
Q3
Wn
Wn
Wn
Wn
W0
W1
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
Qn
Q1
Q1
Q1
Q1
Q3
Wn-1
Wn
Wn
Wn
Wn
W0
5937 drw24
Figure 21. Null Queue Flow Diagram
43
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
WCLK
WEN
2
1
tENH
tENS
tAH
tAS
tAS
tAH
WRADD
D1
Q2
D1 Q0
tQS
tQH
tQH
tQS
WADEN
Din
tDS
tDH
WD-m
D1 Q2
tWAF
tWAF
tAFLZ
HIGH-Z
PAF
(Device 1)
tFFHZ
PAF
(Device 2)
5937 drw25
Cycle:
*A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* Word, Wd-m is written into Q2 causing the PAF flag to go from HIGH to LOW. The flag latency is 2 WCLK cycles + tWAF.
*D* Queue 0 if device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 2 WCLK + tWAF latency.
*E* The PAF flag goes LOW based on the write 2 cycles earlier.
*F* The PAF flag goes HIGH due to the queue switch to Q0.
Figure 22. Almost Full Flag Timing and Queue Switch
tCLKL
tCLKL
WCLK
WEN
PAF
1
2
1
tENS
tENH
tWAF
tWAF
D-(m+1) words
in Queue
D - (m+1) words in Queue
D - m words in Queue
tSKEW2
RCLK
tENS
tENH
5937 drw26
REN
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + tWAF
De-assertion: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there will be one extra WCLK cycle.
Figure 23. Almost Full Flag Timing
44
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
RCLK
REN
HIGH
AS
t
tAH
tAS
tAH
RDADD
D1
Q3
D1
Q1
tQS
tQH
tQH
tQS
RADEN
Qout
t
A
t
A
t
A
tA
tOLZ
HIGH-Z
HIGH-Z
D1
Q3
Wn
D
1
Q3
Wn+1
D
1
Q1
W0
D1 Q1 W1
t
RAE
t
RAE
tAELZ
PAE
(Device 1)
tAEHZ
PAE
(Device 2)
HIGH-Z
5937 drw27
Cycle:
*A* Queue 3 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* The PAE flag output now switches to device 1. Word, Wn is read from Q3 due to the FWFT operation. This read operation from Q3 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*D* Q1 of device 1 is selected.
*E* The PAE flag goes LOW due to the read from Q3 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*F* Word, W0 is read from Q1 due to the FWFT operation. The PAE flag goes HIGH to show that Q1 is not almost empty.
Figure 24. Almost Empty Flag Timing and Queue Switch
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
n+1 words in Queue
SKEW2
n+2 words in Queue
n+1 words in Queue
tRAE
t
tRAE
RCLK
1
2
tENS
tENH
5937 drw28
REN
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + tRAE
De-assertion: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there will be one extra RCLK cycle.
Figure 25. Almost Empty Flag Timing
45
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
1
*C*
2
*D*
*E*
*F*
WCLK
WADEN
FSTR
tQH
tQS
tQS
tQH
tSTS
tSTH
tENS
tENS
tENH
tENH
WEN
tAS
tAH
tAH
tAS
tAS
tAH
Device 4
D3Q2
01110
WRADD
Dn
D5Q3
100 11
tDS
tDH
100 xx
tDS
tDH
Wp
Wp+1
Wn+1
D5Q3
Wn
D5 Q3
Wx
D3 Q2
Writes to Previous Q
tSKEW3
RCLK
RADEN
ESTR
1
2
tQS
tQH
tSTH
tSTS
tENS
tENH
REN
tAH
tAS
tAS
tAH
RDADD
Device 5
D5Q3
100 011
101 xxx
t
A
t
A
tA
t
A
tA
Wy
D5 Q3
Wy+3
D5 Q3
Wy+1
D5 Q3
Device 5 -Qn
Wa
D5 Qx
Wa+1
D5 Qn
Wy+2
D5 Q3
Previous value loaded on to PAE bus
Prev PAEn
tPAEHZ
tPAE
tPAEZL
1xxx
1xxx
Device 5 PAEn
Device 5
Device 5
1xxx
Device 5
1xxx
Device 5
Previous value loaded on to PAE bus
D5 Qx Status
Bus PAEn
t
RAE
tRAE
tRAE
D5 Q3
status
Device 5 PAE
5937 drw29
*EE*
*AA*
*BB*
*CC*
*FF*
*DD*
Cycle:
*A* Queue 3 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA* Queue 3 of Device 5 is selected for read operations.
Another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
*B* Word Wp+1 is written into the previously selected queue.
*BB* Word, Wa+1 is read from Qx of D5, due to FWFT operation.
*C* Word, Wn is written into the newly selected queue, Q3 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added.
*CC* Word, Wy from the newly selected queue, Q3 will be read out due to FWFT operation.
Device 5 is selected on the PAEn bus. Q3 of device 5 will therefore have is PAE status output on PAE[3]. There is a single RCLK cycle latency before the PAEn bus changes
to the new selection.
*D* Queue 2 of Device 3 is selected for write operations.
Word Wn+1 is written into Q3 of D5.
*DD* The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and are placed onto the outputs. The previously selected device now places its
PAEn outputs into High-Impedance to prevent bus contention. Word, Wy+1 is read from Q3 of D5.
The discrete PAE flag will go HIGH to show that Q3 of D5 is not almost empty. Q3 of device 5 will have its PAE status output on PAE[3].
*E* No writes occur.
*EE* Word, Wy+2 is read from Q3 of D5.
*F* Device 4 is selected on the write port for the PAFn bus.
Word, Wx is written into Q2 of D3.
*FF* The PAEn bus updates to show that Q3 of D5 is almost empty based on the reading out of word, Wy+1.
The discrete PAE flag goes LOW to show that Q3 of D5 is almost empty based on the reading of Wy+1.
Figure 26. PAEn - Direct Mode, Flag Operation – Devices in Expansion
46
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
*A*
*B*
*C*
*D*
*E*
*F*
*G*
RCLK
tQH
tQS
tQS
tQH
RADEN
tSTH
tSTS
ESTR
REN
tAS
tAH
tAH
tAS
RDADD
D6Q2
110 010
Device 7
111 xxx
D0Q1
000 001
OE
tA
tA
tA
t
A
tOLZ
Qout
W
X
W
X +1
Prev. Q
W
D0 Q1
D - M + 2
W0
D6 Q2
W
D0 Q1
D-M+1
Prev. Q
tSKEW3
WCLK
FSTR
1
2
tSTS
tSTH
tAS
tAH
tAS
tAH
WRADD
D0 Q1
Device 0
000 xxx
tENS
tENH
WEN
tQH
tQS
WADEN
Din
t
DS
t
DH
tDS
tDH
tDS
tDH
Wy+1
Wy+2
Word W
y
D0 Q1
D0 Q1
D0 Q1
tPAFLZ
tPAF
tPAF
Device 0 PAFn
xx0x
xx0x
xx1x
xx1x
xx0x
xx0x
Device 0
Device 0
Device 0
Device 0
Device 0
HIGH-Z
Previous Device
Previous Device
Device 0
Bus PAFn
tPAFHZ
HIGH-Z
Prev. PAFn
tPAFLZ
tWAF
Device 0
HIGH - Z
5937 drw30
PAF
*AA*
*BB*
*CC*
*DD*
*EE*
*FF*
Cycle:
*A* Queue 1 of device 0 is selected for read operations.
The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.
*AA* Device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected device X.
*B* Word, Wx+1 is read out from the previous queue due to the FWFT effect.
*BB* Queue 1 of device 0 is selected on the write port.
The PAFn bus is updated with the device selected on the previous cycle, device 0 PAF[1] is LOW showing the status of queue 1.
The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
*C* Device 7 is selected for the PAFn bus.
Word, Wd-m+1 is read from Q1 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q1. This read will cause the PAF[1] output to go from
LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.
*CC* PAFn continues to show status of D0.
*D* No read operations occur, REN is HIGH.
*DD* PAF[1] goes HIGH to show that D0 Q1 is not almost empty due to the read on cycle *C*.
The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q1.
*E* Queue 2 of Device 6 is selected for write operations.
*EE* Word, Wy+1 is written into D0 Q1.
*F* Word, Wd-m+2 is read out due to FWFT operation.
*FF* PAF[1] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q1 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q1.
*G* Word, W0 is read from Q0 of D6, selected on cycle *E*, due to FWFT.
Figure 27. PAFn - Direct Mode, Flag Operation – Devices in Expansion
47
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
tFSYNC
tFSYNC
tFSYNC
tFSYNC
FSYNC
0
(MASTER)
tFXO
tFXO
tFXO
tFXO
FXO /
0
FXI
1
tFSYNC
tFSYNC
FSYNC
1
(SLAVE)
tFXO
tFXO
FXO /
1
FXI
2
tFSYNC
tFSYNC
FSYNC
2
(SLAVE)
tFXO
tFXO
FXO /
2
FXI
0
tPAF
tPAF
tPAF
tPAF
tPAF
Device 0
Device 1
Device 2
Device 0
PAF[3:0]
5937 drw31
NOTE:
1. This diagram is based on 3 devices connected to expansion mode.
Figure 28. PAFn Bus - Polled Mode
48
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
RCLK
tESYNC
tESYNC
tESYNC
tESYNC
ESYNC
0
tEXO
tEXO
tEXO
tEXO
EXO /
0
EXI
1
tESYNC
tESYNC
ESYNC
1
tEXO
tEXO
EXO /
1
FXI
2
tESYNC
tESYNC
ESYNC
2
tEXO
tEXO
EXO /
2
EXI
0
tPAE
tPAE
tPAE
tPAE
tPAE
Device 0
Device 1
Device 2
Device 0
PAE
n
5937 drw32
Figure 29. PAEn/PRn Bus - Polled Mode
49
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Serial Programming Data Input
Serial Enable
SENI
SI FXI EXI
Output Data Bus
Data Bus
Q -Q
D -D
0
35
0
35
Read Clock
Write Clock
RCLK
WCLK
Write Enable
Read Enable
WEN
REN
RDADD
RADEN
Read Queue Select
Read Address
Write Queue Select
Write Address
WRADD
WADEN
DEVICE
1
Empty Strobe
Full Strobe
ESTR
FSTR
PAFn
Programmable Almost Full
Programmable Almost Empty
PAEn
Empty Sync 1
Output Valid Flag
Almost Empty Flag
Packet Reads
Full Sync1
ESYNC
FSYNC
Full Flag
OV
FF
Almost Full Flag
Serial Clock
PAF
PAE
PR
SCLK
SENO SO FXO EXO
SENI SI FXI EXI
Q -Q
D -D
0
35
0
35
WCLK
RCLK
WEN
REN
WRADD
WADEN
RDADD
RADEN
DEVICE
2
FSTR
PAFn
ESTR
PAEn
Empty Sync 2
Full Sync2
FSYNC
ESYNC
FF
OV
PAF
PAE
SCLK
PR
SENO SO FXO EXO
SENI SI FXI EXI
Q -Q
D -D
0
35
0
35
WCLK
RCLK
REN
WEN
WRADD
WADEN
RDADD
RADEN
DEVICE
n
FSTR
PAFn
FSYNC
ESTR
PAEn
Full Sync n
Empty Sync n
ESYNC
FF
OV
PAF
PAE
PR
SCLK
SENO
FXO EXO
DONE
5937 drw33
NOTES:
1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO
outputs are DNC (Do Not Connect).
2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.
Figure 30. Multi-Queue Expansion Diagram
50
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V51236/72V51246/
72V51256incorporates thenecessarytapcontrollerandmodifiedpadcellsto
implementtheJTAG facility.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
The Figure belowshows the standardBoundary-ScanArchitecture
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5937 drw34
Figure 31. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
51
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-IR
Shift-DR
1
1
1
1
Input = TMS
Exit1-IR
Exit1-DR
0
0
0
0
Pause-IR
Pause-DR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-IR
Update-DR
1
0
1
0
5937 drw35
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal Queue operations can begin.
Figure 32. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determines thestateprogression
thatoccursoneachTCLKrisingedge.TheTAPcontrollertakesprecedence
overthe Queue andmustbe resetafterpowerupofthe device. See TRST
descriptionformoredetailsonTAPcontrollerreset.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenabling
thenormaloperationoftheIC.TheTAPcontrollerstatemachineisdesigned
insuchawaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-
Logic-ResetstatecanbeenteredbyholdingTMSathighandpulsingTCKfive
times. This is the reasonwhythe TestReset(TRST)pinis optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
52
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
THE INSTRUCTION REGISTER
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
•
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions. Instructionsaredecodedasfollows.
TESTDATAREGISTER
Hex
Value
00
01
02
Instruction
Function
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
EXTEST
SAMPLE/PRELOAD
IDCODE
HIGH-IMPEDANCE
BYPASS
SelectBoundaryScanRegister
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
JTAG
04
0F
SelectBypassRegister
JTAG INSTRUCTION REGISTER DECODING
TEST BYPASS REGISTER
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
EXTEST
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO.Duringthisinstruction,theboundary-scanregisterisaccessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
IDCODE
THE DEVICE IDENTIFICATION REGISTER
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDI and TDO. The device identification register is a 32-bit shift register
containinginformationregardingtheICmanufacturer,devicetype,andversion
code.Accessingthedeviceidentificationregisterdoesnotinterferewiththe
operationoftheIC.Also,accesstothedeviceidentificationregistershouldbe
immediatelyavailable,viaaTAPdata-scanoperation,afterpower-upofthe
ICoraftertheTAPhasbeenresetusingtheoptionalTRSTpinorbyotherwise
movingtotheTest-Logic-Resetstate.
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
FortheIDT72V51236/72V51246/72V51256,thePartNumberfieldcon-
tainsthefollowingvalues:
Device
Part# Field (HEX)
0x41B
IDT72V51236
IDT72V51246
IDT72V51256
SAMPLE/PRELOAD
0x41C
0x41D
TherequiredSAMPLE/PRELOADinstructionallowstheICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.This instructionis alsousedtopreloadtestdata
intotheboundary-scanregisterbeforeloadinganEXTESTinstruction.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
JTAG DEVICE IDENTIFICATION REGISTER
53
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
toTDOwithoutaffectingtheconditionoftheICoutputs.
theIC.
54
IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFLOW-CONTROLDEVICES
(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5937 drw36
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 33. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
(vcc = 3.3V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions Min. Max. Units
SYSTEMINTERFACEPARAMETERS
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
IDT72V51236
IDT72V51246
IDT72V51256
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. 50pf loading on external output signals.
NOTE:
1. Guaranteed by design.
55
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Plastic Ball Grid Array (PBGA, BB256-1)
BB
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
6
7-5
Commercial Only
Commercial & Industrial
L
Low Power
72V51236 589,824 bits 3.3V Multi-Queue Flow-Control Device
72V51346 1,179,648 bits 3.3V Multi-Queue Flow-Control Device
72V51256 2,359,296 bits 3.3V Multi-Queue Flow-Control Device
5937 drw37
NOTE:
1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order.
DATASHEETDOCUMENTHISTORY
10/10/2001
11/16/2001
12/19/2001
01/15/2002
04/05/2002
07/01/2002
06/04/2003
pgs. 1, 8, 11, 14, 15 and 28.
pgs. 4, 11, 17, 22-26, 28-31, 33, 45 and 46.
pgs. 12 and 29.
pg. 50.
pgs. 7, 8, 10, 11, 14, 47 and 52.
pgs. 2 and 29.
pgs. 1 through 56.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1533
email:Flow-Controlhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
56
相关型号:
72V51246L7-5BBGI
FIFO, 32KX36, 4ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT
72V51253L6BBG8
FIFO, 128KX18, 3.7ns, Synchronous, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
IDT
©2020 ICPDF网 联系我们和版权申明