72V51256L6BBI_技术文档

3.3V MULTI-QUEUE FIFO (4 QUEUES)

36 BIT WIDE CONFIGURATION

589,824 bits, 1,179,648 bits and

2,359,296 bits

PRELIMINARY

IDT72V51236

IDT72V51246

IDT72V51256

•

4 bit parallel flag status on both read and write ports

FEATURES:

Provides continuous PAE and PAF status of up to 4 Queues

Global Bus Matching - (All Queues have same Input Bus Width

and Output Bus Width)

User Selectable Bus Matching Options:

- x36in to x36out

- x18in to x36out

- x9in to x36out

- x36in to x18out

- x36in to x9out

•

Choose from among the following memory density options:

IDT72V51236

IDT72V51246

IDT72V51256

Total Available Memory = 589,824 bits

Total Available Memory = 1,179,648 bits

Total Available Memory = 2,359,296 bits

•

Configurable from 1 to 4 Queues

Queues may be configured at master reset from the pool of

Total Available Memory in blocks of 256 x 36

Independent Read and Write access per queue

User programmable via serial port

Default Multi-Queue device configurations

-IDT72V51236: 4,096 x 36 x 4Q

•

FWFT mode of operation on read port

Packet Ready mode of operation

Partial Reset, clears data in single Queue

Expansion of up to 8 Multi-Queue devices in parallel is available

JTAG Functionality (Boundary Scan)

Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm

HIGH Performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

-IDT72V51246: 8,192 x 36 x 4Q

-IDT72V51256: 16,384 x 36 x 4Q

•

100% Bus Utilization, Read and Write on every clock cycle

166 MHz High speed operation (6ns cycle time)

3.7ns access time

Individual, Active queue flags (OV, FF, PAE, PAF, PR)

DATA PATH FLOW DIAGRAM

MULTI-QUEUE FIFO

WADEN

FSTR

RADEN

ESTR

Q

0

RDADD

6

WRADD

5

REN

WEN

RCLK

WCLK

OE

Q

D

in

out

x9, x18, x36

DATA OUT

x9, x18, x36

DATA IN

OV

FF

Q

3

PR

PAF

PAE

PAFn

4

PAEn/PRn

4

5937 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc

JANUARY 2002

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

1

DSC-5937/4

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

A packet ready mode of operation is also provided when the device is

configuredfor36bitinputand36bitoutputportsizes.ThePacketReadymode

providestheuserwithaflagoutputindicatingwhenatleastone(ormore)packets

ofdatawithinaqueueisavailableforreading.ThePacketReadyprovidesthe

userwithameans bywhichtomarkthestartandendofpackets ofdatabeing

passedthroughtheFIFOqueues.TheMulti-Queuedevicethenprovides the

userwithaninternallygeneratedpacketreadystatus perqueue.

Theuserhasfullflexibilityconfiguringqueueswithinthedevice,beingable

toprogramthetotalnumberofqueues between1and4,theindividualqueue

depthsbeingindependentofeachother.Theprogrammableflagpositionsare

alsouserprogrammable.Allprogrammingisdoneviaadedicatedserialport.

IftheuserdoesnotwishtoprogramtheMulti-Queuedevice,adefaultoptionis

availablethatconfiguresthedeviceinapredeterminedmanner.

DESCRIPTION:

TheIDT72V51236/72V51246/72V51256Multi-QueueFIFOdeviceisa

single chipwithinwhichanywhere between1and4discrete FIFOqueues

canbe setup.Allqueues withinthe device have a commondata inputbus,

(writeport)andacommondataoutputbus,(readport).Datawrittenintothe

write port is directed to a respective queue via an internal de-multiplex

operation,addressedbytheuser.Datareadfromthereadportisaccessed

froma respective queue via aninternalmultiplexoperation,addressedby

the user. Data writes and reads can be performed at high speeds up to

166MHz,withaccesstimesof3.7ns.Datawriteandreadoperationsaretotally

independent of each other, a queue maybe selected on the write port and

adifferentqueueonthereadportorbothportsmayselectthesamequeue

simultaneously.

BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster

Reset latches in all configuration setup pins and must be performed before

programmingofthedevicecantakeplace.APartialResetwillresetthereadand

writepointersofanindividualFIFOqueue,providedthatthequeueisselected

onboththe write portandreadportatthe time ofpartialreset.

AJTAGtestportisprovided,heretheMulti-QueueFIFOhasafullyfunctional

BoundaryScanfeature,compliantwithIEEE1449.1StandardTestAccessPort

andBoundaryScanArchitecture.

The device provides FullflagandOutputValidflagstatus forthe queue

selectedforwriteandreadoperations respectively.AlsoaProgrammable

AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.

Two 4 bit programmable flag busses are available, providing status of all

queues,includingqueuesnotselectedforwriteorreadoperations,theseflag

busses provide an individual flag per queue.

BusMatchingisavailableonthisdevice,eitherportcanbe9bits,18bits

or 36 bits wide provided that at least one port is 36 bits wide. When Bus

Matchingisusedthedeviceensuresthelogicaltransferofdatathroughput

inaLittleEndianmanner.

SeeFigure1,Multi-QueueFIFOBlockDiagramforanoutlineofthefunctional

blockswithinthedevice.

2

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

D

= TEOP

= TSOP

D

35

34

in

x9, x18, x36

D - D

2

0

35

WCLK

WEN

TMS

TDI

INPUT

DEMUX

JTAG

TDO

TCK

Logic

5

WRADD

WADEN

Write Control

Logic

TRST

Write Pointers

PR

Packet Mode

Logic

4

PAF

General Flag

Monitor

PRn/PAEn

FSTR

PAFn

4

FSYNC

Upto 4

FIFO

Queues

FXO

FXI

OV

Active Q

Flags

PAE

0.5 Mbit

1.1 Mbit

2.3 Mbit

Dual Port

Memory

Active Q

Flags

FF

PAF

PAE

General Flag

Monitor

SI

SO

SCLK

Serial

Multi-Queue

Programming

ESTR

ESYNC

EXI

SENI

SENO

EXO

Read Pointers

FM

IW

OW

BM

Reset

Logic

6

RDADD

RADEN

Read Control

Logic

MAST

PKT

REN

RCLK

ID0

ID1

ID2

DF

Device ID

3 Bit

OUTPUT

MUX

PAE/ PAF

2

Offset

Q

= REOP

= RSOP

DFM

35

34

OUTPUT

REGISTER

PRS

MRS

5937 drw02

OE

Q - Q

35

0

Q

x9, x18, x36

out

Figure 1. Multi-Queue Block Diagram

3

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINCONFIGURATION

A1 BALL PAD CORNER

A

D14

D15

D13

D16

D12

D11

D10

D9

D7

D6

D4

D3

D1

D0

TCK

TMS

TDO

TDI

ID1

ID0

Q3

Q2

Q6

Q9

Q8

Q7

Q12

Q11

Q14

Q13

Q15

Q19

B

C

D

E

F

Q5

TRST

VCC

GND

D17

D18

D19

D8

D5

D2

GND

VCC

ID2

VCC

GND

Q0

VCC

GND

Q1

Q4

Q10

Q16

Q24

Q27

Q30

Q33

PKT

GND

BM

Q17

Q21

Q23

Q26

Q29

Q32

Q35

MAST

IW

Q18

Q20

Q22

Q25

Q28

Q31

Q34

FM

VCC

GND

VCC

D20

D23

D26

D21

D24

D27

D22

D25

D28

VCC

GND

VCC

GND

VCC

G

H

J

D29

D32

GND

SI

D30

D31

D34

D35

GND

DF

VCC

GND

VCC

GND

VCC

GND

VCC

D33

VCC

GND

DFM

K

VCC

L

OW

M

N

P

R

T

SENO

SENI

OE

SO

VCC

GND

VCC

GND

VCC

RDADD0 RDADD1

WRADD1 WRADD0

SCLK

RDADD2 GND

GND

FF

OV

PAE

GND

WADEN

PAF3

DNC

PAE3 RDADD3 RDADD4 RDADD5

PAF

PRS

PR

WRADD3 WRADD2 FSYNC

FSTR

PAF2

PAF1

DNC

PAE2

PAE1

RADEN ESTR

ESYNC

EXI

WEN

MRS

REN

WRADD4

FXI

FXO

PAF0

WCLK

RCLK

PAE0

EXO

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

5937 drw03

PBGA (BB256-1, order code: BB)

TOP VIEW

NOTE:

1. DNC - Do Not Connect.

4

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

providesauserprogrammablealmostfullflagforall4FIFOqueuesandwhen

arespectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus

for that queue. Conversely, the read port has an output valid flag, providing

statusofthedatabeingreadfromthequeueselectedonthereadport.Aswell

astheoutputvalidflagthedeviceprovidesadedicatedalmostemptyflag.This

almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.

The device provides a user programmable almost empty flag for all 4 FIFO

queuesandwhenarespectivequeueisselectedonthereadport,thealmost

emptyflagprovidesstatusforthatqueue.

DETAILEDDESCRIPTION

MULTI-QUEUE STRUCTURE

TheIDTMulti-QueueFIFOhasasingledatainputportandsingledataoutput

portwithupto4FIFOqueuesinparallelbufferingbetweenthetwoports.The

usercansetupbetween1and4FIFOQueueswithinthedevice.Thesequeues

canbeconfiguredtoutilizethetotalavailablememory,providingtheuserwith

fullflexibilityandabilitytoconfigurethequeuestobevariousdepths,indepen-

dentofoneanother.

PROGRAMMABLE FLAG BUSSES

MEMORYORGANIZATION/ALLOCATION

Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput

valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost

fullflagstatusbusisprovided,thisbusis4bitswide.Also,analmostemptyflag

statusbusisprovided,againthisbusis4bitswide.Thepurposeoftheseflag

bussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels

within FIFO queues that may not be selected on the write or read port. As

mentioned,thedeviceprovidesalmostfullandalmostemptyregisters(program-

mable by the user) for each of the 4 FIFO queues in the device.

The4bitPAEnand4bitPAFnbussesprovideadiscretestatusoftheAlmost

EmptyandAlmostFullconditionsofall4queue's.Ifthedeviceisprogrammed

for less than 4 queue's, then there will be a corresponding number of active

outputs onthePAEnandPAFnbusses.

Theflagbussescanprovideacontinuousstatusofallqueues.Ifdevicesare

connectedinexpansionmodetheindividualflagbussescanbeleftinadiscrete

form,providingconstantstatusofallqueues,orthebussesofindividualdevices

canbe connectedtogethertoproduce a single bus of4bits. The device can

then operate in a "Polled" or "Direct" mode.

Whenoperatinginpolledmodetheflagbusprovidesstatusofeachdevice

sequentially,thatis,oneachrisingedgeofaclocktheflagbusisupdatedtoshow

thestatusofeachdeviceinorder.Therisingedgeofthewriteclockwillupdate

theAlmostFullbusandarisingedgeonthereadclockwillupdatetheAlmost

Emptybus.

Whenoperatingindirectmodethedevicedrivingtheflagbusisselectedby

theuser.Theuseraddresses thedevicethatwilltakecontrolofarespective

flagbus, these PAFnandPAEnflagbusses operatingindependentlyofone

another.AddressingoftheAlmostFullflagbus is doneviathewriteportand

addressingoftheAlmostEmptyflagbus is doneviathereadport.

Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing

256x36bits.Whentheuserisconfiguringthenumberofqueuesandindividual

queuesizestheusermustallocatethememorytorespectivequeues,inunits

ofblocks,thatis,asinglequeuecanbemadeupfrom0tomblocks,wherem

isthetotalnumberofblocksavailablewithinadevice.Alsothetotalsizeofany

given queue must be in increments of 256 x36. For the IDT72V51236/

72V51246andIDT72V51256theTotalAvailableMemoryis64,128and256

blocks respectively(a blockbeing256x36). Queues canbe builtfromthese

blocks to make any size queue desired and any number of queues desired.

BUS WIDTHS

TheinputportiscommontoallFIFOqueueswithinthedevice,asistheoutput

port.ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinput

portandoutputportcanbeeitherx9,x18orx36bitswideprovidedthatatleast

one of the ports is x36 bits wide, the read and write port widths being set

independentlyofoneanother.Becausetheportsarecommontoallqueuesthe

widthofthequeuesisnotindividuallyset,sothattheinputwidthofallqueues

are equal and the output width of all queues are equal.

WRITING TO & READING FROM THE MULTI-QUEUE

Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete

FIFOqueueviathewritequeueselectaddressinputs.Conversely,databeing

readfromthedevicereadportisreadfromaqueueselectedviathereadqueue

selectaddressinputs.Datacanbesimultaneouslywrittenintoandreadfromthe

sameFIFOqueueordifferentFIFOqueues.Onceaqueueisselectedfordata

writes or reads, the writing and reading operation is performed in the same

mannerasconventionalIDTsynchronousFIFO’s,utilizingclocksandenables,

thereisasingleclockandenableperport.Whenaspecificqueueisaddressed

on the write port, data placed on the data inputs is written to that queue

sequentiallybasedontherisingedgeofawriteclockprovidedsetupandhold

timesaremet.Conversely,dataisreadontotheoutputportafteranaccesstime

from a rising edge on a read clock.

Theoperationofthewriteportiscomparabletothefunctionofaconventional

FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon

thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput

provides status of the selected queue. The operation of the read port is

comparabletothefunctionofaconventionalFIFOoperatinginFWFTmode.

WhenaFIFOqueueisselectedontheoutputport,thenextwordinthatqueue

willautomaticallyfallthroughtotheoutputregister.Allsubsequentwordsfrom

thatqueuerequireanenabledreadcycle.Datacannotbereadfromaselected

queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating

whendata readoutis valid. Ifthe userswitches toa queue thatis empty, the

lastwordfromtheprevious queuewillremainontheoutputregister.

Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected

queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost

fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice

PACKETREADY

The36bitMulti-QueueFIFOalsooffersa”PacketReady”modeofoperation,

thisisuserselectableandrequiresthatthedevicebeconfiguredwithbothwrite

and read ports as 36 bits wide. The packet mode of operation provides

monitoringof“usermarked”locations,whentheuseriswritingdataintoaFIFO

queueawordbeingwrittenincanbemarkedasa“StartofPacket”or“Endof

Packet”. Internally as words are being written into the device with markers

attached,thedevicemonitorsthesemarkersandprovidesapacketreadystatus

flag,whichindicateswhenatleastonefullpacketisavailableinaqueue.The

readportthereforeincludesanadditionalstatusflag,“PacketReady”,thisflag

providingpacketreadystatusforthequeuecurrentlyselectedonthereadport

forreadoperations,indicatingwhenatleastone(ormore)packetsofdataare

availabletoberead.Wheninpacketreadymodethealmostemptyflagstatus

busnolongerprovidesalmostemptystatusforindividualquadrants,butinstead

providespacketreadyflagstatusforindividualquadrants.(Apacketisregarded

as anynumberofwords writtenbetweena startofpacketandendofpacket

marker,packetsizesareuserdefinedandsizesarenotcontrolledorlimitedby

thedevice).

5

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

EXPANSION

deviceutilizingallmemoryblocksavailabletoproduceasinglequeue.Thisis

ExpansionofMulti-Queuedevicesisalsopossible,upto8devicescanbe thedeepestFIFOqueuethatcansetupwithinadevice.

connectedinaparallelfashionprovidingthepossibilityofbothdepthexpansion

For queue expansion of the 4 queue device, a maximum number of 32 (8

or queue expansion. Depth Expansion means expanding the depths of x4)queuesmaybesetup,eachqueuebeing2Kx36deep,iflessqueuesare

individual queues. Queue expansion means increasing the total number of setup,thenmorememoryblockswillbeavailabletoincreasequeuedepthsif

queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore desired.WhenconnectingMulti-Queuedevicesinexpansionmodeallrespec-

memoryblockswithinaMulti-Queuedevicecanbeallocatedtoincreasethe tive input pins (data & control) and output pins (data & flags), should be

depth of a queue. For example, depth expansion of 8 devices provides the “connected”togetherbetweenindividualdevices.

possibilityof8queuesof64Kx36deep,eachqueuebeingsetupwithinasingle

6

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS

Symbol

Name

I/OTYPE

Description

BM

BusMatching

LVTTL ThispinissetupbeforeMasterResetandmustnottoggleduringanydeviceoperation.Thispinisused

INPUT alongwithIWandOWtosetupthe FIFObus width. Please refertoTable 3fordetails.

D[35:0]

Din

DataInputBus

LVTTL These are the 36data inputpins. Data is writtenintothe device via these inputpins onthe risingedge

INPUT ofWCLKprovidedthatWENisLOW.Note,thatinPacketReadymodeD32-D35maybeusedaspacket

markers,pleaseseepacketreadyfunctionaldiscussionformoredetail.Duetobusmatchingnotallinputs

maybe used, anyunusedinputs shouldbe tiedLOW.

DF⁽¹⁾

DefaultFlag

DefaultMode

LVTTL IftheuserrequiresdefaultprogrammingoftheMulti-Queuedevice,thispinmustbesetupbeforeMaster

INPUT Resetandmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines

the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.

(1)

DFM

LVTTL TheMulti-Queuedevicerequiresprogrammingaftermasterreset.Theusercandothisseriallyviathe

INPUT serialport,ortheusercanusethedefaultmethod.IfDFMisLOWatmasterresetthenserialmodewillbe

selected,ifHIGHthendefaultmodeisselected.

ESTR

PAEn Flag Bus

Strobe

LVTTL IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK

INPUT andtheRDADDbustoselectadeviceforitsqueuestobeplacedontothePAEnbusoutputs.Adevice

addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If

Polledoperationshasbeenselected,ESTRshouldbetiedinactive,LOW.

ESYNC

PAEnBus Sync

LVTTL ESYNCisanoutputfromtheMulti-QueuedevicethatprovidesasynchronizingpulseforthePAEnbus

OUTPUT duringPolledoperationofthePAEnbus.DuringPolledoperationeachdevicesqueuestatusflagsare

loadedontothePAEnbusoutputssequentiallybasedonRCLK.ThefirstRCLKrisingedgeloadsdevice1

ontoPAEn,thesecondRCLKrisingedgeloadsdevice2andsoon.DuringtheRCLKcyclethataselected

device is placed on to the PAEn bus, the ESYNC output will be HIGH.

EXI

PAEn/PRnBus

ExpansionIn

LVTTL TheEXIinputis usedwhenMulti-Queuedevices areconnectedinexpansionmodeandPolledPAEn/

INPUT PRnbus operationhas beenselected. EXIofdevice ‘N’connects directlytoEXOofdevice ‘N-1’. The

EXIreceivesatokenfromthepreviousdeviceinachain.InsingledevicemodetheEXIinputshouldbe

tiedLOWifthePAEn/PRnbusisoperatedindirectmode.IfthePAEn/PRnbusisoperatedinpolledmode

theEXIinputshouldbeconnectedtotheEXOoutputofthesamedevice.InexpansionmodetheEXIof

thefirstdeviceshouldbetiedLOW,whendirectmodeisselected.

EXO

PAEn/PRnBus

ExpansionOut

LVTTL EXOisanoutputthatisusedwhenMulti-QueuedevicesareconnectedinexpansionmodeandPolled

OUTPUT PAEn/PRnbusoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.

ThispinpulsesHIGHwhendeviceNplacesitsPAEstatusontothePAEn/PRnbuswithrespecttoRCLK.

This pulse (token) is then passed on to the next device in the chain ‘N+1’ and on the next RCLK rising

edgethefirstquadrantofdeviceN+1willbeloadedontothePAEn/PRnbus.Thiscontinuesthroughthe

chainandEXOofthelastdeviceisthenloopedbacktoEXIofthefirstdevice.TheESYNCoutputofeach

deviceinthechainprovides synchronizationtotheuserofthis loopingevent.

FF

Full Flag

LVTTL This pinprovides thefullflagoutputfortheactiveFIFOqueue,thatis,thequeueselectedontheinput

OUTPUT portforwrite operations, (selectedvia WCLK, WRADDbus andWADEN). Onthe WCLKcycle aftera

queueselection,thisflagwillshowthestatusofthenewlyselectedqueue.Datacanbewrittentothisqueue

onthenextcycleprovidedFFisHIGH.ThisflaghasHigh-Impedancecapability,thisisimportantduring

expansionofdevices,whentheFFflagoutputofupto8devicesmaybeconnectedtogetheronacommon

line.ThedevicewithaqueueselectedtakescontroloftheFFbus,allotherdevicesplacetheirFFoutput

intoHigh-Impedance.Whenaqueueselectionismadeonthewriteportthisoutputwillswitchfrom

High-ImpedancecontrolonthenextWCLKcycle.ThisflagissynchronizedtoWCLK.

(1)

FM

Flag Mode

LVTTL Thispinissetupbeforeamasterresetandmustnottoggleduringanydeviceoperation.Thestateofthe

INPUT FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbussesoperateineitherPolled

orDirectmode.Ifthis pinis HIGHthemodeis Polled,ifLOWthenitwillbeDirect.

FSTR

PAFn Flag Bus

Strobe

LVTTL IfdirectoperationofthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK

INPUT andtheWRADDbustoselectadeviceforitsqueuestobeplacedontothe PAFnbusoutputs.Adevice

addressedviatheWRADDbus is selectedontherisingedgeofWCLKprovidedthatFSTRis HIGH.If

Polledoperationshasbeenselected,FSTRshouldbetiedinactive,LOW.

FSYNC

PAFn Bus Sync

LVTTL FSYNCisanoutputfromtheMulti-QueuedevicethatprovidesasynchronizingpulseforthePAFnbus

OUTPUT duringPolledoperationofthePAFnbus.DuringPolledoperationeachquadrantofqueuestatusflagsis

loadedontothePAFnbusoutputssequentiallybasedonWCLK.ThefirstWCLKrisingedgeloadsdevice1

7

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/OTYPE

Description

FSYNC

(Continued)

PAFn Bus Sync

LVTTL ontothePAFnbusoutputs,thesecondWCLKrisingedgeloadsdevice2andsoon.DuringtheWCLK

OUTPUT cycle thata selecteddevice is placedontothePAFnbus, the FSYNCoutputwillbe HIGH.

FXI

PAFnBus

ExpansionIn

LVTTL The FXIinputis usedwhenMulti-Queue devices are connectedinexpansionmode andPolled PAFn

INPUT bus operation has been selected. FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI

receivesatokenfromthepreviousdeviceinachain.InsingledevicemodetheFXIinputshouldbetied

LOWifthePAEnbusisoperatedindirectmode.IfthePAEnbusisoperatedinpolledmodetheFXIinput

shouldbeconnectedtotheFXOoutputofthesamedevice.InexpansionmodetheFXIofthefirstdevice

shouldbetiedLOW,whendirectmodeisselected.

FXO

PAFnBus

ExpansionOut

LVTTL FXOisanoutputthatisusedwhenMulti-QueuedevicesareconnectedinexpansionmodeandPolled

OUTPUT PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This

pinpulsesHIGHwhendeviceNplacesitsPAFstatusontothePAFnbuswithrespecttoWCLK.Thispulse

(token)isthenpassedontothenextdeviceinthechain‘N+1’andonthenextWCLKrisingedgethefirst

quadrantofdevice N+1willbe loadedontothe PAFnbus. This continues throughthe chainandFXO

ofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdeviceinthe

chainprovidessynchronizationtotheuserofthisloopingevent.

(1)

ID[2:0]

Device ID Pins

LVTTL Forthe4QMulti-QueuedevicetheWRADDaddressbusis5bitsandRDADDaddressbusis6bitswide.

INPUT Whenaqueueselectiontakesplacethe3MSB’softhisaddressbusareusedtoaddressthespecificdevice

(theLSB’sareusedtoaddressthequeuewithinthatdevice).Duringwrite/readoperationsthe3MSB’s

oftheaddressarecomparedtothedeviceIDpins.ThefirstdeviceinachainofMulti-Queue’s(connected

inexpansionmode),maybesetupas‘000’,thesecondas‘001’andsoonthroughtodevice8whichis

‘111’,howevertheIDdoesnothavetomatchthedeviceorder.Insingledevicemodethesepinsshould

besetupas‘000’andthe3MSB’softheWRADDandRDADDaddressbussesshouldbetiedLOW.The

ID[2:0]inputssetuparespectivedevicesIDduringmasterreset.TheseIDpinsmustnottoggleduring

any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.

(1)

IW

InputWidth

LVTTL ThispinisusedinconjunctionwithOWandBMtosetuptheinputandoutputbuswidthstobeacombination

INPUT of x9, x18 or x36, (providing that one port is x36).

(1)

MAST

MasterDevice

LVTTL ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe

INPUT MasterdeviceoraSlave.IfthispinisHIGH,thedeviceisthemaster,ifitisLOWthenitisaSlave.Themaster

deviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgotoHigh-Impedance,

preventingbuscontention.IfaMulti-Queuedeviceisbeingusedinsingledevicemode,thispinmust

be setHIGH.

MRS

OE

MasterReset

OutputEnable

LVTTL AmasterresetisperformedbytakingMRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired

INPUT aftermasterreset.

LVTTL TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontroloftheMulti-Queue

INPUT dataoutputbus,Qout.Ifadevicehasbeenconfiguredasa“Master”device,theQoutdataoutputswill

beinaLowImpedanceconditioniftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbe

inHighImpedance.Ifadeviceisconfigureda“Slave”device,thentheQoutdataoutputswillalwaysbe

inHighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpointOEprovidesthree-

stateofthatrespectivedevice.

OV

OutputValidFlag

OutputWidth

LVTTL ThisoutputflagprovidesoutputvalidstatusforthedatawordpresentontheMulti-QueueFIFOdataoutput

OUTPUT port,Qout.Thisflagistherefore,2-stagedelayedtomatchthedataoutputpathdelay.Thatis,thereis

a2RCLKcycledelayfromthetimeagivenqueueisselectedforreads,tothetimetheOVflagrepresents

thedatainthatrespectivequeue.Whenaselectedqueueonthereadportisreadtoempty,theOVflag

willgoHIGH,indicatingthatdataontheoutputbus is notvalid.The OVflagalsohas High-Impedance

capability,requiredwhenmultipledevices areusedandtheOVflags aretiedtogether.

(1)

OW

LVTTL ThispinissetupduringMasterResetandmustnottoggleduringanydeviceoperation.Thispinisused

INPUT inconjunctionwithIWandBMtosetupthedatainputandoutputbuswidthstobeacombinationofx9,

x18 or x36, (providing that one port is x36).

PAE

Programmable

Almost-EmptyFlag

LVTTL ThispinprovidestheAlmost-EmptyflagstatusfortheFIFOqueuethathasbeenselectedontheoutput

OUTPUT portforreadoperations,(selectedviaRCLK,RDADDandRADEN).ThispinisLOWwhentheselected

FIFOqueuealmost-empty.This flagoutputmaybeduplicatedononeofthe PAEnbus lines.This flag

is synchronizedtoRCLK.

8

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/OTYPE

Description

PAEn/PRn Programmable

Almost-EmptyFlag

Bus/PacketReady

FlagBus

LVTTL On the 4Q device the PAEn/ PRn bus is 4 bits wide. During a Master Reset this bus is setup for either

OUTPUT AlmostEmptymodeorPacketReadymode.Thisoutputbusprovides PAE/PRnstatusofall4queues,

withinaselecteddevice.DuringFIFOread/writeoperationstheseoutputsprovideprogrammableempty

flagstatusorpacketreadystatus,ineitherdirectorpolledmode.Themodeofflagoperationisdetermined

duringmasterresetviathestateoftheFMinput.ThisflagbusiscapableofHigh-Impedancestate,this

is importantduringexpansionofMulti-Queuedevices.Duringdirectoperationthe PAEn/PRnbusis

updatedtoshowthePAE/PRstatusofqueueswithinaselecteddevice.SelectionismadeusingRCLK,

ESTR and RDADD. During Polled operation the PAEn/PRn bus is loaded with the PAE/ PRn status

of Multi-Queue FIFO devices sequentially based on the rising edge of RCLK. PAE or PR operation is

determinedbythestateofPKTduringmasterreset.

PAF

Programmable

Almost-FullFlag

LVTTL ThispinprovidestheAlmost-FullflagstatusfortheFIFOqueuethathasbeenselectedontheinput

OUTPUT portforwriteoperations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselected

FIFOqueueisalmost-full.Thisflagoutputmaybeduplicatedononeofthe PAFnbuslines.Thisflagis

synchronizedtoWCLK.

PAFn

Programmable

LVTTL Onthe4QdevicethePAFnbusis4bitswide.ThisoutputbusprovidesPAFstatusofall4queues,within

Almost-FullFlagBus OUTPUT aselecteddevice.DuringFIFOread/writeoperationstheseoutputsprovideprogrammablefullflagstatus,

ineitherdirectorpolledmode.Themodeofflagoperationisdeterminedduringmasterresetviathestate

oftheFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansionof

Multi-Queuedevices.DuringdirectoperationthePAFnbusisupdatedtoshowthePAFstatusofaqueues

withinaselecteddevice.SelectionismadeusingWCLK,FSTR,WRADDandWADEN.DuringPolled

operationthePAFnbusisloadedwiththe PAFstatusofMulti-QueueFIFOdevicessequentiallybased

onthe risingedge ofWCLK.

(1)

PKT

PacketMode

LVTTL ThestateofthispinduringaMasterResetwilldeterminewhetherthepartisoperatinginPacketReady

INPUT modeprovidingbothaPacketReady(PR)outputandaProgrammableAlmostEmpty(PAE)discrete

output,orstandardmode,providinga(PAE)outputonly.IfthispinisHIGHduringMasterResetthepart

willoperateinpacketreadymode,ifitisLOWthenalmostemptymode.Ifpacketmodehasbeenselected

the readportflagbus becomes packetreadyflagbus, PRnandthe discrete packetreadyflag, PR is

functional.Ifalmostemptyoperationhasbeenselectedthentheflagbusprovidesalmostemptystatus,PAEn

andthediscretealmostemptyflag,PAEisfunctional,thePRflagisinactiveandshouldnotbeconnected.

PacketReadyutilizesusermarkedlocationstoidentifystartandendofpacketsbeingwrittenintothedevice.

PacketModecanonlybeselectedifboththeinputportwidthandoutputportwidthare36bits.

PR

PacketReadyFlag

LVTTL IfpacketreadymodehasbeenselectedthisflagoutputprovidesPacketReadystatusoftheFIFOqueue

OUTPUT selectedforreadoperations.DuringamasterresetthestateofthePKTinputdetermineswhetherPacket

modeofoperationwillbeused.IfPacketmodeisselected,thenthePRflagbecomesavalidoutput,from

whichtheusercandetermineifaselectedFIFOqueuehasa“complete”packetofdataavailableforreading.

Theusermustmarkthestartofapacketandtheendofapacketwhenwritingdataintoaqueue.Using

theseStartOfPacket(SOP)andEndOfPacket(EOP)markers,theMulti-Queuedevicesets PRLOW

ifone ormore “complete”packets are available inthe queue.

PRS

PartialReset

LVTTL APartialResetcanbeperformedonasinglequeueselectedwithintheMulti-Queuedevice.BeforeaPartial

INPUT Resetcanbe performedona queue, thatqueue mustbe selectedonboththe write portandreadport

2clockcycles beforetheresetis performed.APartialResetis thenperformedbytakingPRS LOWfor

one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to

thefirstmemorylocation,noneofthedevicesconfigurationwillbechanged.

Q[35:0]

Qout

DataOutputBus

LVTTL Thesearethe36dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge

OUTPUT ofRCLKprovidedthatRENisLOW,OEisLOWandtheFIFOqueueisselected.Note,thatinPacketReady

modeQ32-Q35maybeusedaspacketmarkers,pleaseseepacketreadyfunctionaldiscussionformore

detail.Duetobusmatchingnotalloutputsmaybeused,anyunusedoutputsshouldnotbeconnected.

RADEN

RCLK

ReadAddress Enable LVTTL The RADENinputis usedinconjunctionwithRCLKandthe RDADDaddress bus toselecta queue to

INPUT be read from. A FIFO queue addressed via the RDADD bus is selected on the rising edge of RCLK

provided that RADEN is HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR.

ReadClock

LVTTL WhenenabledbyREN,therisingedgeofRCLKreadsdatafromtheselectedFIFOqueueviatheoutput

INPUT busQout.TheFIFOqueuetobereadisselectedviatheRDADDaddressbusandarisingedgeofRCLK

whileRADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthe

9

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/OTYPE

Description

RCLK

(Continued)

ReadClock

LVTTL devicetobeplacedonthePAEn/PRnbusduringdirectflagoperation.Duringpolledflagoperationthe

INPUT PAEn/PRnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronizedtoRCLK.ThePAE,

PR andOV outputs are allsynchronizedtoRCLK. Duringdevice expansionthe EXOandEXIsignals

are based on RCLK. RCLK must be continuous and free-running.

RDADD

[5:0]

Read Address Bus

LVTTL For the 4Q device the RDADD bus is 6 bits. The RDADD bus is a dual purpose address bus. The first

INPUT functionofRDADDis toselectaFIFOqueuetobereadfrom.Theleastsignificant2bits ofthebus,

RDADD[1:0] are used to address 1 of 4 possible queues within a Multi-Queue device. Address pin,

RDADD[2]providestheuserwithaNull-Qaddress.Iftheuserdoesnotwishtoaddressoneofthe4queues,

aNull-Qcanbeaddressedusingthispin.TheNull-Qoperationisdiscussedinmoredetaillater.Themost

significant3bits,RDADD[5:3]areusedtoselect1of8possibleMulti-Queuedevicesthatmaybeconnected

inexpansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent

ontheRDADDbuswillbeselectedonarisingedgeofRCLKprovidedthatRADENisHIGH,(note,that

datacanbeplacedontotheQoutbus,readfromthepreviouslyselectedFIFOqueueonthisRCLKedge).

On the next rising RCLK edge after a read queue select, a data word from the previous queue will be

placedontotheoutputs,Qout,regardlessoftheRENinput.TwoRCLKrisingedgesafterreadqueueselect,

datawillbeplacedontotheQoutoutputsfromthenewlyselectedqueue,regardlessofRENduetothe

firstwordfallthrougheffect.

The second function of the RDADDbus is toselect the device of FIFOqueues tobe loadedon to the

PAEn/PRnbusduringstrobedflagmode.Themostsignificant3bits,RDADD[5:3]areagainusedtoselect1

of8possibleMulti-Queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsRDADD[2:0]

aredon’t careduringdeviceselection.ThedeviceaddresspresentontheRDADDbuswillbeselected

onthe risingedge ofRCLKprovidedthatESTRis HIGH, (note, thatdata canbe placedontothe Qout

bus, readfromthe previouslyselectedFIFOQonthis RCLKedge). Please refertoTable 2fordetails

on RDADD bus.

REN

ReadEnable

LVTTL The RENinputenables readoperations fromaselectedFIFOqueuebasedonarisingedgeofRCLK.

INPUT Aqueue tobe readfromcanbe selectedvia RCLK, RADENandthe RDADDaddress bus regardless

ofthestateofREN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond

RCLKcycle afterqueue selectionregardless ofREN due tothe FWFToperation. Areadenable is not

required to cycle the PAEn/PRn bus (in polled mode) or to select the device , (in direct mode).

SCLK

SerialClock

LVTTL IfserialprogrammingoftheMulti-Queuedevicehasbeenselectedduringmasterreset,theSCLKinput

INPUT clockstheserialdatathroughtheMulti-Queuedevice.DatasetupontheSIinputisloadedintothedevice

ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed

theSCLKofalldevices shouldbeconnectedtothesamesource.

SENI

SerialInputEnable

LVTTL DuringserialprogrammingofaMulti-Queuedevice,dataloadedontotheSIinputwillbeclockedintothe

INPUT part(via a risingedge ofSCLK), providedthe SENI inputofthatdevice is LOW. Ifmultiple devices are

cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial

loadingofagivendeviceiscomplete,its SENOoutputgoesLOW,allowingthenextdeviceinthechain

tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI

inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.

SENO

SerialOutputEnable LVTTL ThisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingoftheMulti-Queuedevice

OUTPUT hasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO

willgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENOwillalso

goHIGH.WhentheSENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.

Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENO output

shouldbeconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogrammingofthe

firstdeviceiscomplete, SENOwillgoLOW,therebytakingtheSENIinputofthenextdeviceLOWand

soonthroughoutthe chain. Whena givendevice inthe chainis fullyprogrammedthe SENO output

essentiallyfollowstheSENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.

WhenthisoutputgoesLOW,serialloadingofalldeviceshasbeencompleted.

SI

SerialIn

LVTTL DuringserialprogrammingthispinisloadedwiththeserialdatathatwillconfiguretheMulti-Queuedevices.

INPUT Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion

modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO

10

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/OTYPE

Description

SI

SerialIn

LVTTL hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice

INPUT connectstotheSIpinofthesecondandsoon.TheMulti-Queuedevicesetupregistersareshiftregisters.

(Continued)

SO

SerialOut

LVTTL Thisoutputisusedinexpansionmodeandallowsserialdatatobepassedthroughdevicesinthechain

OUTPUT tocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdeviceinthe

chain. The SOofthe finaldevice ina chainshouldnotbe connected.

TCK

TDI

JTAGClock

LVTTL ClockinputforJTAGfunction. TMSandTDIare sampledonthe risingedge ofTCK. TDOis outputon

INPUT thefallingedgeofTCK.

TestDataInput

TestDataOutput

LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK.

INPUT This is alsothedatafortheInstructionRegister,JTAGIDRegisterandBypass Register.

TDO

LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK.

OUTPUT ThisoutputisinHigh-ImpedanceexceptwhenshiftingdatawhileinSHIFT-DRandSHIFT-IRcontroller

states.

TMS

JTAGModeSelect

JTAGReset

LVTTL TMSis a serialinputpin. Bits are seriallyloadedonthe risingedge ofTCK, whichselects 1of5modes

INPUT ofoperationforthe JTAGboundaryscan.

TRST

LVTTL TRSTistheasynchronousresetpinfortheJTAGcontroller.IftheJTAGportisnotutilized,TRSTshould

INPUT be tiedtoGND.

WADEN WriteAddressEnable LVTTL TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto

INPUT be written in to. A FIFO queue addressed via the WRADD bus is selected on the rising edge of WCLK

providedthatWADENis HIGH. WADENcannotbe HIGHforthe same WCLKcycle as FSTR.

WCLK

WriteClock

LVTTL WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheselectedFIFOqueueviatheinput

INPUT bus, Din. The FIFO queue to be written to is selected via the WRADD address bus and a rising edge

ofWCLKwhileWADENisHIGH.ArisingedgeofWCLKinconjunctionwithFSTRandWRADDwillalso

selectthedevicetobeplacedonthePAFnbusduringdirectflagoperation.Duringpolledflagoperation

thePAFnbusiscycledwithrespecttoWCLKandtheFSYNCsignalissynchronizedtoWCLK.ThePAFn,

PAFandFF outputs areallsynchronizedtoWCLK.DuringdeviceexpansiontheFXOandFXIsignals

are basedonWCLK. The WCLKmustbe continuous andfree-running.

WEN

WriteEnable

LVTTL The WEN input enables write operations to a selected FIFO queue based on a rising edge of WCLK.

INPUT AqueuetobewrittentocanbeselectedviaWCLK,WADENandtheWRADDaddress bus regardless

ofthestateofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLK

cycleafterqueueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFn

bus (in polled mode) or to select the device , (in direct mode).

WRADD WriteAddressBus

[4:0]

LVTTL Forthe 4Qdevice the WRADDbus is 5bits. The WRADDbus is a dualpurpose address bus. The first

INPUT functionofWRADDistoselectaFIFOqueuetobewrittento.Theleastsignificant2bitsofthebus,

WRADD[1:0]areusedtoaddress1of4possiblequeueswithinaMulti-Queuedevice.Themostsignificant

3bits,WRADD[4:2]areusedtoselect1of8possibleMulti-Queuedevices thatmaybeconnectedin

expansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent

ontheWRADDbuswillbeselectedonarisingedgeofWCLKprovidedthatWADENisHIGH,(note,that

datapresentontheDinbuscanbewrittenintothepreviouslyselectedFIFOqueueonthisWCLKedge

andonthenextrisingWCLKalso,providingthatWENisLOW).TwoWCLKrisingedgesafterwritequeue

select,datacanbewrittenintothenewlyselectedqueue.

The secondfunctionofthe WRADDbus is toselectthe device ofFIFOqueues tobe loadedontothe

PAFnbusduringstrobedflagmode.Themostsignificant3bits,WRADD[4:2]areagainusedtoselect

1of8possibleMulti-Queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsWRADD[1:0]

aredon’tcareduringdeviceselection.ThedeviceaddresspresentontheWRADDbuswillbeselected

ontherisingedgeofWCLKprovidedthatFSTRisHIGH,(note,thatdatacanbewrittenintothepreviously

selectedFIFO queue on this WCLKedge). Please refertoTable 1 for details onthe WRADD bus.

VCC

GND

NOTE:

+3.3VSupply

GroundPin

Power These are VCC power supply pins and must all be connected to a +3.3V supply rail.

Power These are Ground pins and must all be connected to the GND supply rail.

1. Inputs should not change after Master Reset.

11

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ABSOLUTEMAXIMUMRATINGS

RECOMMENDED DC OPERATING

CONDITIONS

Symbol

Rating

Com'l & Ind'l

Unit

Symbol

Parameter

Min. Typ.

Max.

3.45

0

Unit

V

VTERM

TerminalVoltage

with respect to GND

–0.5to+4.5

V

(1)

VCC

SupplyVoltage(Com'l/Ind'l)

3.15

0

3.3

0

TSTG

IOUT

StorageTemperature

DCOutputCurrent

–55 to +125

–50 to +50

°C

GND SupplyVoltage(Com'l/Ind'l)

V

mA

VIH

VIL

TA

InputHighVoltage(Com'l/Ind'l)

InputLowVoltage(Com'l/Ind'l)

OperatingTemperatureCommercial

OperatingTemperatureIndustrial

2.0

—

0

—

VCC+0.3

0.8

V

NOTE:

V

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

+70

°C

TA

-40

+85

NOTE:

1. V^CC= 3.3V ± 0.15V, JEDEC JESD8-A compliant.

DCELECTRICALCHARACTERISTICS

(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant)

Symbol

Parameter

Min.

Max.

Unit

(1)

ILI

InputLeakageCurrent

OutputLeakageCurrent

–10

2.4

—

10

µA

V

(2)

ILO

VOH

Output Logic “1” Voltage, IOH = –8 mA

Output Logic “0” Voltage, IOL = 8 mA

Active Power Supply Current

StandbyCurrent

—

0.4

100

25

VOL

V

ICC1^(3,4,5)

ICC2^(3,6)

—

mA

—

NOTES:

1. Measurements with 0.4 ≤ VIN ≤ VCC.

2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

3. Tested with outputs open (IOUT = 0).

4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

5. Typical I^CC1= 16 + 3.14*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,

C^L= capacitive load (in pF).

6. RCLK and WCLK, toggle at 20 MHz.

The following inputs should be pulled to GND: WRADD, RDADD, WADEN, RADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.

The following inputs should be pulled to V^CC: WEN, REN, SENI, PRS, MRS, TDI, TMS and TRST.

All other inputs are don't care, and should be pulled HIGH or LOW.

CAPACITANCE(TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

Max.

Unit

(2)

CIN

Input

VIN = 0V

10

pF

Capacitance

(1,2)

COUT

Output

VOUT = 0V

10

pF

Capacitance

NOTES:

1. With output deselected, (OE ≥ V^IH).

2. Characterized values, not currently tested.

12

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

AC TEST LOADS

ACTESTCONDITIONS

InputPulseLevels

GND to 3.0V

1.5ns

V

CC/2

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

OutputLoad

1.5V

50Ω

Z0 = 50Ω

1.5V

See Figure 2a & 2b

I/O

5937 drw04

Figure 2a. AC Test Load

6

5

4

3

2

1

20 30 50 80 100

Capacitance (pF)

200

5937 drw04a

Figure 2b. Lumped Capacitive Load, Typical Derating

13

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ACELECTRICALCHARACTERISTICS

(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant)

(1)

Commercial

Com'l & Ind'l

IDT72V51236L6

IDT72V51246L6

IDT72V51256L6

IDT72V51236L7-5

IDT72V51246L7-5

IDT72V51256L7-5

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

fC

Clock Cycle Frequency (WCLK & RCLK)

DataAccessTime

—

0.6

6

166

3.7

—

3.7

10

—

0.6

7.5

3.5

2.0

0.5

2.0

0.5

10

133

4

MHz

ns

MHz

ns

tA

tCLK

tCLKH

tCLKL

tDS

Clock Cycle Time

—

4

Clock High Time

2.7

2

Clock Low Time

DataSetupTime

tDH

DataHoldTime

0.5

2

tENS

EnableSetupTime

tENH

tRS

EnableHoldTime

0.5

10

ResetPulseWidth

tRSS

ResetSetupTime

15

tRSR

tPRSS

tPRSH

tOLZ(OE-Qn)⁽²⁾

ResetRecoveryTime

10

PartialResetSetup

2.0

0.5

0.6

—

100

45

2.5

0.5

0.6

—

100

45

PartialResetHold

OutputEnabletoOutputinLow-Impedance

OutputEnabletoOutputinHigh-Impedance

OutputEnabletoDataOutputValid

Clock Cycle Frequency (SCLK)

Serial Clock Cycle

(2)

tOHZ

4

tOE

4

fS

10

—

20

4

tSCLK

tSCKH

tSCKL

tSDS

tSDH

tSENS

tSENH

tSDO

tSENO

tSDOP

tSENOP

tPCWQ

tPCRQ

tAS

—

20

Serial Clock High

Serial Clock Low

45

SerialDataInSetup

20

Serial Data In Hold

1.2

20

1.2

20

SerialEnableSetup

SerialEnableHold

1.2

—

1.5

20

1.2

—

1.5

20

SCLK to Serial Data Out

SCLK to Serial Enable Out

SerialDataOutPropagationDelay

SerialEnablePropagationDelay

ProgrammingCompletetoWriteQueueSelection

ProgrammingCompletetoReadQueueSelection

AddressSetup

20

3.7

—

3.7

—

3.7

4

—

20

2.5

1

3.0

1

—

5

tAH

Address Hold

tWFF

tROV

tSTS

tSTH

tQS

Write ClocktoFullFlag

ReadClocktoOutputValid

StrobeSetup

—

2

—

2

5

—

4

StrobeHold

0.5

2

0.5

2.5

0.5

0.6

QueueSetup

tQH

QueueHold

0.5

0.6

tWAF

tRAE

tPAF

tPAE

WCLK to PAF flag

RCLK to PAE flag

4

Write ClocktoSynchronous Almost-FullFlagBus

4

Read Clock to Synchronous Almost-Empty Flag Bus

4

NOTE:

1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order.

2. Values guaranteed by design, not currently tested.

14

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ACELECTRICALCHARACTERISTICS(CONTINUED)

(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant)

(1)

Commercial

Com'l & Ind'l

IDT72V51236L6

IDT72V51246L6

IDT72V51256L6

IDT72V51236L7-5

IDT72V51246L7-5

IDT72V51256L7-5

Symbol

Parameter

Min.

0.6

4.5

6

Max.

Min.

0.6

5.75

7.5

12

Max.

4

Unit

ns

(2)

tPAELZ

RCLK to PAE Flag Bus to Low-Impedance

RCLK to PAE Flag Bus to High-Impedance

WCLK to PAF Flag Bus to Low-Impedance

WCLK to PAF Flag Bus to High-Impedance

WCLKtoFullFlagtoHigh-Impedance

3.7

—

(2)

tPAEHZ

4

(2)

tPAFLZ

4

(2)

tPAFHZ

4

(2)

tFFHZ

4

(2)

tFFLZ

WCLKtoFullFlagtoLow-Impedance

4

(2)

tOVLZ

RCLKtoOutputValidFlagtoLow-Impedance

RCLKtoOutputValidFlagtoHigh-Impedance

WCLK to PAF Bus Sync to Output

WCLK to PAF Bus Expansion to Output

RCLK to PAE Bus Sync to Output

4

(2)

tOVHZ

4

tFSYNC

tFXO

4

tESYNC

tEXO

4

RCLK to PAE Bus Expansion to Output

RCLK to Packet Ready Flag

4

tPR

4

tSKEW1

tSKEW2

tSKEW3

tSKEW4

tSKEW5

SKEW time between RCLK and WCLK for FF and OV

SKEW time between RCLK and WCLK for PAF and PAE

SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7]

SKEW time between RCLK and WCLK for PR and OV

—

6

SKEW time between RCLK and WCLK for OV when in Packet

10

Ready Mode

tXIS

tXIH

ExpansionInputSetup

ExpansionInputHold

1.0

0.5

—

1.3

0.5

—

ns

NOTE:

1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order.

2. Values guaranteed by design, not currently tested.

15

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Once the master reset is complete and MRS is HIGH, the device can be

seriallyloaded.DatapresentontheSI(serialin),inputisloadedintotheserial

port on a rising edge of SCLK (serial clock), provided that SENI (serial in

enable),isLOW.Onceserialprogrammingofthedevicehasbeensuccessfully

completedthedevicewillindicatethisviatheSENO(serialoutputenable)going

active,LOW.Upondetectionofcompletionofprogramming,theusershould

ceaseallprogrammingandtakeSENIinactive,HIGH.Note,SENOfollowsSENI

onceprogrammingofadeviceiscomplete.Therefore,SENOwillgoLOWafter

programmingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENO

willalsogoHIGH.TheoperationoftheSOoutputissimilar,whenprogramming

ofagivendeviceiscomplete,theSOoutputwillfollowtheSIinput.

FUNCTIONALDESCRIPTION

MASTERRESET

AMasterResetisperformedbytogglingtheMRSinputfromHIGHtoLOW

toHIGH.DuringamasterresetallinternalMulti-Queuedevicesetupandcontrol

registersareinitializedandrequireprogrammingeitherseriallybytheuservia

theserialport,orusingthedefaultsettings.Duringamasterresetthestateof

thefollowinginputsdeterminethefunctionalityofthepart,thesepinsshouldbe

held HIGH or LOW.

PKT–PacketMode

FM – Flag bus Mode

Ifdevicesarebeingusedinexpansionmodetheserialportsofdevicesshould

becascaded.Theusercanloadalldevicesviatheserialinputportcontrolpins,

SI & SENI, of the first device in the chain. Again, the user may utilize the ‘C’

programtogeneratetheserialbitstream,theprogrampromptingtheuserfor

the numberofdevices tobe programmed. The SENO andSO(serialout)of

thefirstdeviceshouldbeconnectedtothe SENI andSIinputs ofthesecond

devicerespectivelyandsoon,withtheSENO&SOoutputsconnectingtothe

SENI&SIinputsofalldevicesthroughthechain.Alldevicesinthechainshould

beconnectedtoacommonSCLK.Theserialoutputportofthefinaldeviceshould

be monitored by the user. When SENO of the final device goes LOW, this

indicates thatserialprogrammingofalldevices has beensuccessfullycom-

pleted.Upondetectionofcompletionofprogramming,theusershouldceaseall

programmingandtakeSENIofthefirstdeviceinthechaininactive,HIGH.

Asmentioned,thefirstdeviceinthechainhasitsserialinputportcontrolled

bytheuser,thisisthefirstdevicetohaveitsinternalregistersseriallyloaded

bytheserialbitstream.Whenprogrammingofthisdeviceiscompleteitwilltake

its SENOoutputLOWandbypasstheserialdataloadedontheSIinputtoits

SOoutput.Theserialinputoftheseconddeviceinthechainisnowloadedwith

thedatafromtheSOofthefirstdevice,whiletheseconddevicehasits SENI

input LOW. This process continues through the chain until all devices are

programmedandtheSENOofthefinaldevicegoesLOW.

IW,OW,BM–BusMatchingoptions

MAST – Master Device

ID0, 1, 2 – Device ID

DFM–Programmingmode,serialordefault

DF – Offset value for PAE andPAF

Onceamasterresethastakenplace,thedevicemustbeprogrammedeither

seriallyorviathedefaultmethodbeforeanyFIFOread/writeoperations can

begin.

See Figure 4, Master Reset for relevant timing.

PARTIALRESET

APartialResetisameansbywhichtheusercanresetboththereadandwrite

pointers ofa single queue thathas beensetupwithina Multi-Queue device.

Beforeapartialresetcantakeplaceonaqueue,therespectivequeuemustbe

selectedonboththereadportandwriteportaminimumof2RCLKand2WCLK

cyclesbeforethePRSgoesLOW.Thepartialresetisthenperformedbytoggling

thePRSinputfromHIGHtoLOWtoHIGH,maintainingtheLOWstateforatleast

oneWCLKandoneRCLKcycle.Onceapartialresethastakenplaceaminimum

of3WCLKand3RCLKcyclesmustoccurbeforeenabledwritesorreadscan

occur.

APartialResetonlyresets thereadandwritepointers ofagivenqueue,a

partialresetwillnoteffecttheoverallconfigurationandsetupoftheMulti-Queue

deviceandits queues.

Once all serial programming has been successfully completed, normal

operations,(queueselectionsonthereadandwriteports)maybegin.When

connectedinexpansionmode,theIDT72V51236/72V51246/72V51256de-

vicesrequireatotalnumberofseriallyloadedbitsperdevicetocompleteserial

programming,(SCLKcycleswithSENIenabled),calculatedby:n[19+(Qx72)]

whereQis thenumberofqueues theuserwishes tosetupwithinthedevice,

where n is the number of devices in the chain.

See Figure 5, PartialReset for relevanttiming.

SERIAL PROGRAMMING

TheMulti-QueueFIFOdeviceisafullyprogrammabledevice,providingthe

userwithflexibilityinhowFIFOqueuesareconfiguredintermsofthenumber

of queues, depth of each queue and position of the PAF/PAE flags within

respectivequeues.Alluserprogrammingisdoneviatheserialportafteramaster

resethastakenplace.InternallytheMulti-Queuedevicehassetupregisters

whichmustbeseriallyloaded,theseregisterscontainvaluesforeveryqueue

within the device, such as the depth and PAE/PAF offset values. The

IDT72V51236/72V51246/72V51256devices are capable ofupto4queues

andthereforecontain4setsofregistersforthesetupofeachqueue.

DuringaMasterResetiftheDFM(DefaultMode)inputisLOW,thenthedevice

willrequire serialprogrammingbythe user. Itis recommendedthatthe user

utilizea‘C’programprovidedbyIDT,thisprogramwillprompttheuserforall

informationregardingtheMulti-Queuesetup.Theprogramwillthengenerate

aserialbitstreamwhichshouldbeseriallyloadedintothedeviceviatheserial

port.FortheIDT72V51236/72V51246/72V51256devicestheserialprogram-

mingrequiresatotalnumberofseriallyloadedbitsperdevice,(SCLKcycles

withSENIenabled),calculatedby:19+(Qx72)whereQisthenumberofqueues

the user wishes to setup within the device. Please refer to the separate

ApplicationNote,AN-303forrecommendedcontroloftheserialprogramming

port.

SeeFigure6,SerialPortConnectionandFigure7,SerialProgrammingfor

connectionandtiminginformation.

DEFAULTPROGRAMMING

Duringa MasterResetifthe DFM(DefaultMode)inputis HIGHthe Multi-

Queuedevicewillbeconfiguredfordefaultprogramming,(serialprogramming

is not permitted). Default programming provides the user with a simpler,

howeverlimitedmeansbywhichtosetuptheMulti-QueueFIFOdevice,rather

thanusingtheserialprogrammingmethod.Thedefaultmodewillconfigurea

Multi-Queue device suchthatthe maximumnumberofqueues possible are

setup, with all of the parts available memory blocks being allocated equally

betweenthequeues.ThevaluesofthePAE/PAFoffsetsisdeterminedbythe

stateoftheDF(default)pinduringamasterreset.

FortheIDT72V51236/72V51246/72V51256devicesthedefaultmodewill

setup 4 queues, each queue being 4,096 x 36, 8,192 x 36 and 16,384 x 36

deep respectively. For both devices the value of the PAE/PAF offsets is

determinedatmasterresetbythestateoftheDFinput.IfDFisLOWthenboth

the PAE & PAF offset will be 8, if HIGH then the value is 128.

16

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

WhenconfiguringtheIDT72V51236/72V51246/72V51256devicesinde- theWRADDbusduringarisingedgeofWCLKprovidedthatWADENisHIGH.

faultmodetheusersimplyhastoapplyWCLKcyclesafteramasterreset,until AqueuetobewrittentoneedonlybeselectedonasinglerisingedgeofWCLK.

SENOgoesLOW,thissignalsthatdefaultprogrammingiscomplete.Theseclock Allsubsequentwriteswillbewrittentothatqueueuntilanewqueueisselected.

cyclesarerequiredforthedevicetoloaditsinternalsetupregisters. Whena Aminimumof2WCLKcyclesmustoccurbetweenqueueselectionsonthewrite

singleMulti-Queueisused,thecompletionofdeviceprogrammingissignaled port.OnthenextWCLKrisingedgethewriteportdiscretefullflagwillupdate

bytheSENOoutputofadevicegoingfromHIGHtoLOW.Note,thatSENImust toshowthefullstatusofthenewlyselectedqueue.Onthesecondrisingedge

beheldLOWwhenadeviceis setupfordefaultprogrammingmode.

ofWCLK,datapresentonthedatainputbus,Dincanbewrittenintothenewly

WhenMulti-Queuedevicesareconnectedinexpansionmode,theSENIof selectedFIFOqueueprovidedthatWENisLOWandthenewqueueisnotfull.

thefirstdeviceinachaincanbeheldLOW.TheSENOofadeviceshouldconnect Thecycleofthequeueselectionandthenextcyclewillcontinuetowritedata

totheSENIofthenextdeviceinthechain.TheSENOofthefinaldeviceisused presentonthedatainputbus,DinintothepreviousqueueprovidedthatWEN

toindicatethatdefaultprogrammingofalldevicesiscomplete.Whenthefinal isactiveLOW.

SENO goes LOW normal operations may begin. Again, all devices will be

IfWENisHIGH,inactiveforthese2clockcycles,thendatawillnotbewritten

programmedwiththeirmaximumnumberofqueuesandthememorydivided in to the previous queue.

equally between them. Please refer to Figure 8, DefaultProgramming.

Ifthenewlyselectedqueueisfullatthepointofitsselection,thenwritestothat

queue willbe prevented, a fullqueue cannotbe writteninto.

WRITE QUEUE SELECTION & WRITE OPERATION

Inthe4queueMulti-QueuedevicetheWRADDaddressbusis5bitswide.

TheIDT72V51236/72V51246/72V51256Multi-QueueFIFOdeviceshave Theleastsignificant2bitsareusedtoaddressoneofthe4availablequeues

upto4FIFOqueuesthatdatacanbewrittenintoviaacommonwriteportusing withinasingleMulti-Queuedevice.Themostsignificant3bitsareusedwhen

the data inputs, Din, write clock, WCLK and write enable, WEN. The queue adeviceis connectedinexpansionmode,upto8devices canbeconnected

address present on the write address bus, WRADD during a rising edge on inexpansion,eachdevicehavingits own3bitaddress.Theselecteddevice

WCLKwhilewriteaddressenable,WADENisHIGH,isthequeueselectedfor istheoneforwhichtheaddressmatchesa3bitIDcode,whichisstaticallysetup

writeoperations.ThestateofWENisdon’tcareduringthewritequeueselection on the ID pins, ID0, ID1, and ID2 of each individual device.

cycle.ThequeueselectiononlyhastobemadeonasingleWCLKcycle,this

Note,theWRADDbusisalsousedinconjunctionwithFSTR(almostfullflag

will remain the selected queue until another queue is selected, the selected busstrobe),toaddressthealmostfullflagbusofarespectivedeviceduringdirect

queueisalwaysthelastqueueselected.

modeofoperation.

Thewriteportisdesignedsuchthat100%busutilizationcanbeobtained.

RefertoTable1,forWriteAddressbusarrangement.Also,refertoFigure

ThismeansthatdatacanbewrittenintothedeviceoneveryWCLKrisingedge 9, Write Queue Select, Write Operation and Full flag Operation and Figure

includingthecyclethatanewqueueisbeingaddressed.Whenanewqueue 11,FullFlagTimingExpansionMode fortimingdiagrams.

isselectedforwriteoperationstheaddressforthatqueuemustbepresenton

TABLE 1 WRITE ADDRESS BUS, WRADD[4:0]

Operation WCLK WADEN FSTR

WRADD[4:0]

4 3 2

Device Select

(Compared to

ID0,1,2)

1 0

Write Queue Address

(2 bits = 4 Queues)

Write Queue

1

0

Select

4 3 2

1 0

PAFn Flag Bus

Device Select

0

1

Device Select

(Compared to

ID0,1,2)

X

5937 drw05

17

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

READ QUEUE SELECTION & READ OPERATION

thenextwordfromthenewqueue,boththesewordswillfallthroughtotheoutput

TheMulti-QueueFIFOdevicehasupto4FIFOqueuesthatdataisreadfrom registerconsecutivelyuponselectionofthenewqueue.Thispipeliningeffect

viaacommonreadportusingthedataoutputs,Qout,readclock,RCLKand providestheuserwith100%busutilization,butbringsaboutthepossibilitythat

readenable,REN.Anoutputenable,OEcontrolpinisalsoprovidedtoallow a “NULL” queue may be required within a Multi-Queue device. Null queue

High-ImpedanceselectionoftheQoutdataoutputs.TheMulti-Queuedevice operationisdiscussedinthenextsectionon.

readportoperatesinamodesimilarto“FirstWordFallThrough”onatraditional

IfanemptyqueueisselectedforreadoperationsontherisingedgeofRCLK,

IDT FIFO, but with the added feature of data output pipelining. This data onthesameRCLKedgeandthefollowingRCLKedge,2finalreadswillbemade

pipeliningontheoutputportallows theusertoachieve100%bus utilization, fromthepreviousqueue,providedthatRENisactive,LOW.OnthenextRCLK

which is the ability to read out a data word on every rising edge of RCLK rising edge a read from the new queue will not occur, because the queue is

regardless of whether a new queue is being selected for read operations.

empty.Thelastwordinthedataoutputregister(fromthepreviousqueue),will

Thequeueaddresspresentonthereadaddressbus,RDADDduringarising remainthere,buttheoutputvalidflag,OVwillgoHIGH,toindicatethatthedata

edge on RCLK while read address enable, RADEN is HIGH, is the queue present is no longer valid.

selectedforreadoperations.Aqueuetobereadfromneedonlybeselected

TheRDADDbusisalsousedinconjunctionwithESTR(almostemptyflag

on a single rising edge of RCLK. All subsequent reads will be read from that busstrobe),toaddressthealmostemptyflagbusofarespectivedeviceduring

queueuntilanewqueueisselected.Aminimumof2RCLKcyclesmustoccur direct mode of operation. In the 4 queue Multi-Queue device the RDADD

betweenqueueselectionsonthereadport.Datafromthenewlyselectedqueue addressbusis6bitswide.Theleastsignificant2bitsareusedtoaddressone

willbepresentontheQoutoutputsafter2RCLKcyclesplusanaccesstime, of the 4 available queues within a single Multi-Queue device. The 3rd least

providedthatOEisactive,LOW.OnthesameRCLKrisingedgethatthenew significantbitisusedtoselecta"Null"Queue.DuringaNull-Qselectionthe2

queueis selected,datacanstillbereadfromthepreviouslyselectedqueue, LSB'saredon'tcare.TheNull-Qisseenasanemptyqueueonthereadport.

providedthatRENisLOW,activeandthepreviousqueueisnotemptyonthe Null-Qoperationis discussedinmore detailina separate section. The most

followingrisingedgeofRCLKawordwillbereadfromthepreviouslyselected significant3bitsareusedwhenadeviceisconnectedinexpansionmode,up

queueregardlessofRENduetothefallthroughoperation,(providedthequeue to8devicescanbeconnectedinexpansion,eachdevicehavingitsown3bit

isnotempty). RememberthatOEallowstheusertoplacetheQout,dataoutput address.Theselecteddeviceistheoneforwhichtheaddressmatchesa3bit

bus into High-Impedance and the data can be read onto the output register ID code, which is statically setup on the ID pins, ID0, ID1, and ID2 of each

regardlessofOE.

individualdevice.

Whena queue is selectedonthe readport, the nextwordavailable inthat

RefertoTable2,forReadAddressbusarrangement.Also,refertoFigures

queue (provided that the queue is not empty), will fall through to the output 12,14&15forreadqueueselectionandreadportoperationtimingdiagrams.

registerafter2RCLKcycles.Asmentioned,intheprevious2RCLKcyclesto Note,thealmostemptyflagbusbecomesthe“PacketReady”flagbuswhen

thenewdatabeingavailable,datacanstillbereadfromthepreviousqueue, thedeviceisconfiguredforpacketreadymode,thisisdiscussedinaseparate

providedthatthequeueisnotempty.Atthepointofqueueselection,the2-stage sectionofthedatasheet.

internaldatapipelineisloadedwiththelastwordfromthepreviousqueueand

TABLE 2 READ ADDRESS BUS, RDADD[5:0]

Operation RCLK RADEN ESTR

RDADD[5:0]

5 4 3

2

1 0

Read Queue

1

0

Device Select

(Compared to

ID0,1,2)

Null-Q

Read Queue Address

Select

Select Pin (2 bits = 4 Queues)

5 4 3

2

1 0

Flag Bus Device

Selection

0

1

Device Select

(Compared to

ID0,1,2)

X

5937 drw06

18

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

NULL QUEUE OPERATION (OF THE READ PORT)

BUS MATCHING OPERATION

Pipeliningofdatatotheoutputportenablesthedevicetoprovide100%bus

BusMatchingoperationbetweentheinputportandoutputportisavailable.

utilization,datacanbereadoutoftheMulti-QueueFIFOoneveryRCLKcycle DuringamasterresetoftheMulti-Queuethestateofthethreesetuppins,BM

regardlessofqueueswitchesorotheroperations.Thedevicearchitectureis (BusMatching),IW(InputWidth)andOW(OutputWidth)determinetheinputand

suchthatthepipelineisconstantlyfilledwiththenextwordsinaselectedqueue outputportbuswidthsaspertheselectionsshowninTable3,“BusMatching

tobereadout,againproviding100%busutilizationandhighspeedoperation. Set-up”.9bitbytes,18bitwordsand36bitlongwordscanbewrittenintoand

This type of architecture does assume that the user is constantly switching readformtheFIFOqueuesprovidedthatatleastoneoftheportsissetupfor

queuessuchthatduringaqueueswitch,thelastdatawordsrequiredfromthe x36operation.WhenwritingtoorreadingfromtheMulti-Queueinabusmatching

previous queueareforcedthroughthepipelinetotheoutput.

mode, the device orders data in a “Little Endian” format. See Figure 3, Bus

Toputitanotherway, ifa useris readingfroma queue andwishes tostop MatchingByteArrangementfordetails.

readingfromthatqueueanddonothing,thepipewillhavethenextwordinthat

TheFullflagandAlmostFullflagoperationis always basedonwrites and

queueavailableinthepipeline.Iftheusernowswitchestoanotherqueuethe readsofdatawidthsdeterminedbythewriteportwidth.Forexample,iftheinput

firstdataoutofthepipewillbethewordfromthepreviousqueue.Iftheuserhas portisx36andtheoutputportisx9,thenfourdatareadsfromafullqueuewill

nonewqueue toswitchto, the nextdata wordfromthe currentqueue willbe berequiredtocausethefullflagtogoHIGH(queuenotfull).Conversely,the

sittinginthepipeline,thiswordmayneedtobeforcedoutthroughthepipe.Note, OutputValidflagandAlmostEmptyflagoperationsarealwaysbasedonwrites

that if reads cease at the empty boundary of a queue, then the last word will andreadsofdatawidthsdeterminedbythereadport.Forexample,iftheinput

automaticallybeforcedthroughthepipelinetotheoutputs.

portis x18andthe outputportis x36, twowrite operations willbe requiredto

Iftheuserdoesnotwanttobringwordsfromaqueueintothepipelineafter causetheoutputvalidflagofanemptyqueuetogoLOW,outputvalid(queue

areadoperationwithinaspecificqueuehasended,thentoforcethelastrequired isnotempty).

wordoutofthepipe,auserhas2optionsopentothem,thatis, ameansbywhich

toforcedataoutofthepipeattheendofreadoperationswithoutfillingthepipeline port,thereforetheinputbuswidthtoallqueuesisequal(determinedbytheinput

withnewdata. portsize)andtheoutputbuswidthfromallqueuesisequal(determinedbythe

Note,thattheinputportservesallqueueswithinadevice,asdoestheoutput

Thefirstofthese2optionsisto“doublepump”datawhenwritingthedatainto outputportsize).

thegivenFIFOqueue.Thisessentiallymeansperforming2writesofthelast

TABLE 3 BUS-MATCHING SET-UP

wordofagivensectionofdatatobereadout.Thisprovidesameansbywhich

whenthereadportstopsreadingthepipelineisfilledwiththesamewordtwice

andsothelastwordisreadout.Ifaqueueswitchoccurs,thefirstwordoutwill

be the double written word from the previous queue and should be ignored.

Thisoptionassumesthattheuserisbothwritingandreadingdatawithknown

sizesofpackets(apacketismadeupofdatawords).Sothatthelastword(write)

within a packet can be written twice (double pumped). This option however

meansthattheusergivesupthe100%busutilizationfeatureoftheMulti-Queue

device, the double pump takes up the bus for a single RCLK cycle.

Thereforeasecondoptionisavailabletotheuser,thisisthe“NullQ”select,

thisoptionallowstheusertoforcethelastrequireddatawordsfromaqueue

throughthepipeline,whilstmaintaining100%busutilization.Thisprovidesa

meansbywhichtheusercanforcedataoutofthepipelinewhenreadoperations

from a queue have ceased and there are no new queues that need to be

switchedovertoandreadfrom.TheNull-Qisselectedviareadportaddress

space RDADD[2]. The RDADD[5:0] bus should be addressed with xxx1xx,

thisaddressistheNull-Q.

Thenullqueuecannowbe"switched"tobytheuserwhennofurtherreads

are requiredfroma previouslyselectedqueue. The queue switchtothe null

queuewillforcethedatainthepipelinetobeforcedthroughtotheoutputs.The

devicecannowremainwiththenullqueueselecteduntilafurtherqueuechange

is madetoaqueuecontainingdataavailableforreadoperations.

Note,Iftheuserswitchesthereadporttothenullqueue,thisqueueisseen

asandtreatedasanemptyqueue,thereforeafterswitchingtothenullqueue

thelastwordfromthepreviousqueuewillremainontheoutputregisterandthe

OV flagwillgoHIGH, data notvalid.

x36 DEVICE

BM

IW

OW Write Port Read Port

0

1

X

0

1

X

0

1

0

1

x36

x18

x9

x36

x18

x9

x36

FULL FLAG OPERATION

The Multi-Queue FIFOdevice provides a single FullFlagoutput, FF. The

FFflagoutputprovidesafullstatusoftheFIFOqueuecurrentlyselectedonthe

writeportforwriteoperations.InternallytheMulti-QueueFIFOmonitorsand

maintainsastatusofthefullconditionofallqueueswithinit,howeveronlythe

queuethatisselectedforwriteoperationshasitsfullstatusoutputtotheFFflag.

Thisdedicatedflagisoftenreferredtoasthe“activequeuefullflag”.

Whenqueueswitchesarebeingmadeonthewriteport,theFFflagoutput

willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,

onthecycleafteranewqueueselectionismade.Theuserthenhasafullstatus

forthenewqueueonecycleaheadoftheWCLKrisingedgethatdatacanbe

writtenintothenewqueue.Thatis,anewqueuecanbeselectedonthewrite

portviatheWRADDbus,WADENenableandarisingedgeofWCLK.Onthe

nextrisingedgeofWCLK,theFFflagoutputwillshowthefullstatusofthenewly

selected queue. On the second rising edge of WCLK following the queue

selection,datacanbewrittenintothenewlyselectedqueueprovidedthatdata

andenablesetup&holdtimesaremet.

Thenullqueueoperationisonlyapossiblerequirementonthereadportof

theMulti-Queue,ameansbywhichtoforcedatathroughtheoutputpipeline.

NullQselectionandoperationhasnomeaningoradvantageonthewriteport

of the device. A Null Q address should never be selected on the write port.

See Figure 16, ReadOperationandNullQueue SelectionandFigure 17,

NullQueueFlowDiagramforadetailedtimingdiagramsthatshowshownull

queueselectioncanbeimplemented.

Note,theFF flagwillprovidestatus ofanewlyselectedqueueoneWCLK

cycleafterqueueselection,whichisonecyclebeforedatacanbewrittentothat

queue. This prevents the user from writing data to a FIFO queue that is full,

(assumingthataqueueswitchhasbeenmadetoaqueuethatisactuallyfull).

19

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

TheFFflagissynchronoustotheWCLKandalltransitionsoftheFFflagoccur

TheOVflagissynchronoustotheRCLKandalltransitionsoftheOVflagoccur

basedonarisingedgeofWCLK.InternallytheMulti-Queuedevicemonitors basedonarisingedgeofRCLK.InternallytheMulti-Queuedevicemonitors

andkeepsarecordofthefullstatusforallqueues.Itispossiblethatthestatus andkeepsarecordoftheoutputvalid(empty)statusforallqueues.Itispossible

ofa FF flagmaybechanginginternallyeventhoughthatflagis nottheactive that the status of an OV flag may be changing internally even though that

queueflag(selectedonthewriteport).Aqueueselectedonthereadportmay respectiveflagisnottheactivequeueflag(selectedonthereadport).Aqueue

experienceachangeofitsinternalfullflagstatusbasedonreadoperations. selectedonthewriteportmayexperienceachangeofitsinternalOVflagstatus

SeeFigure9,WriteQueueSelect,WriteOperationandFullFlagOperation basedonwriteoperations,thatis,datamaybewrittenintothatqueuecausing

andFigure 11,FullFlagTiminginExpansionModefortiminginformation.

ittobecome“notempty”.

SeeFigure12,ReadQueueSelect,ReadOperationandFigure13,Output

ValidFlagTimingfordetailsofthetiming.

EXPANSION MODE - FULL FLAG OPERATION

WhenMulti-QueuedevicesareconnectedinExpansionmodetheFFflags

of all devices should be connected together, such that a system controller EXPANSION MODE – OUTPUT VALID FLAG OPERATION

monitoringandmanagingthe Multi-Queue devices write portonlylooks ata

WhenMulti-QueuedevicesareconnectedinExpansionmode,theOVflags

singleFFflag(asopposedtoadiscreteFFflagforeachdevice).This FFflag of all devices should be connected together, such that a system controller

isonlypertinenttotheFIFOqueuebeingselectedforwriteoperationsatthat monitoringandmanagingthe Multi-Queue devices readportonlylooks ata

time.Remember,thatwheninexpansionmodeonlyoneMulti-Queuedevice singleOVflag(asopposedtoadiscreteOVflagforeachdevice).ThisOVflag

canbewrittentoatanymomentintime,thustheFFflagprovidesstatusofthe isonlypertinenttotheFIFOqueuebeingselectedforreadoperationsatthat

active queue onthe write port.

time.Remember,thatwheninexpansionmodeonlyoneMulti-Queuedevice

ThisconnectionofflagoutputstocreateasingleflagrequiresthattheFFflag canbereadfromatanymomentintime,thustheOVflagprovidesstatusofthe

outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis active queue on the read port.

madeonlyasingledevicedrivestheFFflagbusandallotherFF flagoutputs

ThisconnectionofflagoutputstocreateasingleflagrequiresthattheOVflag

connectedtotheFFflagbusareplacedintoHigh-Impedance.Theuserdoes outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis

nothavetoselectthisHigh-Impedancestate,agivenMulti-QueueFIFOdevice madeonlyasingledevicedrivestheOVflagbusandallotherOVflagoutputs

willautomaticallyplaceitsFFflagoutputintoHigh-Impedancewhennoneofits connectedtotheOVflagbusareplacedintoHigh-Impedance.Theuserdoes

queuesareselectedforwriteoperations.

nothavetoselectthisHigh-Impedancestate,agivenMulti-QueueFIFOdevice

Whenqueueswithinasingledeviceareselectedforwriteoperations,theFF willautomaticallyplaceitsOVflagoutputintoHigh-Impedancewhennoneofits

flagoutputofthatdevicewillmaintaincontroloftheFFflagbus.ItsFFflagwill queues areselectedforreadoperations.

simplyupdatebetweenqueueswitchestoshowtherespectivequeuefullstatus.

Whenqueueswithinasingledeviceareselectedforreadoperations,theOV

TheMulti-QueuedeviceplacesitsFFflagoutputintoHigh-Impedancebased flagoutputofthatdevicewillmaintaincontroloftheOVflagbus.ItsOVflagwill

onthe3bitIDcodefoundinthe3mostsignificantbitsofthewritequeueaddress simplyupdatebetweenqueueswitchestoshowtherespectivequeueoutput

bus,WRADD.Ifthe3mostsignificantbitsofWRADDmatchthe3bitIDcodesetup validstatus.

onthestaticinputs,ID0,ID1andID2thentheFFflagoutputoftherespective

TheMulti-QueuedeviceplacesitsOVflagoutputintoHigh-Impedancebased

devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheFFflag onthe3bitIDcodefoundinthe3mostsignificantbitsofthereadqueueaddress

outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure bus,RDADD.Ifthe3mostsignificantbitsofRDADDmatchthe3bitIDcodesetup

11,FullFlagTiminginExpansionModefordetailsofflagoperation,including onthestaticinputs,ID0,ID1andID2thentheOVflagoutputoftherespective

when more than one device is connected in expansion.

devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheOVflag

outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure

13,OutputValidFlagTimingfordetailsofflagoperation,includingwhenmore

OUTPUTVALIDFLAGOPERATION

TheMulti-QueueFIFOdeviceprovidesasingleOutputValidflagoutput,OV. thanone device is connectedinexpansion.

TheOVprovidesanemptystatusordataoutputvalidstatusforthedataword

currentlyavailableontheoutputregisterofthereadport.Therisingedgeofan ALMOST FULL FLAG

RCLKcyclethatplacesnewdataontotheoutputregisterofthereadport,also

As previously mentioned the Multi-Queue FIFO device provides a single

updatestheOVflagtoshowwhetherornotthatnewdatawordisactuallyvalid. ProgrammableAlmostFullflagoutput,PAF.ThePAFflagoutputprovidesa

InternallytheMulti-QueueFIFOmonitorsandmaintainsastatusoftheempty statusofthealmostfullconditionfortheactivequeuecurrentlyselectedonthe

conditionofallqueueswithinit,howeveronlythequeuethatisselectedforread writeportforwriteoperations.InternallytheMulti-QueueFIFOmonitorsand

operationshasitsoutputvalid(empty)statusoutputtotheOVflag,givingavalid maintainsastatusofthealmostfullconditionofallqueueswithinit,howeveronly

statusforthewordbeingreadatthattime.

Thenatureofthefirstwordfallthroughoperationmeansthatwhenthelast flag.Thisdedicatedflagisoftenreferredtoasthe“activequeuealmostfullflag”.

thequeuethatisselectedforwriteoperationshasitsfullstatusoutputtothePAF

datawordisreadfromaselectedqueue,theOVflagwillgoHIGHonthenext ThepositionofthePAFflagboundarywithinaFIFOqueuecanbeatanypoint

enabled read, that is, on the next rising edge of RCLK while REN is LOW.

withinthatqueuesdepth.Thislocationcanbeuserprogrammedviatheserial

Whenqueueswitchesarebeingmadeonthereadport,theOVflagwillswitch port or one of the default values (8 or 128) can be selected if the user has

toshowstatusofthenewqueueinlinewiththedataoutputfromthenewqueue. performeddefaultprogramming.

Whenaqueueselectionismadethefirstdatafromthatqueuewillappearon

Asmentioned,everyqueuewithinaMulti-Queuedevicehasitsownalmost

theQoutdataoutputs2RCLKcycleslater,theOVwillchangestatetoindicate fullstatus,whenaqueueisselectedonthewriteport,thisstatusisoutputviathe

validityofthedatafromthenewlyselectedqueueonthis2^ndRCLKcyclealso. PAF flag. The PAF flag value for each queue is programmed during Multi-

Thepreviouscycleswillcontinuetooutputdatafromthepreviousqueueand Queuedeviceprogramming(alongwiththenumberofqueues,queuedepths

theOVflagwillindicatethestatusofthoseoutputs.Again,theOVflagalways andalmostemptyvalues).ThePAFoffsetvalue,m,forarespectivequeuecan

indicatesstatusforthedatacurrentlypresentontheoutputregister.

be programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total

20

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

memorydepthforthatqueue.ThePAFvalueofdifferentqueueswithinthesame viatheserialportoroneofthedefaultvalues(8or128)canbeselectedifthe

devicecanbedifferentvalues.

userhasperformeddefaultprogramming.

Whenqueueswitchesarebeingmadeonthewriteport,thePAFflagoutput

Asmentioned,everyqueuewithinaMulti-Queuedevicehasitsownalmost

willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus, emptystatus,whenaqueueisselectedonthereadport,thisstatusisoutputvia

onthesecondcycleafteranewqueueselectionismade,onthesameWCLK thePAEflag.ThePAEflagvalueforeachqueueisprogrammedduringMulti-

cyclethatdatacanactuallybewrittentothenewqueue.Thatis,anewqueue Queuedeviceprogramming(alongwiththenumberofqueues,queuedepths

canbeselectedonthewriteportviatheWRADDbus,WADENenableanda andalmostfullvalues).ThePAEoffsetvalue,n,forarespectivequeuecanbe

risingedgeofWCLK.OnthesecondrisingedgeofWCLKfollowingaqueue programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory

selection,thePAFflagoutputwillshowthefullstatusofthenewlyselectedqueue. depthforthatqueue.ThePAEvalueofdifferentqueueswithinthesamedevice

The PAFis flagoutputis doubleregisterbuffered,sowhenawriteoperation canbedifferentvalues.

occursatthealmostfullboundarycausingtheselectedqueuestatustogoalmost

fullthePAFwillgoLOW2WCLKcyclesafterthewrite.Thesameistruewhen willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,

a read occurs, there will be a 2 WCLK cycle delay after the read operation. onthesecondcycleafteranewqueueselectionismade,onthesameRCLK

Whenqueueswitchesarebeingmadeonthereadport,thePAEflagoutput

So the PAF flag delays are:

cyclethatdataactuallyfallsthroughtotheoutputregisterfromthenewqueue.

That is, a new queue can be selected on the read port via the RDADD bus,

froma write operationto PAF flagLOWis 2WCLK+tWAF

ThedelayfromareadoperationtoPAFflagHIGHistSKEW2+WCLK+tWAF RADENenableandarisingedgeofRCLK.OnthesecondrisingedgeofRCLK

Note, if tSKEW is violated there will be one added WCLK cycle delay.

followingaqueueselection,thedatawordfromthenewqueuewillbeavailable

ThePAFflagissynchronoustotheWCLKandalltransitionsofthePAFflag attheoutputregisterandthePAEflagoutputwillshowtheemptystatusofthe

occur based on a rising edge of WCLK. Internally the Multi-Queue device newlyselectedqueue.ThePAEis flagoutputis doubleregisterbuffered,so

monitorsandkeepsarecordofthealmostfullstatusforallqueues.Itispossible when a read operation occurs at the almost empty boundary causing the

thatthestatusofaPAFflagmaybechanginginternallyeventhoughthatflagis selectedqueuestatustogoalmostemptythePAEwillgoLOW2RCLKcycles

nottheactivequeueflag(selectedonthewriteport).Aqueueselectedonthe after the read. The same is true when a write occurs, there will be a 2 RCLK

readportmayexperienceachangeofitsinternalalmostfullflagstatusbased cycledelayafterthewriteoperation.

onreadoperations.TheMulti-QueueFIFOdevicealsoprovides aduplicate

ofthePAFflagonthePAF[3:0]flagbus,thiswillbediscussedindetailinalater

sectionofthedatasheet.

So the PAE flag delays are:

from a read operation toPAE flag LOW is 2 RCLK + tRAE

ThedelayfromawriteoperationtoPAEflagHIGHistSKEW2+RCLK+tRAE

Note, if tSKEW is violated there will be one added RCLK cycle delay.

ThePAEflagissynchronoustotheRCLKandalltransitionsofthePAEflag

occur based on a rising edge of RCLK. Internally the Multi-Queue device

SeeFigures 18and19forAlmostFullflagtimingandqueueswitching.

ALMOSTEMPTYFLAG

As previously mentioned the Multi-Queue FIFO device provides a single monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible

ProgrammableAlmostEmptyflagoutput,PAE.ThePAEflagoutputprovides thatthestatusofaPAEflagmaybechanginginternallyeventhoughthatflagis

astatusofthealmostemptyconditionfortheactivequeuecurrentlyselectedon nottheactivequeueflag(selectedonthereadport).Aqueueselectedonthe

thereadportforreadoperations.InternallytheMulti-QueueFIFOmonitorsand writeportmayexperienceachangeofitsinternalalmostemptyflagstatusbased

maintainsastatusofthealmostemptyconditionofallqueueswithinit,however onwriteoperations.TheMulti-QueueFIFOdevicealsoprovidesaduplicate

onlythequeuethatisselectedforreadoperationshasitsemptystatusoutput ofthePAEflagonthePAE[3:0]flagbus,thiswillbediscussedindetailinalater

tothePAEflag.Thisdedicatedflagisoftenreferredtoasthe“activequeuealmost sectionofthedatasheet.

emptyflag”. The positionofthe PAEflagboundarywithina FIFOqueue can

beatanypointwithinthatqueuesdepth.Thislocationcanbeuserprogrammed

SeeFigures20and21forAlmostEmptyflagtimingandqueueswitching.

21

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

TABLE 4 FLAG OPERATION BOUNDARIES & TIMING

Full Flag, FF Boundary

Output Valid, OV Flag Boundary

I/O Set-Up

In36 to out36

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

FF Boundary Condition

I/O Set-Up

OV Boundary Condition

OV Goes LOW after 1^stWrite

(seenote1belowfortiming)

FF Goes LOW after D+1 Writes

(seenotebelowfortiming)

In36 to out36 (Almost Empty Mode)

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

In36 to out36

(Writeportonlyselectedforqueue

when the 1^stWord is written in)

FF Goes LOW after D Writes

(seenotebelowfortiming)

In36toout36(PacketReadyMode)

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

OV Goes LOW after 1^stWrite

(seenote2belowfortiming)

In36 to out18

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

FF Goes LOW after D Writes

(seenotebelowfortiming)

In36 to out18

OV Goes LOW after 1^stWrite

(seenote1belowfortiming)

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

In36 to out18

FF Goes LOW after D Writes

In36 to out9

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

OV Goes LOW after 1^stWrite

(Writeportonlyselectedforqueue

(seenotebelowfortiming)

(seenote1belowfortiming)

when the 1^stWord is written in)

In36 to out9

FF Goes LOW after D Writes

(seenotebelowfortiming)

In18 to out36

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

OV Goes LOW after 1^stWrite

(seenote1belowfortiming)

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

In36 to out9

FF Goes LOW after D Writes

(seenotebelowfortiming)

In9 to out36

OV Goes LOW after 1^stWrite

(seenote1belowfortiming)

(Writeportonlyselectedforqueue

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

In18 to out36

FF Goes LOW after ([D+1] x 2) Writes

(seenotebelowfortiming)

NOTE:

1. OV Timing

Assertion:

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

In18 to out36

(Writeportonlyselectedforqueue

when the 1^stWord is written in)

FF Goes LOW after (D x 2) Writes

Write to OV LOW: tSKEW1 + RCLK + tROV

If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tROV

De-assertion:

(seenotebelowfortiming)

Read Operation to OV HIGH: tROV

In9 to out36

(Bothportsselectedforsamequeue

when the 1^stWord is written in)

FF Goes LOW after ([D+1] x 4) Writes

(seenotebelowfortiming)

2. OV Timing when in Packet Ready Mode (36 in to 36 out only)

Assertion:

Write to OV LOW: tSKEW4 + RCLK + tROV

If tSKEW4 is violated there may be 1 added clock: tSKEW4 + 2 RCLK + tROV

De-assertion:

In9 to out36

(Writeportonlyselectedforqueue

when the 1^stWord is written in)

FF Goes LOW after (D x 4) Writes

(seenotebelowfortiming)

Read Operation to OV HIGH: tROV

NOTE:

D = FIFO Queue Depth

FF Timing

Assertion:

Write Operation to FF LOW: tWFF

De-assertion:

Read to FF HIGH: tSKEW1 + tWFF

If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF

Programmable Almost Full Flag, PAF & PAFn Bus Boundary

I/O Set-Up

PAF & PAFn Boundary

in36 to out36

PAF/PAFn Goes LOW after

(Bothportsselectedforsamequeuewhenthe1^stD+1-mWrites

Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)

in36 to out36

PAF/PAFn Goes LOW after

NOTE:

D = FIFO Queue Depth

m = Almost Full Offset value.

(Writeportonlyselectedforsamequeuewhenthe D-mWrites

1^stWordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)

Default values: if DF is LOW at Master Reset then m = 8

if DF is HIGH at Master Reset then m= 128

PAF Timing

in36 to out18

in36 to out9

in18 to out36

PAF/PAFn Goes LOW after

D-mWrites(seebelowfortiming)

PAF/PAFn Goes LOW after

D-mWrites(seebelowfortiming)

Assertion:

Write Operation to PAF LOW: 2 WCLK + tWAF

De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF

If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF

PAFn Timing

PAF/PAFn Goes LOW after

([D+1-m] x 2) Writes

(seenotebelowfortiming)

Assertion:

Write Operation to PAFn LOW: 2 WCLK* + tPAF

De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF

If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF

* If a queue switch is occurring on the write port at the point of flag assertion there may

be one additional WCLK clock cycle delay.

in9 to out36

PAF/PAFn Goes LOW after

([D+1-m] x 4) Writes

(seenotebelowfortiming)

22

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

TABLE 4 FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)

Programmable Almost Empty Flag Bus, PAEn Boundary

I/O Set-Up PAEn Boundary Condition

PAEn Goes HIGH after

(Bothportsselectedforsamequeuewhenthe1^stn+2Writes

Programmable Almost Empty Flag, PAE Boundary

I/O Set-Up PAE Assertion

PAE Goes HIGH after n+2

(Bothportsselectedforsamequeuewhenthe1^stWrites

in36 to out36

Wordiswritteninuntiltheboundaryisreached)

(seenotebelowfortiming)

Wordiswritteninuntiltheboundaryisreached)

(seenotebelowfortiming)

in36 to out36

PAEn Goes HIGH after

in36 to out18

PAE Goes HIGH after n+1

(Writeportonlyselectedforsamequeuewhenthe n+1Writes

(Bothportsselectedforsamequeuewhenthe1^stWrites

1^stWordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)

Wordiswritteninuntiltheboundaryisreached)

(seenotebelowfortiming)

in36 to out18

in36 to out9

in18 to out36

PAEn Goes HIGH after n+1

in36 to out9

PAE Goes HIGH after n+1

Writes (seebelowfortiming)

(Bothportsselectedforsamequeuewhenthe1^stWrites

PAEn Goes HIGH after n+1

Writes(seebelowfortiming)

Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)

in18 to out36

PAE Goes HIGH after

PAEn Goes HIGH after

(Bothportsselectedforsamequeuewhenthe1^st([n+2] x 2) Writes

Wordiswritteninuntiltheboundaryisreached)

(seenotebelowfortiming)

PAE Goes HIGH after

Wordiswritteninuntiltheboundaryisreached)

(seenotebelowfortiming)

in9 to out36

in18 to out36

PAEn Goes HIGH after

(Bothportsselectedforsamequeuewhenthe1^st([n+2] x 4) Writes

(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 2) Writes

1^stWordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)

Wordiswritteninuntiltheboundaryisreached)

(seenotebelowfortiming)

in9 to out36

PAEn Goes HIGH after

NOTE:

(Bothportsselectedforsamequeuewhenthe1^st([n+2] x 4) Writes

n = Almost Empty Offset value.

Default values: if DF is LOW at Master Reset then n = 8

if DF is HIGH at Master Reset then n = 128

PAE Timing

Assertion:

Wordiswritteninuntiltheboundaryisreached)

(seenotebelowfortiming)

PAEn Goes HIGH after

in9 to out36

(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 4) Writes

Read Operation to PAE LOW: 2 RCLK + tRAE

1^stWordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)

De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE

If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE

NOTE:

n = Almost Empty Offset value.

Default values: if DF is LOW at Master Reset then n = 8

if DF is HIGH at Master Reset then n = 128

PAEn Timing

Assertion:

Read Operation to PAEn LOW: 2 RCLK* + tPAE

De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE

If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE

* If a queue switch is occurring on the read port at the point of flag assertion there may

be one additional RCLK clock cycle delay.

PACKET READY FLAG BUS, PRn BOUNDARY

Assertion:

PACKETREADYFLAG,PRBOUNDARY

Assertion:

Both the rising and falling edges of PRn are synchronous to RCLK.

PRn Falling Edge occurs upon writing the first TEOP marker, on input D35,

(assumingaTSOPmarker,oninputD34has previouslybeenwritten).i.e.a

completepacketisavailablewithinaqueue.

Both the rising and falling edges ofPR are synchronous to RCLK.

PR Falling Edge occurs upon writing the first TEOP marker, on input D35,

(assumingaTSOPmarker,oninputD34has previouslybeenwritten).i.e.a

completepacketisavailablewithinaqueue.

Timing:

FromWCLKrisingedgewritingtheTEOPwordPRgoes LOWafter:tSKEW4

+ 2 RCLK* + tPAE

FromWCLKrisingedgewritingtheTEOPwordPRgoes LOWafter:tSKEW4

+ 2 RCLK + tPR

If tSKEW4 is violated PRn goes LOW after tSKEW4 + 3 RCLK* + tPAE

*Ifaqueueswitchisoccurringonthereadportatthepointofflagassertionthere

may be one additional RCLK clock cycle delay.

De-assertion:

IftSKEW4isviolated:

PR goes LOW after tSKEW4 + 3 RCLK + tPR

(Please refer to Figure 26, Data Input (Transmit) Packet Ready Mode of

Operationfortimingdiagram).

PRRisingEdgeoccursuponreadingthelastRSOPmarker,fromoutputQ34.

i.e.therearenomorecompletepacketsavailablewithinthequeue.

Timing:

FromRCLKrisingedge Readingthe RSOPwordthePR goes HIGHafter:2

RCLK* + tPAE

De-assertion:

PRRisingEdgeoccursuponreadingthelastRSOPmarker,fromoutputQ34.

i.e.therearenomorecompletepacketsavailablewithinthequeue.

Timing:

From RCLK rising edge Reading the RSOP word the PR goes HIGH after:

2 RCLK + tPR

*Ifaqueueswitchisoccurringonthereadportatthepointofflagassertionthere

may be one additional RCLK clock cycle delay.

(Please refer to Figure 27, Data Output (Receive) Packet Ready Mode of

Operationfortimingdiagram).

23

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PACKETREADYFLAG

TSOPmarkerfollowed(atsomelatertime),byaTEOPmarkerhasbeenwritten.

The Multi-Queue FIFO provides the user with a Packet Ready feature. ThePRflagwillgoactiveLOWtoindicatethatacompletepacketisavailable

DuringaMasterResetthestateofthePKTinput(packetreadymodeselect), withinthequeue.OncetheRSOPmarkerisreadout,thePRflagwillgoHIGH,

determineswhetherthedevicewilloperateinpacketreadymode.Adiscrete indicatingthatacompletepacketisnolongerpresent,(assumingthatthereare

flagoutputPR,providesapacketreadystatusoftheactivequeue,selectedon no more packets in the queue). The user may proceed with the reading

thereadport.Apacketreadystatusismaintainedforallqueues,howeveronly operationuntilthecurrentpackethasbeenreadoutandnofurthercomplete

thequeueselectedonthereadporthasitspacketreadystatusoutputtotheactive packets are available. Ifduringthattime anothercomplete packethas been

PR flag. The PR output flag for the active queue on the read port, is LOW writtenintothequeueandthePRflaghasagaingoneactive,thenreadsfrom

whenevertheactivequeuehasoneormorefullpacketsofdatawithinitsqueue, thenewpacketmayfollowafterthecurrentpackethasbeencompletelyread

availableforreading.IflessthanafullpacketisavailablethenthePRflagwill out.

beHIGH,packetnotready. InPacketmode,wordscannotbereadfromaqueue

Thepacketcountersthereforelookforstartofpacketmarkersfollowedbyend

untilacompletepackethasbeenwrittenintothatqueue,regardlessofREN. ofpacketmarkers andregarddatainbetweentheTSOPandTEOPas afull

WhenpacketreadymodeisselectedtheProgrammableAlmostEmptybus, packetofdata.Thepacketmonitoringhasnolimitationastohowmanypackets

PAEn, actually becomes the Packet Ready bus, PRn. The PRn bus now arewrittenintoaFIFOqueue,theonlyconstraintofcoursebeingthedepthof

providing packet ready status for all queues including those not currently thequeue.Note,thatthereisaminimumallowablepacketsizeoffourwrites,that

selected on the read port. Both Polled and Direct modes of operation are is within a TSOP marker and TEOP marker there must be two other write

availableandselectableduringaMasterReset.

operations.

WhentheMulti-Queueisselectedforpacketreadymodethedevicemustalso

The packet logic does expect a TSOP marker to be followed by a TEOP

beconfiguredwitha36bitwriteportand36bitreadport.Thetwomostsignificant marker.

bits ofthe36bitdatabus cannowbeusedas “packetmarkers”.Onthewrite

IfasecondTSOPmarkerisreadafterafirst,thenitisignoredandthelogic

port these are bits D34, D35 and on the read port Q34, Q35. All four bits are regardsdatabetweenthefirstTSOPandthefirstsubsequentTEOPasthefull

monitoredbythepacketcontrollogicasdataiswrittenintoandreadoutfrom packet.ThesameistrueforTEOP,asecondconsecutiveTEOPmarkisignored.

the FIFO queues. The packet ready status for individual queues is then Onthewritesidethe2ndconsecutiveTSOPandTEOPisignored.Ontheread

determinedbythepacketreadylogic.

sidetheusershouldregardapacketasbeingbetweenthefirstRSOPandthe

OnthewriteportD34isusedto“mark”thewordcurrentlybeingwritteninto firstsubsequentREOP.

theselectedFIFOqueueasa“TransmitStartofPacket”,TSOP.Whentheuser

Theusermayalsowishtoimplementtheuseofan“AlmostEndofPacket”

requiresawordbeingwrittenintobemarkedasthestartofapacket,theTSOP marker,AEOP.Forexample,theAEOPcanbesetoninputD33,andthiswill

inputmustbeHIGHforthesameWCLKrisingedgeasthewordthatiswritten passstraightthroughtheFIFOqueue,remainingattachedasa“tag”tothe36

in. This markeris effectivelya “tag”onthe endofthe wordtobe markedas it bitlongworditwaswrittenwith,beingreadoutonQ33.ThepurposeofthisAEOP

isbeingwrittenintoitsrespectivequeue.ThisTSOPmarkerwillremainstored markeristoprovidetheentityreadingdatafromtheMulti-Queuedevicethatthe

intheFIFOqueuealongwiththedataitwaswritteninwithuntilthewordinturn endofpacketisafixed(known)numberofreadsawayfromtheendofpacket.

isreadoutofthequeueviathereadport.ThismarkerwillbereadoutonQ34 Thisisausefulfeaturewhenduetolatencieswithinthesystem,monitoringthe

andis nowdenotedwiththename,“ReceiveStartofPacket”,RSOP.

REOPmarkeralonedoesnotprevent“overreading”ofthedatafromthequeue

ThesecondmarkerthatisusedonthewriteportisD35andisusedto“mark” selected.Forexample,anAEOPmarkerset4writesbeforetheTEOPmarker

thewordcurrentlybeingwrittenintotheselectedFIFOqueueasa“Transmit providesthedeviceconnectedtothereadportwithand“almostendofpacket”

EndofPacket”, TEOP. Whenthe userrequires a wordbeingwrittenintobe indication4cyclesbeforetheendofpacket.

markedastheendofapacket,theTEOPinputmustbeHIGHforthesameWCLK

risingedgeasthewordthatiswrittenin.Thismarkeriseffectivelya“tag”onthe determinedbytheuserrequirementsorlatenciesinvolvedinthesystem.

endofthewordtobemarkedasitisbeingwrittenintoitsrespectivequeue.This IdeallyaswitchshouldbeperformedonecyclebeforetheTEOPisreadout.

The AEOP can be set any number of words before the end of packet

TEOPmarkerwillremainstoredintheFIFOqueuealongwiththedataitwas Soonthenextcyclethelastwordofapacket(TEOP)isread,andonthefollowing

writteninwithuntilthe wordinturnis readoutofthe queue via the readport. cyclethenextwordofthenewqueueisreadout.Onceapacketisbeingread

ThismarkerwillbereadoutonQ35andisnowdenotedwiththename,“Receive outitmustbereadtocompletion.Thatis,theusercannotswitchtoanewqueue

EndofPacket”,REOP.

inthemiddleofapacketbeingreadout.Forexample,whentheRSOPmarker

Thepacketreadylogicmonitorsallstartandendofpacketmarkersbothas isreadoutofaqueue,markingthestartofPacket,thatpacketmustbereadto

theyenterrespectivequeuesviathewriteportandastheyexitqueuesviathe completion,untilitsassociatedREOP,(EndofPacketMarker)hasbeenread

readport.Thelogicbothincrementsanddecrementsapacketcounter,which out,againthequeueswitchtakingplaceonecyclebeforethe"EndofPacket"

isprovidedforeachqueue.Thisfunctionalityofthepacketreadylogicmeans is readout.

that status is provided as to whether or not at least one full packet of data is

SeeFigure26,DataInput(Transmit)PacketReadyModeofOperationand

availablewithinarespectivequeue.Forexample,ifaTSOPhasbeenreceived Figure 27, Data Output (Receive) Packet Ready Mode of Operation.

andsometimelateraTEOPis receivedafullpacketofdatais deemedtobe

available,andthePRflagwillgoactiveLOW.Consequentlyifreadsbeginfrom PACKETREADY–MODULOOPERATION

thatqueueandtheRSOPisdetectedontheoutputportasdataisbeingread

WhenutilizingtheMulti-QueueFIFOdeviceinPacketReadymode,theuser

out,thenthereisnolongerdeemedtobeafullpacketofdataavailableandPR mayalsowanttoconsidertheimplementationof“Modulo”operationor“valid

will go inactive HIGH provided, that no other full packets are available. bytemarking”.Thismaybearequirementwhenthepacketsbeingtransferred

Essentially,apartialpacketinaqueueisregardedasapacketnotbeingready through a FIFO queue are in a byte arrangement even though the data bus

andPRwillbeHIGH.InPacketmode,wordscannotbereadfromaqueueuntil widthis36bits.Heretheusermayactuallybeconcatenatingbytestoforma36

acompletepackethasbeenwrittenintothatqueue,regardlessofREN.InPacket bitdatabusthroughtheMulti-Queuedevice.Inthissituationonlyalimitednumber

modetheMulti-Queuedevicewillpreventreadsfromaselectedqueueuntila ofbytes mayactuallybepartofthepacket.This willonlyoccurwhenthefirst

24

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

TABLE 5 PACKET MODE VALID BYTE

BYTE D

BYTE C

BYTE B

BYTE A

TMOD1 (D33)

RMOD1 (Q33)

TMOD2 (D32)

RMOD2 (Q32)

VALID BYTES

0

1

0

1

0

1

A, B, C, D

A

A, B

A, B, C

5937 drw07

NOTE:

Packet Mode is only available when the Input Port and Output Port are 36 bits wide.

36bitlongwordofapacketiswritteninandthelast36bitlongwordofpacket

Alternatively,the4bitPAFnflagbusofeachdevicecanbeconnectedtogether

iswrittenin.Themodulooperationisameansbywhichtheusercanmarkand toformasingle4bitbus,i.e.PAF[0]ofdevice1willconnecttoPAF[0]ofdevice

identifywhichbytes ofa 36bitlongwordare partofthe packet. 2etc. Whenconnectingdevices inthis mannerthe PAFncanonlybe driven

Onthewriteportdatainputbits,D32(transmitmodulobit2,TMOD2)andD33 byasingledeviceatanytime,(thePAFnoutputsofallotherdevicesmustbe

(transmitmodulobit1,TMOD1)canbeusedtocodewhichbytesofawordare inhighimpedancestate).Therearetwomethodsbywhichtheusercanselect

partofthepacketthatisalsobeingmarkedasthe“StartofPacket”or“Endof whichdevicehas controlofthebus,theseare“Direct”(Addressed)modeor

Packet”.Converselyonthereadportwhenreadingoutthesemarkedwords, “Polled”(Looped)mode,determinedbythestateoftheFM(flagMode)input

dataoutputsQ32(receivemodulobit2,RMOD2)andQ33(receivemodulobit duringaMasterReset.

1,RMOD1)willpassonthebytevalidityinformationforthatlongword.Refer

toTable5foranexampleofhowthemodulobitsmaybesetupandused.See PAFn BUS EXPANSION - DIRECT MODE

Figure26,DataInput(Transmit)PacketReadyModeofOperationandFigure

27, Data Output (Receive) Packet Ready Mode of Operation.

If FM is LOW at Master Reset then the PAFn bus operates in Direct

(addressed)mode.Indirectmodetheusercanaddressthedevicetheyrequire

The internal packet ready control logic performs no operation on these tocontrolthePAFnbus.Theaddresspresentonthe3mostsignificantbitsof

Modulobits,theyarepurelyinformationalbitsthatarepassedthroughaqueue the WRADD[4:0] address bus with FSTR (PAF flag strobe), HIGH will be

withtherespectivedatabytes.

selectedasthedeviceonarisingedgeofWCLK.Sotoaddressthefirstdevice

inabankofdevicestheWRADD[4:0]addressshouldbe“000xx”thesecond

device“001xx”andsoon.The3mostsignificantbitsoftheWRADD[4:0]address

PAFn FLAG BUS OPERATION

TheIDT72V51236/72V51246/72V51256Multi-QueueFIFOdevicecanbe buscorrespondtothedeviceIDinputsID[2:0].ThePAFnbuswillchangestatus

configuredforupto4FIFOqueues,eachqueuehavingitsownalmostfullstatus. toshowthenewdeviceselected1WCLKcycleafterdeviceselection.Note,that

Anactivequeuehasitsflagstatusoutputtothediscreteflags,FFandPAF,on if a read or write operation is occurring to a specific queue, say queue ‘x’ on

thewriteport.Queuesthatarenotselectedforawriteoperationcanhavetheir thesamecycleasaPAFnbusswitchtothedevicecontainingqueue‘x’,then

PAFstatus monitoredviathe PAFnbus.ThePAFnflagbus is 4bits wide,so theremaybeanextraWCLKcycledelaybeforethatqueuesstatusiscorrectly

that all 4 queues can have their status output to the bus. When a single shownontherespectiveoutputofthe PAFnbus.However,the“active” PAF

Multi-Queuedeviceisusedanywherefrom1to4queuesmaybeset-upwithin flagwillshowcorrectstatusatalltimes.

thepart,eachqueuehavingitsowndedicatedPAFflagoutputonthePAFnbus.

Devices can be selected on consecutive WCLK cycles, that is the device

Queues 1 through 4 have their PAF status to PAF[0] through PAF[3] controllingthe PAFnbus canchange everyWCLKcycle. Also, data present

respectively. If less than 4 queues are used then only the associated PAFn ontheinputbus,Din,canbewrittenintoaFIFOqueueonthesameWLCKrising

outputswillberequired,unusedPAFnoutputswillbedon’tcareoutputs.When edgethatadeviceisbeingselectedonthePAFnbus,theonlyrestrictionbeing

devices are connected in expansion mode the PAFn flag bus can also be thatawritequeueselectionandPAFnbusselectioncannotbemadeonthesame

expandedbeyond4bits toproduce a widerPAFnbus thatencompasses all cycle.

queues.

25

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PAFn BUS EXPANSION– POLLED MODE

devicesmustbeinhighimpedancestate).Therearetwomethodsbywhichthe

IfFMisHIGHatMasterResetthenthePAFnbusoperatesinPolled(Looped) user can select which device has control of the bus, these are “Direct”

mode.InpolledmodethePAFnbusautomaticallycyclesthroughthedevices (Addressed)modeor“Polled”(Looped)mode,determinedbythestateofthe

connected in expansion. In expansion mode one device will be set as the FM (flag Mode) input during a Master Reset.

Master,MASTinputtiedHIGH,allotherdeviceswillhaveMASTtiedLOW.The

masterdeviceisthefirstdevicetotakecontrolofthePAFnbusandplacethe PAEn/PRn BUS EXPANSION- DIRECT MODE

PAFstatusofitsqueuesontothebusonthefirstrisingedgeofWCLKafterthe

If FM is LOW at Master Reset then the PAEn/PRn bus operates in Direct

MRSinputgoesHIGHonceaMasterResetiscomplete.TheFSYNC(PAFsync (addressed)mode.Indirectmodetheusercanaddressthedevicetheyrequire

pulse)outputofthefirstdevice(masterdevice),willbeHIGHforonecycleof tocontrolthePAEn/PRnbus.Theaddresspresentonthe3mostsignificantbits

WCLKindicatingthatitishascontrolofthePAFnbusforthatcycle.

ofthe RDADD[5:0]address bus withESTR(PAE/PRflagstrobe), HIGHwill

Thedevicealsopassesa“token”ontothenextdeviceinthechain,thenext beselectedasthedeviceonarisingedgeofRCLK.Sotoaddressthefirstdevice

deviceassumingcontrolofthePAFnbusonthenextWCLKcycle.Thistoken ina bankofdevices the RDADD[5:0]address shouldbe “000xx”the second

passing is done via the FXO outputs and FXI inputs of the devices (“PAFn device“001xx”andsoon.The3mostsignificantbitsoftheRDADD[5:0]address

ExpansionOut”and“PAFnExpansionIn”).TheFXOoutputofthefirstdevice buscorrespondtothedeviceIDinputsID[2:0].ThePAEn/PRnbuswillchange

connectingtothe FXIinputofthe seconddevice inthe chain, the FXOofthe status toshowthenewdeviceselected1RCLKcycleafterdeviceselection.

seconddeviceconnects totheFXIofthethirddeviceandsoon.TheFXOof Note,thatifareadorwriteoperationisoccurringtoaspecificqueue,sayqueue

thefinaldeviceinachainconnectstotheFXIofthefirstdevice,sothatoncethe ‘x’onthesamecycleasaPAEn/PRnbusswitchtothedevicecontainingqueue

PAFn bus has cycled through all devices control is again passed to the first ‘x’,thentheremaybeanextraRCLKcycledelaybeforethatqueuesstatusis

device.TheFXOoutputofadevicewillbeHIGHfortheWCLKcycleithascontrol correctlyshownontherespectiveoutputofthePAEn/PRnbus.However,the

ofthebus.

PleaserefertoFigure24,PAFnBus–PolledModefortiminginformation.

“active”PAEand/orPRflagwillshowcorrectstatusatalltimes.

Devices can be selected on consecutive RCLK cycles, that is the device

controllingthePAEn/PRnbuscanchangeeveryRCLKcycle.Also,datacan

be read out of a FIFO queue on the same RCLK rising edge that a device is

PAEn/PRn FLAG BUS OPERATION

TheIDT72V51236/72V51246/72V51256Multi-QueueFIFOdevicecanbe beingselectedonthePAEn/PRnbus,theonlyrestrictionbeingthatareadqueue

configuredforupto4FIFOqueues,eachqueuehavingitsownalmostempty/ selectionandPAEn/PRnbusselectioncannotbemadeonthesamecycle.

packetreadystatus.Anactivequeuehasitsflagstatusoutputtothediscreteflags,

OV, PAE and PR, on the read port. Queues that are not selected for a read PAEn/PRn BUS EXPANSION- POLLED MODE

operationcanhavetheirPAE/PRstatusmonitoredviathePAEn/PRnbus.The

IfFMis HIGHatMasterResetthenthePAEn/PRnbus operates inPolled

PAEn/PRnflagbusis4bitswide,sothatall4queuescanhavetheirstatusoutput (Looped)mode.InpolledmodethePAEn/PRnbusautomaticallycyclesthrough

tothebus.TheMulti-Queuedevicecanprovideeither“AlmostEmpty”status thedevicesconnectedinexpansion.Inexpansionmodeonedevicewillbeset

or“PacketReady”statusviathePAEn/PRnbusofitsqueues,dependingon astheMaster,MASTinputtiedHIGH,allotherdeviceswillhaveMASTtiedLOW.

whichhas beenselectedviathePKT(Packet)inputduringamasterreset.If ThemasterdeviceisthefirstdevicetotakecontrolofthePAEn/PRnbusand

PKTisHIGHthenpacketmodeisselectedandthePAEn/PRnbuswillprovide placethePAE/PRstatusofitsqueuesontothebusonthefirstrisingedgeofRCLK

“PacketReady”status.IfitisLOWthenthePAEn/PRnbuswillprovide“Almost aftertheMRSinputgoesHIGHonceaMasterResetiscomplete.TheESYNC

Empty”status.Ineithercasetheoperationofthebusisthesamethedifference (PAE/PRsyncpulse)outputofthefirstdevice(masterdevice),willbeHIGHfor

beingthatthebusisproviding“PacketReady”statusversus“AlmostEmpty” onecycleofRCLKindicatingthatitishascontrolofthePAEn/PRnbusforthat

status.

WhenasingleMulti-Queuedeviceisusedanywherefrom1to4queuesmay

cycle.

Thedevicealsopassesa“token”ontothenextdeviceinthechain,thenext

beset-upwithinthepart,eachqueuehavingitsowndedicatedPAEn/PRnflag deviceassumingcontrolofthePAEn/PRnbus onthenextRCLKcycle.This

outputonthePAEn/PRnbus.Queues1through4havetheirPAE/PRstatus tokenpassingisdoneviatheEXOoutputsandEXIinputsofthedevices(“PAEn/

toPAE[0]throughPAE[3]respectively.Iflessthan4queuesareusedthenonly PRnExpansionOut”and“PAEn/PRnExpansionIn”).TheEXOoutputofthe

theassociatedPAEn/PRnoutputswillberequired,unusedPAEn/PRn outputs firstdeviceconnectingtotheEXIinputoftheseconddeviceinthechain,theEXO

willbedon’tcareoutputs.Whendevicesareconnectedinexpansionmodethe oftheseconddeviceconnectstotheEXIofthethirddeviceandsoon.TheEXO

PAEn/PRn flagbus canalsobe expandedbeyond4bits toproduce a wider ofthefinaldeviceinachainconnectstotheEXIofthefirstdevice,sothatonce

PAEn/PRnbusthatencompassesallqueues.

the PAEn/PRnbus has cycledthroughalldevices controlis againpassedto

Alternatively,the4bitPAEn/PRn flagbusofeachdevicecanbeconnected the firstdevice. The EXOoutputofa device willbe HIGHforthe RCLKcycle

togethertoformasingle4bitbus,i.e.PAE[0]ofdevice1willconnecttoPAE[0] ithascontrolofthebus.

ofdevice2etc.WhenconnectingdevicesinthismannerthePAEn/PRnbuscan

Please refer to Figure 25, PAEn/PRn Bus – Polled Mode for timing

onlybedrivenbyasingledeviceatanytime,(thePAEn/PRn outputsofallother information.

26

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

D35-D27

D26-D18

D17-D9

D8-D0

BYTE ORDER ON INPUT PORT:

Write to FIFO Queue

A

B

C

D

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

BYTE ORDER ON OUTPUT PORT:

BM

L

IW OW

A

B

C

D

Read from FIFO Queue

L

(a) x36 INPUT to x36 OUTPUT

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

BM

H

IW OW

1st: Read from FIFO Queue

2nd: Read from FIFO Queue

C

D

L

Q26-Q18

Q17-Q9

Q8-Q0

A

B

(b) x36 INPUT to x18 OUTPUT

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

BM

H

IW OW

D

1st: Read from FIFO Queue

2nd: Read from FIFO Queue

L

H

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

C

Q8-Q0

B

3rd: Read from FIFO Queue

4th: Read from FIFO Queue

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

A

(c) x36 INPUT to x9 OUTPUT

D35-D27

D26-D18

D17-D9

D8-D0

BYTE ORDER ON INPUT PORT:

A

1st: Write to FIFO Queue

2nd: Write to FIFO Queue

B

D26-D18

D17-D9

D8-D0

C

D

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

BYTE ORDER ON OUTPUT PORT:

BM

H

IW OW

D

B

C

A

Read from FIFO Queue

H

L

(d) x18 INPUT to x36 OUTPUT

BYTE ORDER ON INPUT PORT:

D35-D27

D26-D18

D17-D9

D8-D0

A

1st: Write to FIFO Queue

2nd: Write to FIFO Queue

D8-D0

B

D8-D0

C

3rd: Write to FIFO Queue

4th: Write to FIFO Queue

D8-D0

D

Q35-Q27

Q26-Q18

Q17-Q9

Q8-Q0

BYTE ORDER ON OUTPUT PORT:

BM

H

IW OW

D

C

B

A

Read from FIFO Queue

H

(e) x9 INPUT to x36 OUTPUT

5937 drw08

Figure 3. Bus-Matching Byte Arrangement

27

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tRS

MRS

t

RSS

WEN

REN

t

tRSR

SENI

tRSS

FSTR,

ESTR

tRSS

WADEN,

RADEN

t

RSS

ID0, ID1,

ID2

t

OW, IW,

BM

t

HIGH = Looped

LOW = Strobed (Direct)

FM

MAST

PKT

t

RSS

HIGH = Master Device

LOW = Slave Device

t

HIGH = Packet Ready Mode

LOW = Almost Empty

t

RSS

HIGH = Default Programming

LOW = Serial Programming

DFM

t

HIGH = Offset Value is 128

LOW = Offset value is 8

DF

t

RSF

LOGIC "1" if Master Device

FF

HIGH-Z if Slave Device

RSF

LOGIC "1" if Master Device

OV

PAF

PAE

HIGH-Z if Slave Device

LOGIC "1" if Master Device

HIGH-Z if Slave Device

LOGIC "0" if Master Device

t

RSF

LOGIC "1" if Master Device

HIGH-Z if Slave Device

PAFn

PAEn

PR

HIGH-Z if Slave Device

LOGIC "0" if Master Device

LOGIC "1" if Master Device

HIGH-Z if Slave Device

LOGIC "1" if Master Device

HIGH-Z if Slave Device

PRn

LOGIC "1" if OE is LOW and device is Master

Qn

HIGH-Z if OE is HIGH or Device is Slave

5937 drw09

NOTES:

1. OE can toggle during this period.

2. PRS should be HIGH during a MRS.

Figure 4. Master Reset

28

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

w-2

w-1

w

w+1

w+2

w+3

WCLK

tQH

tQS

WADEN

WEN

tENS

t

AS

tAH

WRADD

Qx

t

WFF

FF

tWAF

PAF

t

PAF

Active Bus

PAF-Qx⁽⁵⁾

tPRSS

tPRSH

PRS

tPRSH

tPRSS

RCLK

tENS

REN

tQH

tQS

RADEN

t

AS

tAH

RDADD

Qx

tROV

OV

tRAE

PAE

t

PAE

Active Bus

PAE-Qx⁽⁶⁾

r-2

r-1

r

r+1

r+2

r+3

5937 drw10

NOTES:

1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.

2. The queue must be selected a minimum of 2 clock cycles before the Partial Reset takes place, on both the write and read ports.

3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.

4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.

5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.

6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.

Figure 5. Partial Reset

Master Reset

Default Mode

DFM = 0

MRS

DFM

MRS

DFM

MQ2

MQn

MQ1

Serial Loading

Complete

SENI

SI

SENO

SO

SENI

SI

SENI

SI

SENO

SO

SENO

SO

Serial Enable

Serial Input

SCLK

5937 drw11

Serial Clock

Figure 6. Serial Port Connection for Serial Programming

29

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

30

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

31

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

32

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

WCLK

tENH

tENS

WEN

tDS

tDH

tDS

tDH

tDS

tDH

W1

W2

W3

Dn

RCLK

REN

t

SKEW1

1

2

tENS

tA

Last Word Read Out of Queue

W1 Qy

FWFT

W2 Qy

FWFT

W3 Qy

Qout

OV

tROV

5937 drw13a

NOTES:

1. Qy has previously been selected on both the write and read ports.

2. OE is LOW.

3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.

Figure 10. Write Operations & First Word Fall Through

33

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

34

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

35

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

*A*

*B*

*C*

*D*

*E*

*F*

*G*

*H*

*I*

RCLK

REN

tENS

tAS

tAH

tAS

tQS

tAH

RDADD

RADEN

D1

Q3

D1 Q2

Addr=001011

tQH

Addr=001010

tQS

tQH

tA

tOLZ

Qout

(Device 1)

D

1

Q

3

WD

Last Word

D1 Q2

PFT We-1

D1

Q2

We

Last Word

tROV

W0 Q2

D1

tROV

tOVLZ

HIGH-Z

OV

(Device 1)

tOVHZ

OV

(Device 2)

tSKEW1

WCLK

tENS

tENH

WEN

tAS

tQS

tAH

tQH

WRADD

D1 Q2

WADEN

Din

tDS

tDH

D1 Q2

W0

5937 drw16

Cycle:

*A* Queue 3 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control

of Qout bus, its Qout outputs are in Low-Impedance. This diagram only shows the Qout outputs of device 1. (Reads are disabled).

*B* Reads are now enabled. A word from the previously selected queue of Device 2 will be read out.

*C* The Qout of Device 1 goes to Low-Impedance and word Wd is read from Q3 of D1. This happens to be the last word of Q3. Device 2 places its Qout outputs into

High-Impedance, device 1 has control of the Qout bus. The OV flag of Device 2 goes to High-Impedance and Device 1 takes control of OV. The OV flag of Device 1 goes LOW

to show that Wd of Q3 is valid.

*D* Queue 2 of device 1 is selected for read operations. The last word of Q3 was read on the previous cycle, therefore OV goes HIGH to indicate that the data on the Qout is

not valid (Q3 was read to empty). Word, Wd remains on the output bus.

*E* The last word of Q3 remains on the Qout bus, OV is HIGH, indicating that this word has been previously read.

*F* The next word (We-1), available from the newly selected queue, Q2 of device 1 is now read out. This will occur regardless of REN, 2 RCLK cycles after queue selection

due to the FWFT operation. The OV flag now goes LOW to indicate that this word is valid.

*G* The last word, We is read from Q2, this queue is now empty.

*H* The OV flag goes HIGH to indicate that Q2 was read to empty on the previous cycle.

*I* Due to a write operation the OV flag goes LOW and data word W0 is read from Q2. The latency is: t^SKEW1+ 1*RCLK + tROV.

Figure 13. Output Valid Flag Timing (In Expansion Mode)

36

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

*A*

*B*

*C*

*D*

*E*

*F*

*G*

*H*

*I*

*J*

RCLK

tENS

tENH

tENS

tENH

REN

tAS

tAH

tAS

RDADD

Qn

QP

tQS

tQH

tQS

tQH

RADEN

tA

QOUT

QP

WD

QP WD+1

Q

P

WD+2

Qn

WX

Qn

WX+1

Q

P

WD+3

QP WD+4

OV

5937 drw17

Cycle:

*A* Word Wd+1 is read from the previously selected queue, Qp.

*B* Reads are disabled, word Wd+1 remains on the output bus.

*C* A new queue, Qn is selected for read port operations.

*D* Due to FWFT operation Word, Wd+2 of Qp is read out regardless of REN.

*E* The next available word Wx of Qn is read out regardless of REN, 2 RCLK cycles after queue selection. This is FWFT operation.

*F* The queue, Qp is again selected.

*G* Word Wx+1 is read from Qn regardless of REN, this is due to FWFT.

*H* Word Wd+3 is read from Qp, this read occurs regardless of REN due to FWFT operation.

*I* Word Wd+4 is read from Qp.

*J* Reads are disabled on this cycle, therefore no further reads occur.

Figure 14. Read Queue Selection with Reads Disabled

*A*

*B*

*C*

*D*

*E*

*F*

*G*

*H*

*I*

RCLK

REN

tENS

tENH

tENS

tAS

tAH

tAS

tAH

RDADD

RADEN

QB

QA

tQS

tQH

tQS

tQH

OE

tA

tOHZ

tA

tOE

tOLZ

Qout

Previous Data in O/P Register

Q

A

W

0

QA

W1

QA

W2

QA

W3

QA W4

No Read

Q is Empty

ROV

PFT

B

tROV

t

OV

5937 drw18

NOTES:

1. The Output Valid flag, OV is HIGH therefore the previously selected queue has been read to empty. The Output Enable input is Asynchronous, therefore the Qout output bus

will go to Low-Impedance after time t^OLZ.

The data currently on the output register will be available on the output after time t^OE. This data is the previous data on the output register, this is the last word read out of the

previous queue.

2. In expansion mode the OE inputs of all devices should be connected together. This allows the output busses of all devices to be High-Impedance controlled.

Cycle:

*A* Queue A is selected for reads. No data will fall through on this cycle, the previous queue was read to empty.

*B* No data will fall through on this cycle, the previous queue was read to empty.

*C* Word, W0 from Qa is read out regardless of REN due to FWFT operation. The OV flag goes LOW indicating that Word W0 is valid.

*D* Reads are disabled therefore word, W0 of Qa remains on the output bus.

*E* Reads are again enabled so word W1 is read from Qa.

*F* Word W2 is read from Qa.

*G* Queue, Qb is selected on the read port. This queue is actually empty. Word, W3 is read from Qa.

*H* Word, W4 falls through from Qa.

*I* Output Valid flag, OV goes HIGH to indicate that Qb is empty. Data on the output port is no longer valid.

Output Enable is taken HIGH, this is Asynchronous so the output bus goes to High-Impedance after time, t^OHZ.

Figure 15. Read Queue Select, Read Operation and OE Timing

37

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

SELECT

NEW QUEUE

*D*

NULL QUEUE

SELECT

*B*

*C*

*E*

*F*

*A*

0001xx

t

RCLK

tAS

t

AH

t

AS

tAH

000011

D0 Q3

RDADD

RADEN

tQS

t

QH

t

QS

tQH

tENS

ENH

REN

tA

Qout

Q1 Wn-3

Q1 Wn-2

Q1 Wn-1

Q1 Wn

Q3 W0

FWFT

tROV

OV

5937 drw19

NOTES:

1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words

from that queue.

2. Please see Figure 17, Null Queue Flow Diagram.

Cycle:

*A* Null Q of device 0 is selected, when word Wn-1 from previously selected Q1 is read.

*B* REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register.

Note: *B* and *C* are a minimum 2 RCLK cycles between Q selects.

*C* The Null Q is seen as an empty FIFO on the read side, therefore Wn of Q1 remains in the O/P register and OV goes HIGH.

*D* A new Q, Q3 is selected and the 1st word of Q3 will fall through present on the O/P register on cycle *F*.

Figure 16. Read Operation and Null Queue Select

*A*

*B*

*C*

*D*

*E*

*F*

Null

Queue

Queue 3

Memory

Queue 3

Memory

Queue 1

Memory

Null

Queue

Null

Queue

Q1

Q3

Wn

W0

W1

O/P Reg.

Qn

Q1

Q3

Wn-1

Wn

W0

5937 drw20

Figure 17. Null Queue Flow Diagram

38

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

*A*

*B*

*C*

*E*

*F*

*D*

WCLK

WEN

1

2

tENH

tENS

tAS

tAH

tAS

tQS

tAH

WRADD

D1 Q2

D1 Q0

tQS

tQH

WADEN

Din

tDS

tDH

WD-m

D1 Q2

tWAF

tAFLZ

HIGH-Z

PAF

(Device 1)

tFFHZ

PAF

(Device 2)

5937 drw21

Cycle:

*A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.

*B* No write occurs.

*C* Word, Wd-m is written into Q2 causing the PAF flag to go from HIGH to LOW. The flag latency is 2 WCLK cycles + t^WAF.

*D* Queue 0 if device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 2 WCLK + t^WAFlatency.

*E* The PAF flag goes LOW based on the write 2 cycles earlier.

*F* The PAF flag goes HIGH due to the queue switch to Q0.

Figure 18. Almost Full Flag Timing and Queue Switch

tCLKL

WCLK

WEN

PAF

1

2

1

tENS

tENH

tWAF

D - (m+1) words in FIFO⁽²⁾

D-(m+1) words

in FIFO

D - m words in FIFO

tSKEW2

RCLK

tENS

tENH

5937 drw22

REN

NOTE:

1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read

from at the almost full boundary.

Flag Latencies:

Assertion: 2*WCLK + t^WAF

De-assertion: tSKEW2 + WCLK + tWAF

If tSKEW2 is violated there will be one extra WCLK cycle.

Figure 19. Almost Full Flag Timing

39

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

*A*

*B*

*C*

*D*

*E*

*F*

*G*

RCLK

REN

HIGH

AS

t

tAH

tAS

tAH

RDADD

D1

Q3

D1

Q1

tQS

tQH

tQS

RADEN

Qout

tA

tOLZ

HIGH-Z

D1

Q3

Wn

D

1

Q3

Wn+1

D

1

Q1

W0

D1 Q1 W1

t

RAE

t

RAE

tAELZ

PAE

(Device 1)

tAEHZ

PAE

(Device 2)

HIGH-Z

5937 drw23

Cycle:

*A* Queue 3 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.

*B* No read occurs.

*C* The PAE flag output now switches to device 1. Word, Wn is read from Q3 due to the FWFT operation. This read operation from Q3 is at the almost empty boundary, therefore

PAE will go LOW 2 RCLK cycles later.

*D* Q1 of device 1 is selected.

*E* The PAE flag goes LOW due to the read from Q3 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.

*F* Word, W0 is read from Q1 due to the FWFT operation. The PAE flag goes HIGH to show that Q1 is not almost empty.

Figure 20. Almost Empty Flag Timing and Queue Switch

tCLKH

tCLKL

WCLK

tENS

tENH

WEN

PAE

n+1 words in FIFO

n+2 words in FIFO

n+1 words in FIFO

tRAE

tSKEW2

tRAE

1

2

RCLK

tENS

tENH

5937 drw24

REN

NOTE:

1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read

from at the almost empty boundary.

Flag Latencies:

Assertion: 2*RCLK + t^RAE

De-assertion: tSKEW2 + RCLK + tRAE

If tSKEW2 is violated there will be one extra RCLK cycle.

Figure 21. Almost Empty Flag Timing

40

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

*A*

*B*

*C*

*D*

*E*

*F*

1

2

WCLK

WADEN

FSTR

tQH

tQS

tQH

t

STS

tSTH

tENS

tENH

WEN

tAH

tAS

t

AS

t

AS

tAH

Device 4

D3Q2

01110

WRADD

Dn

D5Q3

100 11

tDH

100 xx

tDS

tDH

tDS

Wp

Wp+1

Wn+1

D5Q3

Wn

D5 Q3

Wx

D3 Q2

Writes to Previous Q

tSKEW3

RCLK

RADEN

ESTR

1

2

tQS

tQH

t

STS

t

STH

tENS

tENH

REN

tAH

t

AS

t

AS

tAH

RDADD

Device 5

D5Q3

100 011

101 xxx

tA

Wy

D5 Q3

Wy+1

D5 Q3

Wy+3

D5 Q3

Device 5 -Qn

Wa

D5 Qx

Wa+1

D5 Qn

Wy+2

D5 Q3

Previous value loaded on to PAE bus

Prev PAEn

t

PAEHZ

t

PAE

tPAEZL

1xxx

Device 5 PAEn

Device 5

1xxx

Device 5

1xxx

Device 5

Previous value loaded on to PAE bus

D5 Qx Status

Bus PAEn

t

RAE

tRAE

D5 Q3

status

Device 5 PAE

5937 drw25

*AA*

*BB*

*CC*

*EE*

*FF*

*DD*

Cycle:

*A* Queue 3 of Device 5 is selected for write operations.

Word, Wp is written into the previously selected queue.

*AA* Queue 3 of Device 5 is selected for read operations.

Another device has control of the PAEn bus.

The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.

*B* Word Wp+1 is written into the previously selected queue.

*BB* Word, Wa+1 is read from Qx of D5, due to FWFT operation.

*C* Word, Wn is written into the newly selected queue, Q3 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,

t^SKEW3+ RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added.

*CC* Word, Wy from the newly selected queue, Q3 will be read out due to FWFT operation.

Device 5 is selected on the PAEn bus. Q3 of device 5 will therefore have is PAE status output on PAE[3]. There is a single RCLK cycle latency before the PAEn bus changes

to the new selection.

*D* Queue 2 of Device 3 is selected for write operations.

Word Wn+1 is written into Q3 of D5.

*DD* The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and are placed onto the outputs. The previously selected device now places its

PAEn outputs into High-Impedance to prevent bus contention. Word, Wy+1 is read from Q3 of D5.

The discrete PAE flag will go HIGH to show that Q3 of D5 is not almost empty. Q3 of device 5 will have its PAE status output on PAE[3].

*E* No writes occur.

*EE* Word, Wy+2 is read from Q3 of D5.

*F* Device 4 is selected on the write port for the PAFn bus.

Word, Wx is written into Q2 of D3.

*FF* The PAEn bus updates to show that Q3 of D5 is almost empty based on the reading out of word, Wy+1.

The discrete PAE flag goes LOW to show that Q3 of D5 is almost empty based on the reading of Wy+1.

Figure 22. PAEn - Direct Mode, Flag Operation – Devices in Expansion

41

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

*A*

*B*

*C*

*D*

*E*

*F*

*G*

RCLK

tQH

tQS

tQH

RADEN

t

STH

t

STS

ESTR

REN

t

AS

tAH

t

AS

RDADD

Device 7

111 xxx

D6Q2

110 010

D0Q1

000 001

OE

tA

tOLZ

Qout

W

Prev. Q

X

W

Prev. Q

X +1

W

D0 Q1

D - M + 2

W0

D6 Q2

W

D0 Q1

D-M+1

tSKEW3

WCLK

FSTR

1

2

t

STS

t

STH

t

AS

tAH

tAS

tAH

WRADD

Device 0

000 xxx

D0 Q1

tENS

tENH

WEN

tQS

tQH

WADEN

Din

t

DS

t

DH

tDS

tDH

tDS

tDH

Word W

y

Wy+1

Wy+2

D0 Q1

t

PAFLZ

tPAF

t

PAF

Device 0 PAFn

xx0x

xx1x

xx0x

Device 0

HIGH-Z

Previous Device

Bus PAFn

Device 0

t

PAFHZ

HIGH-Z

Prev. PAFn

t

PAFLZ

tWAF

Device 0 PAF

HIGH - Z

5937 drw26

*AA*

*BB*

*CC*

*DD*

*EE*

*FF*

Cycle:

*A* Queue 1 of device 0 is selected for read operations.

The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.

*AA* Device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected device X.

*B* Word, Wx+1 is read out from the previous queue due to the FWFT effect.

*BB* Queue 1 of device 0 is selected on the write port.

The PAFn bus is updated with the device selected on the previous cycle, device 0 PAF[1] is LOW showing the status of queue 1.

The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.

*C* Device 7 is selected for the PAFn bus.

Word, Wd-m+1 is read from Q1 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q1. This read will cause the PAF[1] output to go from

LOW to HIGH (almost full to not almost full), after a delay t^SKEW3+ WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.

*CC* PAFn continues to show status of D0.

*D* No read operations occur, REN is HIGH.

*DD* PAF[1] goes HIGH to show that D0 Q1 is not almost empty due to the read on cycle *C*.

The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.

Word, Wy is written into D0 Q1.

*E* Queue 2 of Device 6 is selected for write operations.

*EE* Word, Wy+1 is written into D0 Q1.

*F* Word, Wd-m+2 is read out due to FWFT operation.

*FF* PAF[1] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q1 of D0 to again go almost full.

Word, Wy+2 is written into D0 Q1.

*G* Word, W0 is read from Q0 of D6, selected on cycle *E*, due to FWFT.

Figure 23. PAFn - Direct Mode, Flag Operation – Devices in Expansion

42

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

WCLK

t

FSYNC

tFSYNC

t

FSYNC

t

FSYNC

FXO

FSYNC

0

(MASTER)

tFXO

t

FXO

tFXO

t

FXO /

0

FXI

1

tFSYNC

FSYNC

1

(SLAVE)

tFXO

FXO /

1

FXI

2

tFSYNC

FSYNC

2

(SLAVE)

tFXO

FXO /

2

FXI

0

t

PAF

t

PAF

tPAF

t

PAF

t

PAF

PAF[3:0]

Device 0

Device 1

Device 2

Device 0

5937 drw27

Figure 24. PAFn Bus - Polled Mode

NOTE:

1. This diagram is based on 3 devices connected to expansion mode.

43

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

RCLK

t

ESYNC

tESYNC

t

ESYNC

t

ESYNC

EXO

ESYNC

0

tEXO

t

EXO

tEXO

t

EXO /

0

EXI

1

tESYNC

ESYNC

1

tEXO

EXO /

1

FXI

2

tESYNC

ESYNC

2

tEXO

EXO /

2

EXI

0

t

PAE

t

PAE

tPAE

t

PAE

t

PAE

Device 0

Device 1

Device 2

Device 0

n

5937 drw28

Figure 25. PAEn/PRn Bus - Polled Mode

44

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

45

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

46

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Serial Programming Data Input

Serial Enable

SENI

SI FXI EXI

Output Data Bus

Data Bus

Q -Q

35

D -D

35

0

Read Clock

Write Clock

RCLK

WCLK

Write Enable

Read Enable

WEN

REN

RDADD

RADEN

Write Queue Select

Write Address

Read Queue Select

Read Address

WRADD

DEVICE

1

WADEN

FSTR

Empty Strobe

Full Strobe

ESTR

PAEn

Programmable Almost Full

Programmable Almost Empty

PAFn

Empty Sync 1

Output Valid Flag

Almost Empty Flag

Packet Reads

Full Sync1

ESYNC

FSYNC

Full Flag

OV

FF

Almost Full Flag

Serial Clock

PAF

PAE

PR

SCLK

SENO SO FXO EXO

SENI SI FXI EXI

Q -Q

D -D

35

0

35

0

WCLK

RCLK

WEN

REN

WRADD

WADEN

RDADD

RADEN

DEVICE

2

FSTR

PAFn

ESTR

PAEn

Empty Sync 2

Full Sync2

FSYNC

ESYNC

FF

OV

PAF

PAE

SCLK

PR

SENO SO FXO EXO

SENI SI FXI EXI

Q -Q

D -D

35

0

35

0

WCLK

RCLK

REN

WEN

WRADD

WADEN

RDADD

RADEN

DEVICE

n

FSTR

PAFn

FSYNC

ESTR

PAEn

Full Sync n

Empty Sync n

ESYNC

FF

OV

PAF

PAE

PR

SCLK

SENO

FXO EXO

DONE

5937 drw31

NOTES:

1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO

outputs are DNC (Do Not Connect).

2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.

Figure 28. Multi-Queue Expansion Diagram

47

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

TheStandardJTAGinterfaceconsistsoffourbasicelements:

JTAGINTERFACE

•

Test Access Port (TAP)

TAPcontroller

Instruction Register (IR)

Data Register Port (DR)

Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to

support the JTAG boundary scan interface. The IDT72V51236/72V51246/

72V51256incorporates thenecessarytapcontrollerandmodifiedpadcellsto

implementtheJTAG facility.

NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage

programfilesforthesedevices.

Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora

completedescriptionrefertotheIEEEStandardTestAccessPortSpecification

(IEEEStd. 1149.1-1990).

The Figure belowshows the standardBoundary-ScanArchitecture

DeviceID Reg.

Mux

Boundary Scan Reg.

Bypass Reg.

TDO

TDI

T

A

clkDR, ShiftDR

UpdateDR

P

TMS

TAP

TCLK

Cont-

roller

TRST

Instruction Decode

clklR, ShiftlR

UpdatelR

Instruction Register

Control Signals

5937 drw32

Figure 29. Boundary Scan Architecture

THETAPCONTROLLER

TEST ACCESS PORT (TAP)

TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto

TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction

andDataRegisters forcaptureandupdateofdata.

The Tap interface is a general-purpose port that provides access to the

internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)

and one output port (TDO).

48

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

1

Test-Logic

Reset

0

1

Select-

IR-Scan

0

1

Run-Test/

Idle

Select-

DR-Scan

0

1

Capture-DR

Capture-IR

0

Shift-DR

Shift-IR

1

Input = TMS

Exit1-IR

EXit1-DR

0

Pause-DR

Pause-IR

1

Exit2-IR

Exit2-DR

0

1

Update-DR

Update-IR

1

0

1

0

5937 drw33

Figure 30. TAP Controller State Diagram

EXIT1-DR / EXIT2-DR

Refer to the IEEE Standard Test Access Port Specification (IEEE Std.

1149.1)forthefullstatediagram

AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe

TCLKpulse. TheTMSsignallevel(0or1)determines thestateprogression

that occurs on each TCLK rising edge.

Thisisatemporarycontrollerstate. IfTMSisheldhigh,arisingedgeapplied

toTCKwhileinthisstatecausesthecontrollertoentertheUpdate-DRstate. This

terminatesthescanningprocess. Alltestdataregistersselectedbythecurrent

instructionretaintheirpreviousstateunchanged.

PAUSE-DR

CAPTURE-DR

Thiscontrollerstateallowsshiftingofthetestdataregisterintheserialpath

betweenTDIandTDOtobetemporarilyhalted. Alltestdataregistersselected

bythecurrentinstructionretaintheirpreviousstateunchanged.

Data is loaded from the parallel input pins or core outputs into the Data

Register.

SHIFT-DR

Capture-IR, Shift-IR and Update-IR, Exit-IR and Pause-IR are

similartoDataregisters.Theseinstructionsoperateontheinstructionregisters.

Thepreviouslycaptureddataisshiftedinserially,LSBfirstattherisingedge

ofTCLKintheTDI/TDOpathandshiftedoutserially,LSBfirstatthefallingedge

ofTCLKtowardstheoutput.

UPDATE-DR

The shifting process has been completed. The data is latched into their

paralleloutputsinthisstatetobeaccessedthroughtheinternalbus.

49

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

THE INSTRUCTION REGISTER

JTAG INSTRUCTION REGISTER

TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice

whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto

performthefollowing:

TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe

processor at the rising edge of TCLK.

TheInstructionis usedtoselectthetesttobeperformed,orthetestdata

registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched

atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-

IRstate.

Theinstructionregistermustcontain4bitinstructionregister-basedcells

whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe

serialoutputstheyaretheleastsignificantbits.

•

Selecttestdataregistersthatmayoperatewhiletheinstructionis

current. Theothertestdataregistersshouldnotinterferewithchip

operationandtheselecteddataregister.

•

Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween

TDI and TDO during data register scanning.

The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode

16differentpossibleinstructions. Instructionsaredecodedasfollows.

TESTDATAREGISTER

Hex

Value

00

01

02

Instruction

Function

TheTestDataregistercontainsthreetestdataregisters:theBypass,the

Boundary Scan register and Device ID register.

Theseregistersareconnectedinparallelbetweenacommonserialinput

andacommonserialdataoutput.

Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora

completedescription,refertotheIEEEStandardTestAccessPortSpecification

(IEEEStd. 1149.1-1990).

EXTEST

SAMPLE/PRELOAD

IDCODE

High-Impedance

BYPASS

SelectBoundaryScanRegister

SelectChipIdentificationdataregister

JTAG

04

0F

SelectBypassRegister

JTAG INSTRUCTION REGISTER DECODING

TEST BYPASS REGISTER

Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For

acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification

(IEEEStd. 1149.1-1990).

TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI

toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.

Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage

is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in

theCapture-DRstate.

EXTEST

ThemandatoryEXTESTinstructionis providedforexternalcircuityand

boardlevelinterconnectioncheck.

The operation of the bypass register should not have any effect on the

operationofthedeviceinresponsetotheBYPASSinstruction.

IDCODE

THE BOUNDARY-SCAN REGISTER

ThisinstructionisprovidedtoselectDeviceIdentificationRegistertoread

outmanufacture’sidentity,partnumberandversionnumber.

TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread

outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart

oftheIEEE1149.1-1990StandardJTAGImplementation.

SAMPLE/PRELOAD

ThemandatorySAMPLE/PRELOADinstructionallowsdatavaluestobe

loadedontothelatchedparalleloutputsoftheboundary-scanshiftregisterprior

toselectionoftheboundary-scantestinstruction. TheSAMPLEinstruction

allowsasnapshotofdataflowingfromthesystempinstotheon-chiplogicor

vice versa.

THE DEVICE IDENTIFICATION REGISTER

The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto

specify the manufacturer, part number and version of the processor to be

determinedthroughtheTAPinresponsetotheIDCODEinstruction.

IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity

is droppedinthe11-bitManufacturerIDfield.

HIGH-IMPEDANCE

This instruction places all the output pins on the device into a High-

Impedancestate.

FortheIDT72V51236/72V51246/72V51256,thePartNumberfieldcon-

tainsthefollowingvalues:

Device

Part# Field (HEX)

0x41B

BYPASS

IDT72V51236

IDT72V51246

IDT72V51256

TheBypassinstructioncontainsasingleshift-registerstageandissetto

provideaminimum-lengthserialpathbetweentheTDIandtheTDOpinsofthe

device whennotest operation ofthe device is required.

0x41C

0x41D

31(MSB)

28 27

12 11

1 0(LSB)

Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)

0X0

0X33

1

JTAG DEVICE IDENTIFICATION REGISTER

50

IDT72V51236/72V51246/72V512563.3V, MULTI-QUEUEFIFO(4QUEUES)

36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tTCK

t

4

t

3

t

1

t

2

TCK

TDI/

TMS

tDS

tDH

TDO

t

6

tDO

TRST

5937 drw34

Notes to diagram:

t1 = tTCKLOW

t2 = tTCKHIGH

t

5

t3 = tTCKFALL

t4 = tTCKRise

t5 = tRST (reset pulse width)

t6 = tRSR (reset recovery)

Figure 31. Standard JTAG Timing

JTAG

ACELECTRICALCHARACTERISTICS

(vcc = 3.3V ± 5%; Tcase = 0°C to +85°C)

Parameter

Symbol

Test

Conditions

Min. Max. Units

SYSTEMINTERFACEPARAMETERS

JTAGClockInputPeriod tTCK

-

100

40

-

ns

IDT72V51236

IDT72V51246

IDT72V51256

JTAGClockHIGH

JTAGClockLow

tTCKHIGH

tTCKLOW

tTCKRise

tTCKFall

tRST

-

Parameter

DataOutput

Symbol Test Conditions Min. Max. Units

JTAGClockRiseTime

JTAGClockFallTime

JTAGReset

5⁽¹⁾

-

tDO = Max

5⁽¹⁾

5

50

-

ns

-

2

DataOutputHold

DataInput

tDOH

50

tDS

tDH

trise=3ns

tfall=3ns

30

-

JTAG Reset Recovery

tRSR

-

NOTES:

1. Guaranteed by design.

2. 50pf loading on external output signals.

NOTE:

1. Guaranteed by design.

51

ORDERINGINFORMATION

IDT

XXXXX

X

XX

X

Process /

Temperature

Range

Device Type

Power

Speed

Package

BLANK

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

BB

Plastic Ball Grid Array (PBGA, BB256-1)

Clock Cycle Time (tCLK

Speed in Nanoseconds

)

6

7-5

Commercial Only

Com’l & Ind’l

Low Power

L

72V51236 589,824 bits 3.3V Multi-Queue FIFO

72V51346 1,179,648 bits 3.3V Multi-Queue FIFO

72V51256 2,359,296 bits 3.3V Multi-Queue FIFO

5937 drw35

NOTE:

1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order.

DATASHEETDOCUMENTHISTORY

10/10/2001

11/16/2001

12/19/2001

01/15/2002

pgs. 1, 8, 11, 14, 15 and 28.

pgs. 4, 11, 17, 22-26, 28-31, 33, 45 and 46.

pgs. 12 and 29.

pg. 50.

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

408-330-1753

email:FIFOhelp@idt.com

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

52


型号：	72V51256L6BBI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FIFO 先进先出芯片
文件：	总52页 (文件大小：413K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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