72V51343L6BB9 [IDT]
PBGA-256, Tray;
| 型号： | 72V51343L6BB9 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PBGA-256, Tray LTE |
| 文件： | 总49页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3VMULTI-QUEUEFLOW-CONTROLDEVICES
(8QUEUES)18BITWIDECONFIGURATION
IDT72V51333
IDT72V51343
IDT72V51353
589,824bits
1,179,648bits
2,359,296bits
•
•
•
•
Individual, Active queue flags (OV, FF, PAE, PAF)
8 bit parallel flag status on both read and write ports
Provides continuous PAE and PAF status of up to 8 Queues
Global Bus Matching - (All Queues have same Input Bus Width
and Output Bus Width)
User Selectable Bus Matching Options:
- x18in to x18out
- x9in to x18out
FEATURES:
•
Choose from among the following memory density options:
IDT72V51333
IDT72V51343
IDT72V51353
Total Available Memory = 589,824 bits
Total Available Memory = 1,179,648 bits
Total Available Memory = 2,359,296 bits
•
•
•
Configurable from 1 to 8 Queues
Queues may be configured at master reset from the pool of
Total Available Memory in blocks of 512 x 18 or 1,024 x 9
Independent Read and Write access per queue
User programmable via serial port
Default multi-queue device configurations
-IDT72V51333: 4,096 x 18 x 8Q or 8,192 x 9 x 8Q
-IDT72V51343: 8,192 x 18 x 8Q or 16,384 x 9 x 8Q
-IDT72V51353: 16,384 x 18 x 8Q or 32,768 x 9 x 8Q
100% Bus Utilization, Read and Write on every clock cycle
166 MHz High speed operation (6ns cycle time)
3.7ns access time
- x18in to x9out
- x9in to x9out
•
•
•
•
•
•
•
•
•
•
FWFT mode of operation on read port
Partial Reset, clears data in single Queue
Expansion of up to 8 multi-queue devices in parallel is available
JTAG Functionality (Boundary Scan)
Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm
HIGH Performance submicron CMOS technology
Industrial temperature range (-40°C to +85°C) is available
•
•
•
FUNCTIONALBLOCKDIAGRAM
MULTI-QUEUE FLOW-CONTROL DEVICE
WADEN
FSTR
RADEN
ESTR
RDADD
REN
Q0
WRADD
WEN
7
6
RCLK
WCLK
OE
Q
out
D
in
x9, x18
x9, x18
DATA IN
DATA OUT
OV
FF
Q7
PAF
PAE
PAFn
8
PAEn
8
5940 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
JUNE 2003
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5940/9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Bus Matchingis available onthis device, eitherportcanbe 9bits or18bits
wide.WhenBusMatchingisusedthedeviceensuresthelogicaltransferofdata
throughputinaLittleEndianmanner.
DESCRIPTION:
The IDT72V51333/72V51343/72V51353 multi-queue flow-control de-
vicesaresinglechipwithinwhichanywherebetween1and8discreteFIFO
queuescanbesetup.Allqueueswithinthedevicehaveacommondatainput
bus,(writeport)andacommondataoutputbus,(readport).Datawritteninto
the write portis directedtoa respective queue via aninternalde-multiplex
operation,addressedbytheuser.Datareadfromthereadportisaccessed
froma respective queue via aninternalmultiplexoperation,addressedby
the user. Data writes and reads can be performed at high speeds up to
166MHz,withaccesstimesof3.7ns.Datawriteandreadoperationsaretotally
independent of each other, a queue maybe selected on the write port and
adifferentqueueonthereadportorbothportsmayselectthesamequeue
simultaneously.
The device provides FullflagandOutputValidflagstatus forthe queue
selectedforwriteandreadoperations respectively.AlsoaProgrammable
AlmostFullandProgrammableAlmostEmptyflagforeachqueueisprovided.
Two 8 bit programmable flag busses are available, providing status of all
queues,includingqueuesnotselectedforwriteorreadoperations,theseflag
busses provide an individual flag per queue.
Theuserhasfullflexibilityconfiguringqueueswithinthedevice,beingable
toprogramthetotalnumberofqueues between1and8,theindividualqueue
depthsbeingindependentofeachother.Theprogrammableflagpositionsare
alsouserprogrammable.Allprogrammingisdoneviaadedicatedserialport.
Iftheuserdoesnotwishtoprogramthemulti-queuedevice,adefaultoptionis
availablethatconfiguresthedeviceinapredeterminedmanner.
BothMasterResetandPartialResetpinsareprovidedonthisdevice.AMaster
Reset latches in all configuration setup pins and must be performed before
programmingofthedevicecantakeplace.APartialResetwillresetthereadand
writepointersofanindividualqueue,providedthatthequeueisselectedonboth
thewriteportandreadportatthetimeofpartialreset.
AJTAGtestportisprovided,herethemulti-queueflow-controldevicehasa
fullyfunctionalBoundaryScanfeature,compliantwithIEEE1149.1Standard
TestAccessPortandBoundaryScanArchitecture.
SeeFigure1,Multi-QueueFlow-ControlDeviceBlockDiagramforanoutline
ofthefunctionalblockswithinthedevice.
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
D
in
x9, x18
- D
D
0
17
WCLK
WEN
INPUT
DEMUX
TMS
TDI
6
WRADD
WADEN
Write Control
Logic
JTAG
Logic
TDO
TCK
TRST
Write Pointers
PAF
General Flag
Monitor
FSTR
PAFn
8
FSYNC
Upto 8
FIFO
Queues
FXO
FXI
OV
Active Q
Flags
PAE
0.5 Mbit
1.1 Mbit
2.3 Mbit
Dual Port
Memory
Active Q
Flags
FF
PAF
PAE
General Flag
Monitor
8
SI
SO
SCLK
PAEn
ESTR
ESYNC
EXI
Serial
Multi-Queue
Programming
SENI
SENO
EXO
Read Pointers
FM
IW
Reset
Logic
7
RDADD
RADEN
Read Control
Logic
OW
MAST
REN
RCLK
ID0
ID1
ID2
DF
Device ID
3 Bit
OUTPUT
MUX
PAE/ PAF
Offset
DFM
OUTPUT
REGISTER
PRS
MRS
5940 drw02
OE
Q
- Q
17
0
Q
x9, x18
out
Figure 1. Multi-Queue Flow-Control Device Block Diagram
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINCONFIGURATION
A1 BALL PAD CORNER
A
D14
D15
D13
D16
D12
D11
D10
D9
D7
D6
D4
D3
D1
D0
TCK
TMS
TDO
TDI
ID1
ID0
Q3
Q2
Q6
Q9
Q8
Q12
Q11
Q14
Q13
Q15
B
C
D
E
F
Q5
DNC
TRST
VCC
VCC
GND
GND
GND
GND
GND
GND
D17
GND
GND
GND
GND
GND
GND
GND
SI
GND
GND
GND
GND
GND
GND
GND
GND
DFM
GND
GND
GND
GND
GND
GND
GND
GND
DF
D8
D5
VCC
VCC
VCC
VCC
GND
GND
VCC
VCC
D2
GND
VCC
GND
GND
GND
GND
GND
GND
GND
ID2
VCC
GND
GND
GND
GND
GND
GND
GND
Q0
VCC
VCC
GND
GND
GND
GND
GND
GND
Q1
Q4
VCC
VCC
VCC
VCC
GND
GND
VCC
VCC
Q7
Q10
Q16
Q17
DNC
DNC
DNC
DNC
DNC
DNC
MAST
IW
DNC
DNC
DNC
DNC
DNC
DNC
DNC
FM
VCC
VCC
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
DNC
DNC
DNC
DNC
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
G
H
J
K
L
OW
M
N
P
R
T
SENO
SENI
OE
SO
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
VCC
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RDADD0 RDADD1
WRADD1 WRADD0
SCLK
VCC RDADD2 RDADD3 GND
FF
OV
PAE
GND
GND
WRADD2 WADEN
PAF3
PAF6
PAF7
PAE7
PAE6
PAE3 RDADD4 RDADD5 RDADD6
PAF
PRS
WRADD4 WRADD3 FSYNC
FSTR
PAF2
PAF1
PAF5
PAF4
DNC
DNC
DNC
PAE5
PAE4
PAE2
PAE1
RADEN ESTR
ESYNC
EXI
WEN
MRS
REN
WRADD5 FXI
FXO
PAF0
WCLK
RCLK
PAE0
EXO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
5940 drw03
NOTE:
1. DNC - Do Not Connect.
PBGA (BB256-1, order code: BB)
TOP VIEW
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
provides a user programmable almost full flag for all 8 queues and when a
respectivequeueisselectedonthewriteport,thealmostfullflagprovidesstatus
for that queue. Conversely, the read port has an output valid flag, providing
statusofthedatabeingreadfromthequeueselectedonthereadport.Aswell
astheoutputvalidflagthedeviceprovidesadedicatedalmostemptyflag.This
almostemptyflagissimilartothealmostemptyflagofaconventionalIDTFIFO.
Thedeviceprovidesauserprogrammablealmostemptyflagforall8queues
andwhenarespectivequeueisselectedonthereadport,thealmostemptyflag
providesstatusforthatqueue.
DETAILEDDESCRIPTION
MULTI-QUEUE STRUCTURE
The IDT multi-queue flow-control device has a single data input port and
singledataoutputportwithupto8FIFOqueuesinparallelbufferingbetween
thetwoports.Theusercansetupbetween1and8Queueswithinthedevice.
Thesequeuescanbeconfiguredtoutilizethetotalavailablememory,providing
theuserwithfullflexibilityandabilitytoconfigurethequeuestobevariousdepths,
independentofoneanother.
MEMORYORGANIZATION/ALLOCATION
PROGRAMMABLE FLAG BUSSES
Thememoryisorganizedintowhatisknownas“blocks”,eachblockbeing
512x18or1,024x9bits.Whentheuserisconfiguringthenumberofqueues
andindividualqueue sizes the usermustallocate the memorytorespective
queues,inunitsofblocks,thatis,asinglequeuecanbemadeupfrom0tom
blocks,wheremisthetotalnumberofblocksavailablewithinadevice.Alsothe
totalsize of anygiven queue mustbe in increments of 512 x 18or1,024 x 9.
FortheIDT72V51333,IDT72V51343andIDT72V51353theTotalAvailable
Memoryis64,128and256blocksrespectively(ablockbeing512x18or1,024
x9).Ifanyportisconfiguredforx18buswidth,ablocksizeis512x18.Ifboth
thewriteandreadportsareconfiguredforx9buswidth,ablocksizeis1,024
x9.Queuescanbebuiltfromtheseblockstomakeanysizequeuedesiredand
any number of queues desired.
Inadditiontothesededicatedflags,full&almostfullonthewriteportandoutput
valid&almostemptyonthereadport,therearetwoflagstatusbusses.Analmost
fullflagstatusbusisprovided,thisbusis8bitswide.Also,analmostemptyflag
statusbusisprovided,againthisbusis8bitswide.Thepurposeoftheseflag
bussesistoprovidetheuserwithameansbywhichtomonitorthedatalevels
withinqueuesthatmaynotbeselectedonthewriteorreadport.Asmentioned,
thedeviceprovidesalmostfullandalmostemptyregisters(programmableby
the user) for each of the 8 queues in the device.
The4bitPAEnand4bitPAFnbussesprovideadiscretestatusoftheAlmost
EmptyandAlmostFullconditionsofall8queue's.Ifthedeviceisprogrammed
for less than 8 queue's, then there will be a corresponding number of active
outputs onthePAEnandPAFnbusses.
Theflagbussescanprovideacontinuousstatusofallqueues.Ifdevicesare
connectedinexpansionmodetheindividualflagbussescanbeleftinadiscrete
form,providingconstantstatusofallqueues,orthebussesofindividualdevices
canbe connectedtogethertoproduce a single bus of8bits. The device can
then operate in a "Polled" or "Direct" mode.
Whenoperatinginpolledmodetheflagbusprovidesstatusofeachdevice
sequentially,thatis,oneachrisingedgeofaclocktheflagbusisupdatedtoshow
thestatusofeachdeviceinorder.Therisingedgeofthewriteclockwillupdate
theAlmostFullbusandarisingedgeonthereadclockwillupdatetheAlmost
Emptybus.
Whenoperatingindirectmodethedevicedrivingtheflagbusisselectedby
theuser.Theuseraddresses thedevicethatwilltakecontrolofarespective
flagbus, these PAFnand PAEnflagbusses operatingindependentlyofone
another.AddressingoftheAlmostFullflagbus is doneviathewriteportand
addressingoftheAlmostEmptyflagbus is doneviathereadport.
BUS WIDTHS
Theinputportiscommontoallqueueswithinthedevice,asistheoutputport.
ThedeviceprovidestheuserwithBusMatchingoptionssuchthattheinputport
andoutputportcanbeeitherx9orx18bitswide,thereadandwriteportwidths
beingsetindependentlyofoneanother.Becausetheportsarecommontoall
queuesthewidthofthequeuesisnotindividuallyset,sothattheinputwidthof
all queues are equal and the output width of all queues are equal.
WRITING TO & READING FROM THE MULTI-QUEUE
Databeingwrittenintothedeviceviatheinputportisdirectedtoadiscrete
queueviathewritequeueselectaddressinputs.Conversely,databeingread
fromthedevicereadportisreadfromaqueueselectedviathereadqueueselect
addressinputs.Datacanbesimultaneouslywrittenintoandreadfromthesame
queueordifferentqueues.Onceaqueueisselectedfordatawritesorreads,
the writing and reading operation is performed in the same manner as
conventionalIDTsynchronous FIFO,utilizingclocks andenables,thereis a
singleclockandenableperport.Whenaspecificqueueisaddressedonthe
writeport,dataplacedonthedatainputsiswrittentothatqueuesequentially
basedontherisingedgeofawriteclockprovidedsetupandholdtimesaremet.
Conversely,dataisreadontotheoutputportafteranaccesstimefromarising
edge on a read clock.
Theoperationofthewriteportiscomparabletothefunctionofaconventional
FIFOoperatinginstandardIDTmode.Writeoperationscanbeperformedon
thewriteportprovidedthatthequeuecurrentlyselectedisnotfull,afullflagoutput
provides status of the selected queue. The operation of the read port is
comparabletothefunctionofaconventionalFIFOoperatinginFWFTmode.
Whenaqueueis selectedontheoutputport,thenextwordinthatqueuewill
automaticallyfallthroughtotheoutputregister.Allsubsequentwordsfromthat
queue require an enabled read cycle. Data cannot be read from a selected
queueifthatqueueisempty,thereadportprovidesanOutputValidflagindicating
whendata readoutis valid. Ifthe userswitches toa queue thatis empty, the
lastwordfromtheprevious queuewillremainontheoutputregister.
Asmentioned,thewriteporthasafullflag,providingfullstatusoftheselected
queue.Alongwiththefullflagadedicatedalmostfullflagisprovided,thisalmost
fullflagissimilartothealmostfullflagofaconventionalIDTFIFO.Thedevice
EXPANSION
Expansionofmulti-queuedevicesisalsopossible,upto8devicescanbe
connectedinaparallelfashionprovidingthepossibilityofbothdepthexpansion
or queue expansion. Depth Expansion means expanding the depths of
individual queues. Queue expansion means increasing the total number of
queuesavailable.Depthexpansionispossiblebyvirtueofthefactthatmore
memoryblocks withinamulti-queuedevicecanbeallocatedtoincreasethe
depth of a queue. For example, depth expansion of 8 devices provides the
possibilityof8queuesof32Kx18deepwithintheIDT72V51333,64Kx18deep
withintheIDT72V51343and128Kx18deepwithintheIDT72V51353,each
queuebeingsetupwithinasingledeviceutilizingallmemoryblocksavailable
toproduceasinglequeue. This is thedeepestqueuethatcansetupwithina
device.
For queue expansion of the 8 queue device, a maximum number of 64 (8
x8)queuesmaybesetup,eachqueuebeing16Kx18or32Kx9deep,ifless
queuesaresetup,thenmorememoryblockswillbeavailabletoincreasequeue
depthsifdesired.Whenconnectingmulti-queuedevicesinexpansionmodeall
respectiveinputpins(data&control)andoutputpins(data& flags),shouldbe
“connected”togetherbetweenindividualdevices.
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINDESCRIPTIONS
Symbol
Name
I/OTYPE
Description
D[17:0]
Din
DataInputBus
LVTTL These are the 18data inputpins. Data is writtenintothe device via these inputpins onthe rising edge
INPUT ofWCLKprovidedthatWENisLOW.Duetobusmatchingnotallinputsmaybeused,anyunusedinputs
shouldbetiedLOW.
DF(1)
DefaultFlag
DefaultMode
LVTTL Iftheuserrequiresdefaultprogrammingofthemulti-queuedevice,thispinmustbesetupbeforeMaster
INPUT Resetandmustnottoggleduringanydeviceoperation.Thestateofthisinputatmasterresetdetermines
the value of the PAE/PAF flag offsets. If DF is LOW the value is 8, if DF is HIGH the value is 128.
(1)
DFM
LVTTL The multi-queue device requires programmingaftermasterreset. The usercandothis seriallyvia the
INPUT serialport,ortheusercanusethedefaultmethod.IfDFMisLOWatmasterresetthenserialmodewillbe
selected,ifHIGHthendefaultmodeisselected.
ESTR
PAEn Flag Bus
Strobe
LVTTL IfdirectoperationofthePAEnbushasbeenselected,theESTRinputisusedinconjunctionwithRCLK
INPUT andtheRDADDbustoselectadeviceforitsqueuestobeplacedontothePAEnbusoutputs.Adevice
addressed via the RDADD bus is selected on the rising edge of RCLK provided that ESTR is HIGH. If
Polledoperationshasbeenselected,ESTRshouldbetiedinactive,LOW.Note,thataPAEnflagbus
selectioncannotbemade,(ESTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
andSENO has gone LOW.
ESYNC
EXI
PAEn Bus Sync
LVTTL ESYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAEnbus
OUTPUT duringPolledoperationofthePAEnbus.DuringPolledoperationeachdevicesqueuestatusflagsare
loadedontothePAEnbusoutputssequentiallybasedonRCLK.ThefirstRCLKrisingedgeloadsdevice1
ontoPAEn,thesecondRCLKrisingedgeloadsdevice2andsoon.DuringtheRCLKcyclethataselected
device is placed on to the PAEn bus, the ESYNC output will be HIGH.
PAEnBus
ExpansionIn
LVTTL The EXIinputis usedwhenmulti-queue devices are connectedinexpansionmode andPolledPAEn
INPUT bus operationhas beenselected. EXIofdevice ‘N’connects directlytoEXOofdevice ‘N-1’. The EXI
receives a tokenfromthe previous device ina chain. Insingle device mode the EXIinputmustbe tied
LOWifthe PAEnbus is operatedindirectmode. Ifthe PAEnbus is operatedinpolledmode the EXI
inputmustbeconnectedtotheEXOoutputofthesamedevice.InexpansionmodetheEXIofthefirst
deviceshouldbetiedLOW,whendirectmodeisselected.
EXO
PAEnBus
ExpansionOut
LVTTL EXOisanoutputthatisusedwhenmulti-queuedevicesareconnectedinexpansionmodeandPolledPAEn
OUTPUT busoperationhasbeenselected.EXOofdevice‘N’connectsdirectlytoEXIofdevice‘N+1’.Thispinpulses
HIGHwhendevice Nplaces its PAE status ontothe PAEnbus withrespecttoRCLK. This pulse
(token)isthenpassedontothenextdeviceinthechain‘N+1’andonthenextRCLKrisingedgethefirst
quadrantofdevice N+1willbe loadedontothe PAEnbus. This continues throughthe chainandEXO
ofthelastdeviceisthenloopedbacktoEXIofthefirstdevice.TheESYNCoutputofeachdeviceinthe
chainprovidessynchronizationtotheuserofthisloopingevent.
FF
Full Flag
LVTTL Thispinprovidesthefullflagoutputfortheactivequeue,thatis,thequeueselectedontheinputportfor
OUTPUT write operations, (selectedvia WCLK, WRADDbus andWADEN). Onthe WCLKcycle aftera queue
selection,thisflagwillshowthestatusofthenewlyselectedqueue.Datacanbewrittentothisqueueon
thenextcycleprovidedFF is HIGH.This flaghas High-Impedancecapability,this is importantduring
expansionofdevices,whentheFFflagoutputofupto8devicesmaybeconnectedtogetheronacommon
line.ThedevicewithaqueueselectedtakescontroloftheFFbus,allotherdevicesplacetheirFFoutput
intoHigh-Impedance.Whenaqueueselectionismadeonthewriteportthisoutputwillswitchfrom
High-ImpedancecontrolonthenextWCLKcycle.ThisflagissynchronizedtoWCLK.
(1)
FM
Flag Mode
LVTTL Thispinissetupbeforeamasterresetandmustnottoggleduringanydeviceoperation.Thestateofthe
INPUT FMpinduringMasterResetwilldeterminewhetherthePAFnandPAEnflagbussesoperateineitherPolled
orDirectmode.Ifthis pinis HIGHthemodeis Polled,ifLOWthenitwillbeDirect.
FSTR
PAFn Flag Bus
Strobe
LVTTL IfdirectoperationofthePAFnbushasbeenselected,theFSTRinputisusedinconjunctionwithWCLK
INPUT andtheWRADDbustoselectadeviceforitsqueuestobeplacedontothePAFnbusoutputs.Adevice
addressedviatheWRADDbus is selectedontherisingedgeofWCLKprovidedthatFSTRis HIGH.If
Polledoperations has beenselected,FSTRshouldbetiedinactive,LOW.Note,thataPAFnflagbus
selectioncannotbemade,(FSTRmustNOTgoactive)untilprogrammingoftheparthasbeencompleted
andSENO has gone LOW.
FSYNC
PAFn Bus Sync
LVTTL FSYNCisanoutputfromthemulti-queuedevicethatprovidesasynchronizingpulseforthePAFnbus
OUTPUT duringPolledoperationofthePAFnbus.DuringPolledoperationeachquadrantofqueuestatusflagsis
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
FSYNC
(Continued)
PAFn Bus Sync
LVTTL loadedontothe PAFnbus outputs sequentiallybasedonWCLK.ThefirstWCLKrisingedgeloads
OUTPUT device1ontothePAFnbusoutputs,thesecondWCLKrisingedgeloadsdevice2andsoon.Duringthe
WCLKcycle thata selecteddevice is placedontothe PAFnbus, the FSYNCoutputwillbe HIGH.
FXI
PAFnBus
ExpansionIn
LVTTL The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn
INPUT bus operation has been selected. FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receives a tokenfromthe previous device ina chain. Insingle device mode the FXIinputmustbe tied
LOWifthePAFnbusisoperatedindirectmode.IfthePAFnbusisoperatedinpolledmodetheFXIinput
mustbeconnectedtotheFXOoutputofthesamedevice.InexpansionmodetheFXIofthefirstdevice
shouldbetiedLOW,whendirectmodeisselected.
FXO
PAFnBus
ExpansionOut
LVTTL FXOisanoutputthatisusedwhenmulti-queuedevicesareconnectedinexpansionmodeandPolled
OUTPUT PAFnbusoperationhasbeenselected.FXOofdevice‘N’connectsdirectlytoFXIofdevice‘N+1’.This
pinpulsesHIGHwhendeviceNplacesitsPAFstatusontothePAFnbuswithrespecttoWCLK.Thispulse
(token)isthenpassedontothenextdeviceinthechain‘N+1’andonthenextWCLKrisingedgethefirst
quadrantofdevice N+1willbe loadedontothe PAFnbus. This continues throughthe chainandFXO
ofthelastdeviceisthenloopedbacktoFXIofthefirstdevice.TheFSYNCoutputofeachdeviceinthe
chainprovidessynchronizationtotheuserofthisloopingevent.
(1)
ID[2:0]
Device ID Pins
LVTTL Forthe8Qmulti-queuedevicetheWRADDaddressbusis6bitsandRDADDaddressbusis7bitswide.
INPUT Whenaqueueselectiontakesplacethe3MSb’softhisaddressbusareusedtoaddressthespecificdevice
(theLSb’sareusedtoaddressthequeuewithinthatdevice).Duringwrite/readoperationsthe3MSb’s
oftheaddressarecomparedtothedeviceIDpins.Thefirstdeviceinachainofmulti-queue’s(connected
inexpansionmode),maybesetupas‘000’,thesecondas‘001’andsoonthroughtodevice8whichis
‘111’,howevertheIDdoesnothavetomatchthedeviceorder.Insingledevicemodethesepinsshould
besetupas‘000’andthe3MSb’softheWRADDandRDADDaddressbussesshouldbetiedLOW.The
ID[2:0]inputssetuparespectivedevicesIDduringmasterreset.TheseIDpinsmustnottoggleduring
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
(1)
IW
InputWidth
LVTTL IWselectsthebuswidthforthedatainputbus.IfIWisLOWduringaMasterResetthenthebuswidth
INPUT is x18, if HIGH then it is x9.
(1)
MAST
MasterDevice
LVTTL ThestateofthisinputatMasterResetdetermineswhetheragivendevice(withinachainofdevices),isthe
INPUT MasterdeviceoraSlave.IfthispinisHIGH,thedeviceisthemaster,ifitisLOWthenitisaSlave.Themaster
deviceisthefirsttotakecontrolofalloutputsafteramasterreset,allslavedevicesgotoHigh-Impedance,
preventingbuscontention.Ifamulti-queuedeviceisbeingusedinsingledevicemode,thispinmust
be setHIGH.
MRS
OE
MasterReset
OutputEnable
LVTTL AmasterresetisperformedbytakingMRSfromHIGHtoLOW,toHIGH.Deviceprogrammingisrequired
INPUT aftermasterreset.
LVTTL TheOutputenablesignalisanAsynchronoussignalusedtoprovidethree-statecontrolofthemulti-queue
INPUT dataoutputbus,Qout.Ifadevicehasbeenconfiguredasa“Master”device,theQoutdataoutputswill
beinaLowImpedanceconditioniftheOEinputisLOW.IfOEisHIGHthentheQoutdataoutputswillbe
inHighImpedance.Ifadeviceisconfigureda“Slave”device,thentheQoutdataoutputswillalwaysbe
inHighImpedanceuntilthatdevicehasbeenselectedontheReadPort,atwhichpointOEprovidesthree-
stateofthatrespectivedevice.
OV
OutputValidFlag
LVTTL Thisoutputflagprovidesoutputvalidstatusforthedatawordpresentonthemulti-queueflow-controldevice
OUTPUT dataoutputport,Qout.Thisflagistherefore,2-stagedelayedtomatchthedataoutputpathdelay.That
is,thereisa2RCLKcycledelayfromthetimeagivenqueueisselectedforreads,tothetimetheOVflag
representsthedatainthatrespectivequeue.Whenaselectedqueueonthereadportisreadtoempty,
the OVflagwillgoHIGH, indicatingthatdata onthe outputbus is notvalid. TheOV flagalsohas High-
Impedancecapability, requiredwhenmultipledevicesareusedandtheOVflagsaretiedtogether.
(1)
OW
OutputWidth
LVTTL OWselectsthebuswidthforthedataoutputbus.IfOWisLOWduringaMasterResetthenthebuswidth
INPUT is x18, if HIGH then it is x9.
PAE
Programmable
Almost-EmptyFlag
LVTTL ThispinprovidestheAlmost-Emptyflagstatusforthequeuethathasbeenselectedontheoutputport
OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
queueisalmost-empty.ThisflagoutputmaybeduplicatedononeofthePAEnbuslines.Thisflagis
synchronizedtoRCLK.
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
PAEn
Programmable
LVTTL Onthe8QdevicethePAEnbusis8bitswide.ThisoutputbusprovidesPAEstatusofall8queues,withina
Almost-EmptyFlagBus OUTPUT selecteddevice.Duringqueueread/writeoperationstheseoutputsprovideprogrammableemptyflag
statusineitherdirectorpolledmode.Themodeofflagoperationisdeterminedduringmasterresetvia
thestateoftheFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansion
ofmulti-queuedevices.DuringdirectoperationthePAEnbusisupdatedtoshowthePAEstatusofqueues
within a selected device. Selection is made using RCLK, ESTR and Flag Bus RDADD. During Polled
operationthePAEnbusisloadedwiththePAEstatusofmulti-queueflow-controldevicessequentiallybased
on the rising edge of RCLK.
PAF
Programmable
Almost-FullFlag
LVTTL ThispinprovidestheAlmost-Fullflagstatusforthequeuethathasbeenselectedontheinputportfor
OUTPUT writeoperations,(selectedviaWCLK,WRADDandWADEN).ThispinisLOWwhentheselectedFIFO
queueis almost-full.This flagoutputmaybeduplicatedononeofthePAFnbuslines.Thisflagis
synchronizedtoWCLK.
PAFn
Programmable
LVTTL Onthe8QdevicethePAFnbusis8bitswide.ThisoutputbusprovidesPAFstatusofall8queues,withina
Almost-FullFlagBus OUTPUT selecteddevice.Duringqueueread/writeoperationstheseoutputsprovideprogrammablefullflagstatus,
ineitherdirectorpolledmode.Themodeofflagoperationisdeterminedduringmasterresetviathestate
oftheFMinput.ThisflagbusiscapableofHigh-Impedancestate,thisisimportantduringexpansionof
multi-queuedevices.DuringdirectoperationthePAFnbusisupdatedtoshowthePAFstatusofaqueues
withinaselecteddevice.SelectionismadeusingWCLK,FSTR,WRADDandWADEN.DuringPolled
operationthePAFnbusisloadedwiththePAFstatusofmulti-queueflow-controldevicessequentially
basedonthe risingedge ofWCLK.
PRS
PartialReset
LVTTL APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial
INPUT Resetcanbe performedona queue, thatqueue mustbe selectedonboththe write portandreadport
2clockcycles beforetheresetis performed.APartialResetis thenperformedbytakingPRS LOWfor
one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to
thefirstmemorylocation,noneofthedevicesconfigurationwillbechanged.
Q[17:0]
Qout
DataOutputBus
LVTTL Thesearethe18dataoutputpins.Dataisreadoutofthedeviceviatheseoutputpinsontherisingedge
OUTPUT ofRCLKprovidedthat REN is LOW, OEis LOWandthe queue is selected. Due tobus matchingnot
alloutputs maybeused,anyunusedoutputs shouldnotbeconnected.
RADEN
ReadAddress Enable LVTTL The RADENinputis usedinconjunctionwithRCLKandthe RDADDaddress bus toselecta queue to
INPUT bereadfrom.AqueueaddressedviatheRDADDbusisselectedontherisingedgeofRCLKprovided
thatRADENisHIGH.RADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).RADEN
shouldnotbepermanentlytiedHIGH.RADENcannotbeHIGHforthesameRCLKcycleasESTR.Note,
thatareadqueueselectioncannotbemade,(RADENmustNOTgoactive)untilprogrammingofthepart
has beencompletedandSENO has goneLOW.
RCLK
ReadClock
LVTTL Whenenabledby REN, the risingedge ofRCLKreads data fromthe selectedqueue via the output
INPUT bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
whileRADENisHIGH.ArisingedgeofRCLKinconjunctionwithESTRandRDADDwillalsoselectthe
devicetobeplacedonthePAEnbusduringdirectflagoperation.DuringpolledflagoperationthePAEn
bus is cycledwithrespecttoRCLKandtheESYNCsignalis synchronizedtoRCLK.ThePAE andOV
outputsareallsynchronizedtoRCLK.DuringdeviceexpansiontheEXOandEXIsignalsarebasedon
RCLK.RCLKmustbecontinuous andfree-running.
RDADD
[6:0]
Read Address Bus
LVTTL For the 8Q device the RDADD bus is 7 bits. The RDADD bus is a dual purpose address bus. The first
INPUT functionofRDADDistoselectaqueuetobereadfrom.Theleastsignificant3bitsofthebus,RDADD[2:0]
areusedtoaddress1of8possiblequeueswithinamulti-queuedevice.Addresspin,RDADD[3]provides
the user with a Null-Q address. If the user does not wish to address one of the 8 queues, a Null-Q can
beaddressedusingthispin.TheNull-Qoperationisdiscussedinmoredetaillater.Themostsignificant
3bits,RDADD[6:4]areusedtoselect1of8possiblemulti-queuedevices thatmaybeconnectedin
expansionmode.These3MSB’swilladdressadevicewiththematchingIDcode.Theaddresspresent
ontheRDADDbuswillbeselectedonarisingedgeofRCLKprovidedthatRADENisHIGH,(note,that
data can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge).
On the next rising RCLK edge after a read queue select, a data word from the previous queue will be
placedontotheoutputs,Qout,regardlessoftheRENinput.TwoRCLKrisingedgesafterreadqueueselect,
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
RDADD
[6:0]
ReadAddress Bus
LVTTL datawillbeplacedontotheQoutoutputsfromthenewlyselectedqueue,regardlessofRENduetothe
INPUT firstwordfallthrougheffect.
(Continued)
ThesecondfunctionoftheRDADDbusistoselectthedeviceofqueuestobeloadedontothePAEnbus
duringstrobedflagmode.Themostsignificant3bits,RDADD[6:4]areagainusedtoselect1of8possible
multi-queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsRDADD[3:0]aredon’t care
duringdevice selection. The device address presentonthe RDADDbus willbe selectedonthe rising
edgeofRCLKprovidedthatESTRisHIGH,(note,thatdatacanbeplacedontotheQoutbus,readfrom
the previouslyselectedqueue onthis RCLKedge). Please refertoTable 2fordetails onRDADDbus.
REN
ReadEnable
LVTTL The REN input enables read operations from a selected queue based on a rising edge of RCLK. A
INPUT queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless
ofthestateofREN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond
RCLKcycle afterqueue selectionregardless ofREN due tothe FWFToperation. Areadenable is not
required to cycle the PAEn bus (in polled mode) or to select the device , (in direct mode).
SCLK
SerialClock
LVTTL Ifserialprogrammingofthemulti-queuedevicehasbeenselectedduringmasterreset,theSCLKinput
INPUT clockstheserialdatathroughthemulti-queuedevice.DatasetupontheSIinputisloadedintothedevice
ontherisingedgeofSCLKprovidedthatSENIisenabled,LOW.Whenexpansionofdevicesisperformed
theSCLKofalldevices shouldbeconnectedtothesamesource.
SENI
SerialInputEnable
LVTTL Duringserialprogrammingofamulti-queuedevice,dataloadedontotheSIinputwillbeclockedintothe
INPUT part(via a risingedge ofSCLK), providedthe SENI inputofthatdevice is LOW. Ifmultiple devices are
cascaded,theSENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
loadingofagivendeviceiscomplete,itsSENOoutputgoesLOW,allowingthenextdeviceinthechain
tobeprogrammed(SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
inputofthe masterdevice (orsingle device), shouldbe controlledbythe user.
SENO
SerialOutputEnable LVTTL Thisoutputisusedtoindicatethatserialprogrammingordefaultprogrammingofthemulti-queuedevice
OUTPUT hasbeencompleted.SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO
willgoLOWafterprogrammingprovidedSENIisLOW,onceSENIistakenHIGHagain,SENOwillalso
goHIGH.WhentheSENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.
Ifmultipledevicesarecascadedandserialprogrammingofthedeviceswillbeused,theSENOoutput
shouldbeconnectedtotheSENIinputofthenextdeviceinthechain.Whenserialprogrammingofthe
firstdeviceiscomplete,SENO willgoLOW,therebytakingtheSENIinputofthenextdeviceLOWand
soonthroughoutthe chain. Whena givendevice inthe chainis fullyprogrammedtheSENO output
essentiallyfollowstheSENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.
WhenthisoutputgoesLOW,serialloadingofalldeviceshasbeencompleted.
SI
SerialIn
LVTTL Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.
INPUT Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
modetheserialdatainputisloadedintothefirstdeviceinachain.WhenthatdeviceisloadedanditsSENO
hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connectstotheSIpinofthesecondandsoon.Themulti-queuedevicesetupregistersareshiftregisters.
SO
SerialOut
LVTTL Thisoutputisusedinexpansionmodeandallowsserialdatatobepassedthroughdevicesinthechain
OUTPUT tocompleteprogrammingofalldevices.TheSIofadeviceconnectstoSOofthepreviousdeviceinthe
chain. The SOofthe finaldevice ina chainshouldnotbe connected.
(2)
TCK
JTAGClock
LVTTL ClockinputforJTAGfunction.Oneoffourterminals requiredbyIEEEStandard1149.1-1990.Test
INPUT operationsofthedevicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedge
ofTCKandoutputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneeds
tobe tiedtoGND.
(2)
TDI
JTAGTestData
Input
LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
INPUT operation,testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,
IDRegisterandBypass Register.Aninternalpull-upresistorforces TDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData
Output
LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
OUTPUT operation,testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstruction
Register,IDRegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whilein
SHIFT-DR and SHIFT-IR controller states.
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/OTYPE
Description
TMS(2)
JTAGModeSelect
LVTTL TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthe
INPUT devicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST
JTAGReset
LVTTL TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
INPUT resetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHforfiveTCKcycles.
IftheTAPcontrollerisnotproperlyresetthentheoutputswillalwaysbeinhigh-impedance.IftheJTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure
properqueue operation. Ifthe JTAGfunctionis notusedthenthis signalneeds tobe tiedtoGND. An
internalpull-upresistorforcesTRSTHIGHifleftunconnected.
WADEN
WCLK
WriteAddressEnable LVTTL TheWADENinputisusedinconjunctionwithWCLKandtheWRADDaddressbustoselectaqueueto
INPUT bewritteninto.AqueueaddressedviatheWRADDbusisselectedontherisingedgeofWCLKprovided
thatWADENisHIGH.WADENshouldbeasserted(HIGH)onlyduringaqueuechangecycle(s).WADEN
shouldnotbepermanentlytiedHIGH.WADENcannotbeHIGHforthesameWCLKcycleasFSTR.Note,
thatawritequeueselectioncannotbemade,(WADENmustNOTgoactive)untilprogrammingofthepart
has beencompletedandSENO has goneLOW.
WriteClock
LVTTL WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheselectedqueueviatheinputbus,
INPUT Din.ThequeuetobewrittentoisselectedviatheWRADDaddressbusandarisingedgeofWCLKwhile
WADENisHIGH.ArisingedgeofWCLKinconjunctionwithFSTRandWRADDwillalsoselectthedevice
tobeplacedonthePAFnbusduringdirectflagoperation.Duringpolledflagoperationthe PAFnbusis
cycledwithrespecttoWCLKandtheFSYNCsignalissynchronizedtoWCLK.ThePAFn,PAFandFF
outputsareallsynchronizedtoWCLK.DuringdeviceexpansiontheFXOandFXIsignalsarebasedon
WCLK.TheWCLKmustbecontinuousandfree-running.
WEN
WriteEnable
LVTTL TheWENinputenableswriteoperationstoaselectedqueuebasedonarisingedgeofWCLK.Aqueue
INPUT tobe writtentocanbe selectedvia WCLK, WADENandthe WRADDaddress bus regardless ofthe
stateofWEN.DatapresentonDincanbewrittentoanewlyselectedqueueonthesecondWCLKcycle
afterqueueselectionprovidedthatWENisLOW.AwriteenableisnotrequiredtocyclethePAFnbus(in
polledmode)ortoselectthe device , (indirectmode).
WRADD
[5:0]
WriteAddressBus
LVTTL Forthe 8Qdevice the WRADDbus is 6bits. The WRADDbus is a dualpurpose address bus. The first
INPUT functionofWRADDistoselectaqueuetobewrittento.Theleastsignificant3bitsofthebus,WRADD[2:0]
areusedtoaddress1of8possiblequeueswithinamulti-queuedevice.Themostsignificant3bits,
WRADD[5:3]areusedtoselect1of8possiblemulti-queuedevicesthatmaybeconnectedinexpansion
mode.These3MSB’swilladdressadevicewiththematchingIDcode.TheaddresspresentontheWRADD
buswillbeselectedonarisingedgeofWCLKprovidedthatWADENisHIGH,(note,thatdatapresenton
theDinbuscanbewrittenintothepreviouslyselectedqueueonthisWCLKedgeandonthenextrising
WCLKalso,providingthatWENisLOW).TwoWCLKrisingedgesafterwritequeueselect,datacanbe
writtenintothenewlyselectedqueue.
ThesecondfunctionoftheWRADDbusistoselectthedeviceofqueuestobeloadedontothePAFnbus
duringstrobedflagmode.Themostsignificant3bits,WRADD[6:3]areagainusedtoselect1of8possible
multi-queuedevicesthatmaybeconnectedinexpansionmode.AddressbitsWRADD[2:0]aredon’tcare
duringdevice selection. The device address presentonthe WRADDbus willbe selectedonthe rising
edgeofWCLKprovidedthatFSTRisHIGH,(note,thatdatacanbewrittenintothepreviouslyselected
queue on this WCLK edge). Please refer to Table 1 for details on the WRADD bus.
VCC
+3.3VSupply
GroundPin
Power These are VCC power supply pins and must all be connected to a +3.3V supply rail.
Ground These are Ground pins and must all be connected to the GND supply rail.
GND
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 44-48 and Figures 27-29.
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
ABSOLUTEMAXIMUMRATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Com'l & Ind'l
Unit
Symbol
Parameter
SupplyVoltage(Com'l/Ind'l)
Min. Typ.
Max.
3.45
0
Unit
V
VTERM
TerminalVoltage
with respect to GND
–0.5to+4.5
V
(1)
VCC
3.15
0
3.3
0
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
GND SupplyVoltage(Com'l/Ind'l)
V
VIH
VIL
TA
InputHighVoltage(Com'l/Ind'l)
InputLowVoltage(Com'l/Ind'l)
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
2.0
—
0
—
—
—
—
VCC+0.3
0.8
V
NOTE:
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
+70
°C
°C
TA
-40
+85
NOTE:
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant)
Symbol
Parameter
Min.
Max.
Unit
(1)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–10
–10
2.4
—
10
10
µA
µA
V
ILO(2)
VOH
Output Logic “1” Voltage, IOH = –8 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
StandbyCurrent
—
0.4
100
25
VOL
V
ICC1(3,4,5)
ICC2(3,6)
—
mA
mA
—
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. Tested with outputs open (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical ICC1 = 16 + 3.14*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
6. RCLK and WCLK, toggle at 20 MHz.
The following inputs should be pulled to GND: WRADD, RDADD, WADEN, RADEN, FSTR, ESTR, SCLK, SI, EXI, FXI and all Data Inputs.
The following inputs should be pulled to VCC: WEN, REN, SENI, PRS, MRS, TDI, TMS and TRST.
All other inputs are don't care, and should be pulled HIGH or LOW.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
AC TEST LOADS
6
5
V
CC/2
4
3
2
1
50
Ω
Z0 = 50Ω
I/O
20 30 50 80 100
Capacitance (pF)
200
5940 drw04
5940 drw04a
Figure 2a. AC Test Load
Figure 2b. Lumped Capacitive Load, Typical Derating
ACTESTCONDITIONS
InputPulseLevels
GND to 3.0V
1.5ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
1.5V
1.5V
See Figure 2a & 2b
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
V
IH
IL
OE
V
tOE &
tOLZ
tOHZ
Output
Normally
LOW
V
CC/2
V
CC/2
100mV
100mV
100mV
VOL
V
OH
Output
Normally
HIGH
100mV
VCC/2
VCC/2
5940 drw04b
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72V51333L6
IDT72V51343L6
IDT72V51553L6
IDT72V51333L7-5
IDT72V51343L7-5
IDT72V51553L7-5
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency (WCLK & RCLK)
DataAccessTime
—
0.6
6
166
3.7
—
—
—
—
—
—
—
—
—
—
—
—
3.7
3.7
3.7
10
—
0.6
7.5
3.5
3.5
2.0
0.5
2.0
0.5
10
133
4
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tA
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
—
—
—
—
—
—
—
—
—
—
—
—
4
Clock High Time
2.7
2.7
2
Clock Low Time
DataSetupTime
tDH
DataHoldTime
0.5
2
tENS
tENH
tRS
EnableSetupTime
EnableHoldTime
0.5
10
ResetPulseWidth
tRSS
tRSR
tPRSS
tPRSH
ResetSetupTime
15
15
ResetRecoveryTime
10
10
PartialResetSetup
2.0
0.5
0.6
0.6
0.6
—
100
45
2.5
0.5
0.6
0.6
0.6
—
100
45
PartialResetHold
(2)
tOLZ(OE-Qn)
OutputEnabletoOutputinLow-Impedance
OutputEnabletoOutputinHigh-Impedance
OutputEnabletoDataOutputValid
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
(2)
tOHZ
4
tOE
4
fC
10
—
—
—
—
—
—
—
20
20
4
tSCLK
tSCKH
tSCKL
tSDS
—
—
—
—
—
—
—
20
Serial Clock High
Serial Clock Low
45
45
SerialDataInSetup
20
20
tSDH
tSENS
tSENH
tSDO
tSENO
tSDOP
tSENOP
tPCWQ
tPCRQ
tAS
Serial Data In Hold
1.2
20
1.2
20
SerialEnableSetup
SerialEnableHold
1.2
—
—
1.5
1.5
20
1.2
—
—
1.5
1.5
20
SCLK to Serial Data Out
SCLK to Serial Enable Out
SerialDataOutPropagationDelay
SerialEnablePropagationDelay
ProgrammingCompletetoWriteQueueSelection
ProgrammingCompletetoReadQueueSelection
AddressSetup
20
3.7
3.7
—
—
—
—
3.7
3.7
—
—
—
—
3.7
3.7
3.7
3.7
4
—
—
—
5
20
20
2.5
1
3.0
1
tAH
Address Hold
tWFF
tROV
tSTS
Write Clock to Full Flag
ReadClocktoOutputValid
StrobeSetup
—
—
2
—
—
2
5
—
—
—
—
4
tSTH
tQS
StrobeHold
0.5
2
0.5
2.5
0.5
0.6
0.6
0.6
0.6
QueueSetup
tQH
QueueHold
0.5
0.6
0.6
0.6
0.6
tWAF
tRAE
tPAF
tPAE
WCLK to PAF flag
RCLK to PAE flag
Write ClocktoSynchronous Almost-FullFlagBus
Read Clock to Synchronous Almost-Empty Flag Bus
4
4
4
NOTES:
1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order.
2. Values guaranteed by design, not currently tested.
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
ACELECTRICALCHARACTERISTICS(CONTINUED)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = 40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com'l & Ind'l(1)
IDT72V51333L6
IDT72V51343L6
IDT72V51553L6
IDT72V51333L7-5
IDT72V51343L7-5
IDT72V51553L7-5
Symbol
Parameter
Min.
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
4.5
6
Max.
Min.
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
0.6
5.75
7.5
7.5
7.5
1.3
0.5
Max.
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
tPAELZ
RCLK to PAE Flag Bus to Low-Impedance
RCLK to PAE Flag Bus to High-Impedance
WCLK to PAF Flag Bus to Low-Impedance
WCLK to PAF Flag Bus to High-Impedance
WCLKtoFullFlagtoHigh-Impedance
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
3.7
—
—
—
—
—
—
(2)
tPAEHZ
4
(2)
tPAFLZ
4
(2)
tPAFHZ
4
(2)
tFFHZ
4
(2)
tFFLZ
WCLKtoFullFlagtoLow-Impedance
4
(2)
tOVLZ
RCLKtoOutputValidFlagtoLow-Impedance
RCLKtoOutputValidFlagtoHigh-Impedance
WCLK to PAF Bus Sync to Output
WCLK to PAF Bus Expansion to Output
RCLK to PAE Bus Sync to Output
RCLK to PAE Bus Expansion to Output
SKEW time between RCLK and WCLK for FF and OV
SKEW time between RCLK and WCLK for PAF and PAE
SKEW time between RCLK and WCLK for PAF[0:7] and PAE[0:7]
SKEW time between RCLK and WCLK for OV
ExpansionInputSetup
4
(2)
tOVHZ
4
tFSYNC
tFXO
4
4
tESYNC
tEXO
4
4
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tXIS
—
—
—
—
—
—
6
6
1.0
0.5
tXIH
ExpansionInputHold
NOTES:
1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order.
2. Values guaranteed by design, not currently tested.
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
enable),isLOW.Onceserialprogrammingofthedevicehasbeensuccessfully
completedthedevicewillindicatethisviatheSENO(serialoutputenable)going
active,LOW.Upondetectionofcompletionofprogramming,theusershould
cease all programming and take SENI inactive, HIGH. Note, SENO follows
SENIonceprogrammingofadeviceiscomplete.Therefore,SENOwillgoLOW
afterprogrammingprovidedSENI is LOW,onceSENI is takenHIGHagain,
SENO will also go HIGH. The operation of the SO output is similar, when
programmingofagivendeviceiscomplete,theSOoutputwillfollowtheSIinput.
If devices are being used in expansion mode the serial ports of devices
should be cascaded. The user can load all devices via the serial input port
controlpins,SI&SENI,ofthefirstdeviceinthechain.Again,theusermayutilize
the‘C’programtogeneratetheserialbitstream,theprogrampromptingtheuser
forthenumberofdevicestobeprogrammed.TheSENOandSO(serialout)
ofthefirstdeviceshouldbeconnectedtotheSENIandSIinputsofthesecond
devicerespectivelyandsoon,withtheSENO&SOoutputsconnectingtothe
SENI&SIinputsofalldevicesthroughthechain.Alldevicesinthechainshould
beconnectedtoacommonSCLK.Theserialoutputportofthefinaldeviceshould
be monitored by the user. When SENO of the final device goes LOW, this
indicatesthatserialprogrammingofalldeviceshasbeensuccessfullycom-
pleted.Upondetectionofcompletionofprogramming,theusershouldcease
allprogrammingandtakeSENIofthefirstdeviceinthechaininactive,HIGH.
Asmentioned,thefirstdeviceinthechainhasitsserialinputportcontrolled
bytheuser,thisisthefirstdevicetohaveitsinternalregistersseriallyloaded
bytheserialbitstream.Whenprogrammingofthisdeviceiscompleteitwilltake
itsSENOoutputLOWandbypasstheserialdataloadedontheSIinputtoits
SOoutput.Theserialinputoftheseconddeviceinthechainisnowloadedwith
thedatafromtheSOofthefirstdevice,whiletheseconddevicehasitsSENI
input LOW. This process continues through the chain until all devices are
programmedandtheSENO ofthefinaldevicegoesLOW.
FUNCTIONALDESCRIPTION
MASTERRESET
AMasterResetisperformedbytogglingtheMRSinputfromHIGHtoLOW
toHIGH.Duringamasterresetallinternalmulti-queuedevicesetupandcontrol
registersareinitializedandrequireprogrammingeitherseriallybytheuservia
theserialport,orusingthedefaultsettings.Duringamasterresetthestateof
thefollowinginputsdeterminethefunctionalityofthepart,thesepinsshouldbe
held HIGH or LOW.
FM – Flag bus Mode
IW,OW–BusMatchingoptions
MAST – Master Device
ID0, 1, 2 – Device ID
DFM–Programmingmode,serialordefault
DF – Offset value for PAE and PAF
Onceamasterresethastakenplace,thedevicemustbeprogrammedeither
seriallyorviathedefaultmethodbeforeanyread/writeoperationscanbegin.
See Figure 4, Master Reset for relevant timing.
PARTIALRESET
APartialResetisameansbywhichtheusercanresetboththereadandwrite
pointers of a single queue that has been setup within a multi-queue device.
Beforeapartialresetcantakeplaceonaqueue,therespectivequeuemustbe
selectedonboththereadportandwriteportaminimumof2RCLKand2WCLK
cyclesbeforethePRSgoesLOW.Thepartialresetisthenperformedbytoggling
thePRSinputfromHIGHtoLOWtoHIGH,maintainingtheLOWstateforatleast
oneWCLKandoneRCLKcycle.Onceapartialresethastakenplaceaminimum
of3WCLKand3RCLKcyclesmustoccurbeforeenabledwritesorreadscan
occur.
Once all serial programming has been successfully completed, normal
operations,(queueselectionsonthereadandwriteports)maybegin.When
connectedinexpansionmode,theIDT72V51333/72V51343/72V51353de-
vicesrequireatotalnumberofseriallyloadedbitsperdevicetocompleteserial
programming,(SCLKcycleswithSENIenabled),calculatedby:n[19+(Qx72)]
whereQisthenumberofqueuestheuserwishestosetupwithinthedevice,
where n is the number of devices in the chain.
APartialResetonlyresets thereadandwritepointers ofagivenqueue,a
partialresetwillnoteffecttheoverallconfigurationandsetupofthemulti-queue
deviceandits queues.
See Figure 5, PartialReset for relevant timing.
SERIAL PROGRAMMING
Themulti-queueflow-controldeviceisafullyprogrammabledevice,provid-
ingtheuserwithflexibilityinhowqueuesareconfiguredintermsofthenumber
of queues, depth of each queue and position of the PAF/PAE flags within
respectivequeues.Alluserprogrammingisdoneviatheserialportafteramaster
resethas takenplace. Internallythe multi-queue device has setupregisters
whichmustbeseriallyloaded,theseregisterscontainvaluesforeveryqueue
within the device, such as the depth and PAE/PAF offset values. The
IDT72V51333/72V51343/72V51353devices are capable ofupto8queues
andthereforecontain4setsofregistersforthesetupofeachqueue.
DuringaMasterResetiftheDFM(DefaultMode)inputisLOW,thenthedevice
willrequire serialprogrammingbythe user. Itis recommendedthatthe user
utilizea‘C’programprovidedbyIDT,thisprogramwillprompttheuserforall
informationregardingthemulti-queuesetup.Theprogramwillthengenerate
aserialbitstreamwhichshouldbeseriallyloadedintothedeviceviatheserial
port.FortheIDT72V51333/72V51343/72V51353devicestheserialprogram-
mingrequiresatotalnumberofseriallyloadedbitsperdevice,(SCLKcycles
withSENIenabled),calculatedby:19+(Qx72)whereQisthenumberofqueues
the user wishes to setup within the device. Please refer to the separate
ApplicationNote,AN-303forrecommendedcontroloftheserialprogramming
port.
See Figure 6, Serial Port Connection and Figure 7, Serial Programming
forconnectionandtiminginformation.
DEFAULTPROGRAMMING
DuringaMasterResetiftheDFM(DefaultMode)inputis HIGHthemulti-
queuedevicewillbeconfiguredfordefaultprogramming,(serialprogramming
is not permitted). Default programming provides the user with a simpler,
howeverlimitedmeansbywhichtosetupthemulti-queueflow-controldevice,
rather than using the serial programming method. The default mode will
configure a multi-queue device such that the maximum number of queues
possiblearesetup,withallofthepartsavailablememoryblocksbeingallocated
equallybetweenthequeues.ThevaluesofthePAE/PAFoffsetsisdetermined
bythe state ofthe DF(default)pinduringa masterreset.
FortheIDT72V51333/72V51343/72V51353devicesthedefaultmodewill
setup8queues,eachqueueconfiguredasfollows:FortheIDT72V51333with
x9inputandx9outputports,8,192x9.Ifoneorbothportsisx18,4,096x18.
FortheIDT72V51343withx9inputandx9outputports,16,384x9.Ifoneor
bothportsisx18,8,192x18.FortheIDT72V51353withx9inputandx9output
ports, 32,768 x 9. If one or both ports is x18, 16,384 x 18. For both devices
thevalueofthePAE/PAFoffsetsisdeterminedatmasterresetbythestateof
theDFinput.IfDFisLOWthenboththePAE&PAFoffsetwillbe8,ifHIGHthen
the value is 128.
Once the master reset is complete and MRS is HIGH, the device can be
seriallyloaded.DatapresentontheSI(serialin),inputisloadedintotheserial
port on a rising edge of SCLK (serial clock), provided that SENI (serial in
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WhenconfiguringtheIDT72V51333/72V51343/72V51353devicesinde- theWRADDbusduringarisingedgeofWCLKprovidedthatWADENisHIGH.
faultmodetheusersimplyhastoapplyWCLKcyclesafteramasterreset,until AqueuetobewrittentoneedonlybeselectedonasinglerisingedgeofWCLK.
SENOgoesLOW,thissignalsthatdefaultprogrammingiscomplete.Theseclock Allsubsequentwriteswillbewrittentothatqueueuntilanewqueueisselected.
cycles arerequiredforthedevicetoloadits internalsetupregisters.Whena Aminimumof2WCLKcyclesmustoccurbetweenqueueselectionsonthewrite
singlemulti-queueisused,thecompletionofdeviceprogrammingissignaled port.OnthenextWCLKrisingedgethewriteportdiscretefullflagwillupdate
bytheSENOoutputofadevicegoingfromHIGHtoLOW.Note,thatSENImust toshowthefullstatusofthenewlyselectedqueue.Onthesecondrisingedge
beheldLOWwhenadeviceis setupfordefaultprogrammingmode.
ofWCLK,datapresentonthedatainputbus,Dincanbewrittenintothenewly
Whenmulti-queuedevicesareconnectedinexpansionmode,theSENIof selectedqueueprovidedthatWENisLOWandthenewqueueisnotfull.The
thefirstdeviceinachaincanbeheldLOW.TheSENOofadeviceshouldconnect cycleofthequeueselectionandthenextcyclewillcontinuetowritedatapresent
totheSENIofthenextdeviceinthechain.TheSENOofthefinaldeviceisused onthedatainputbus,DinintothepreviousqueueprovidedthatWENisactive
toindicatethatdefaultprogrammingofalldevicesiscomplete.Whenthefinal LOW.
SENO goes LOW normal operations may begin. Again, all devices will be
IfWENisHIGH,inactiveforthese2clockcycles,thendatawillnotbewritten
programmedwiththeirmaximumnumberofqueuesandthememorydivided in to the previous queue.
equally between them. Please refer to Figure 8, DefaultProgramming.
Ifthenewlyselectedqueueisfullatthepointofitsselection,thenwritestothat
queue willbe prevented, a fullqueue cannotbe writteninto.
WRITE QUEUE SELECTION & WRITE OPERATION
Inthe4queuemulti-queuedevicetheWRADDaddressbusis5bitswide.
TheIDT72V51333/72V51343/72V51353multi-queueflow-controldevices Theleastsignificant2bitsareusedtoaddressoneofthe4availablequeues
haveupto8queuesthatdatacanbewrittenintoviaacommonwriteportusing withinasinglemulti-queuedevice.Themostsignificant3bitsareusedwhen
the data inputs, Din, write clock, WCLK and write enable, WEN. The queue adeviceis connectedinexpansionmode,upto8devices canbeconnected
address present on the write address bus, WRADD during a rising edge on inexpansion,eachdevicehavingits own3bitaddress.Theselecteddevice
WCLKwhilewriteaddressenable,WADENisHIGH,isthequeueselectedfor istheoneforwhichtheaddressmatchesa3bitIDcode,whichisstaticallysetup
writeoperations.ThestateofWENisdon’tcareduringthewritequeueselection on the ID pins, ID0, ID1, and ID2 of each individual device.
cycle.ThequeueselectiononlyhastobemadeonasingleWCLKcycle,this
Note,theWRADDbusisalsousedinconjunctionwithFSTR(almostfullflag
will remain the selected queue until another queue is selected, the selected busstrobe),toaddressthealmostfullflagbusofarespectivedeviceduringdirect
queueisalwaysthelastqueueselected.
modeofoperation.
Thewriteportisdesignedsuchthat100%busutilizationcanbeobtained.
RefertoTable1,forWriteAddressbusarrangement.Also,refertoFigure
ThismeansthatdatacanbewrittenintothedeviceoneveryWCLKrisingedge 9, Write Queue Select, Write Operation and Full flag Operation and Figure
includingthecyclethatanewqueueisbeingaddressed.Whenanewqueue 11,FullFlagTimingExpansionMode fortimingdiagrams.
isselectedforwriteoperationstheaddressforthatqueuemustbepresenton
TABLE 1 — WRITE ADDRESS BUS, WRADD[5:0]
Operation WCLK WADEN FSTR
WRADD[5:0]
5 4 3
Device Select
(Compared to
ID0,1,2)
2 1 0
Write Queue Address
(3 bits = 8 Queues)
Write Queue
1
0
Select
5 4 3
2 1 0
PAFn Flag Bus
Device Select
0
1
Device Select
(Compared to
ID0,1,2)
X
X
X
5940 drw05
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
READ QUEUE SELECTION & READ OPERATION
providedthatthequeueisnotempty.Atthepointofqueueselection,the2-stage
Themulti-queueflow-controldevicehasupto8queuesthatdataisreadfrom internaldatapipelineisloadedwiththelastwordfromthepreviousqueueand
viaacommonreadportusingthedataoutputs,Qout,readclock,RCLKand thenextwordfromthenewqueue,boththesewordswillfallthroughtotheoutput
readenable,REN.Anoutputenable,OEcontrolpinisalsoprovidedtoallow registerconsecutivelyuponselectionofthenewqueue.Thispipeliningeffect
High-ImpedanceselectionoftheQoutdataoutputs.Themulti-queuedevice providestheuserwith100%busutilization,butbringsaboutthepossibilitythat
readportoperatesinamodesimilarto“FirstWordFallThrough”onatraditional a “NULL” queue may be required within a multi-queue device. Null queue
IDT FIFO, but with the added feature of data output pipelining. This data operationisdiscussedinthenextsectionon.
pipeliningontheoutputportallows theusertoachieve100%bus utilization,
which is the ability to read out a data word on every rising edge of RCLK onthesameRCLKedgeandthefollowingRCLKedge,2finalreadswillbemade
regardless of whether a new queue is being selected for read operations. fromthepreviousqueue,providedthatRENisactive,LOW.OnthenextRCLK
IfanemptyqueueisselectedforreadoperationsontherisingedgeofRCLK,
Thequeueaddresspresentonthereadaddressbus,RDADDduringarising rising edge a read from the new queue will not occur, because the queue is
edge on RCLK while read address enable, RADEN is HIGH, is the queue empty.Thelastwordinthedataoutputregister(fromthepreviousqueue),will
selectedforreadoperations.Aqueuetobereadfromneedonlybeselected remainthere,buttheoutputvalidflag,OVwillgoHIGH,toindicatethatthedata
on a single rising edge of RCLK. All subsequent reads will be read from that present is no longer valid.
queueuntilanewqueueisselected.Aminimumof2RCLKcyclesmustoccur
TheRDADDbusisalsousedinconjunctionwithESTR(almostemptyflag
betweenqueueselectionsonthereadport.Datafromthenewlyselectedqueue busstrobe),toaddressthealmostemptyflagbusofarespectivedeviceduring
willbepresentontheQoutoutputsafter2RCLKcyclesplusanaccesstime, direct mode of operation. In the 8 queue multi-queue device the RDADD
providedthatOEisactive,LOW.OnthesameRCLKrisingedgethatthenew addressbusis7bitswide.Theleastsignificant3bitsareusedtoaddressone
queueis selected,datacanstillbereadfromthepreviouslyselectedqueue, of the 8 available queues within a single multi-queue device. The 4th least
providedthatRENisLOW,activeandthepreviousqueueisnotemptyonthe significantbitisusedtoselecta"Null"Queue.DuringaNull-Qselectionthe2
followingrisingedgeofRCLKawordwillbereadfromthepreviouslyselected LSB'saredon'tcare.TheNull-Qisseenasanemptyqueueonthereadport.
queueregardlessofRENduetothefallthroughoperation,(providedthequeue Null-Qoperationis discussedinmore detailina separate section. The most
isnotempty). RememberthatOEallowstheusertoplacetheQout,dataoutput significant3bitsareusedwhenadeviceisconnectedinexpansionmode,up
bus into High-Impedance and the data can be read onto the output register to8devicescanbeconnectedinexpansion,eachdevicehavingitsown3bit
regardlessofOE.
address.Theselecteddeviceistheoneforwhichtheaddressmatchesa3bit
Whenaqueueis selectedonthereadport, thenextwordavailableinthat ID code, which is statically setup on the ID pins, ID0, ID1, and ID2 of each
queue (provided that the queue is not empty), will fall through to the output individualdevice.
registerafter2RCLKcycles.Asmentioned,intheprevious2RCLKcyclesto
RefertoTable2,forReadAddressbusarrangement.Also,refertoFigures
thenewdatabeingavailable,datacanstillbereadfromthepreviousqueue, 12,14&15forreadqueueselectionandreadportoperationtimingdiagrams.
TABLE 2 — READ ADDRESS BUS, RDADD[6:0]
Operation RCLK RADEN ESTR
RDADD[6:0]
6 5 4
3
2 1 0
Read Queue
1
0
Device Select
(Compared to
ID0,1,2)
Null-Q
Read Queue Address
Select
Select Pin (3 bits = 8 Queues)
6 5 4
3
2 1 0
Flag Bus Device
Selection
0
1
Device Select
(Compared to
ID0,1,2)
X
X X X
5940 drw06
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
NULL QUEUE OPERATION (OF THE READ PORT)
FULL FLAG OPERATION
Pipeliningofdatatotheoutputportenablesthedevicetoprovide100%bus
Themulti-queueflow-controldeviceprovidesasingleFullFlagoutput,FF.
utilizationinstandardmode.Datacanbereadoutofthemulti-queueflow-control TheFFflagoutputprovidesafullstatusofthequeuecurrentlyselectedonthe
device on every RCLK cycle regardless of queue switches or other opera- writeportforwriteoperations.Internallythemulti-queueflow-controldevice
tions.Thedevicearchitectureissuchthatthepipelineisconstantlyfilledwith monitorsandmaintainsastatusofthefullconditionofallqueueswithinit,however
thenextwordsinaselectedqueuetobereadout,againproviding100%bus onlythequeuethatisselectedforwriteoperationshasitsfullstatusoutputtothe
utilization.Thistypeofarchitecturedoesassumethattheuserisconstantly FF flag.This dedicatedflagis oftenreferredtoas the“activequeuefullflag”.
switchingqueuessuchthatduringaqueueswitch,thelastdatawordrequired
fromthepreviousqueuewillfallthroughthepipelinetotheoutput.
Whenqueueswitchesarebeingmadeonthewriteport,theFFflagoutput
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
Note,thatifreadsceaseattheemptyboundaryofaqueue,thenthelastword onthecycleafteranewqueueselectionismade.Theuserthenhasafullstatus
willautomaticallyflowthroughthepipelinetotheoutput. forthenewqueueonecycleaheadoftheWCLKrisingedgethatdatacanbe
The Null-Q is selected via read port address space RDADD[3]. The writtenintothenewqueue.Thatis,anewqueuecanbeselectedonthewrite
RDADD[6:0]busshouldbeaddressedwithxxx1xxx,thisaddressistheNull-Q. portviatheWRADDbus,WADENenableandarisingedgeofWCLK.Onthe
A null queue can be selected when no further reads are required from a nextrisingedgeofWCLK,theFFflagoutputwillshowthefullstatusofthenewly
previouslyselectedqueue.Changingtoanullqueuewillcontinuetopropagate selected queue. On the second rising edge of WCLK following the queue
data in the pipeline to the previous queue’s output. The Null-Q can remain selection,datacanbewrittenintothenewlyselectedqueueprovidedthatdata
selecteduntiladatabecomesavailableinanotherqueueforreading.TheNull-Q andenablesetup&holdtimesaremet.
canbeutilizedineitherstandardorpacketmode.
Note,theFF flagwillprovidestatus ofanewlyselectedqueueoneWCLK
Note:Iftheuserswitchesthereadporttothenullqueue,thisqueueisseen cycleafterqueueselection,whichisonecyclebeforedatacanbewrittentothat
asandtreatedasanemptyqueue,thereforeafterswitchingtothenullqueue queue.Thispreventstheuserfromwritingdatatoaqueuethatisfull,(assuming
thelastwordfromthepreviousqueuewillremainintheoutputregisterandthe thataqueueswitchhas beenmadetoaqueuethatis actuallyfull).
OV flagwillgoHIGH,indicatingdata is notvalid.
TheFFflagissynchronoustotheWCLKandalltransitionsoftheFFflagoccur
TheNullqueueoperationonlyhassignificancetothereadportofthemulti- basedonarisingedgeofWCLK.Internallythemulti-queuedevicemonitorsand
queue, it is a means to force data through the pipeline to the output. Null-Q keepsarecordofthefullstatusforallqueues.Itispossiblethatthestatusofa
selectionandoperationhasnomeaningonthewriteportofthedevice.Also, FFflagmaybechanginginternallyeventhoughthatflagisnottheactivequeue
refer to Figure 16, Read Operation and Null Queue Select for diagram.
flag (selected on the write port). A queue selected on the read port may
experienceachangeofitsinternalfullflagstatusbasedonreadoperations.
SeeFigure9,WriteQueueSelect,WriteOperationandFullFlagOperation
BUS MATCHING OPERATION
BusMatchingoperationbetweentheinputportandoutputportisavailable. andFigure11, FullFlagTiminginExpansionModefortiminginformation.
Duringamasterresetofthemulti-queuethestateofthetwosetuppins,IW(Input
Width)andOW(OutputWidth)determinetheinputandoutputportbuswidths EXPANSION MODE - FULL FLAG OPERATION
as pertheselections showninTable3,“Bus MatchingSet-up”.9bitbytes or
Whenmulti-queuedevicesareconnectedinExpansionmodetheFFflags
18bitwordscanbewrittenintoandreadfromthequeues.Whenwritingtoor of all devices should be connected together, such that a system controller
readingfromthemulti-queueinabusmatchingmode,thedeviceordersdata monitoring and managing the multi-queue devices write port only looks at a
ina“LittleEndian”format.SeeFigure3,BusMatchingByteArrangementfor singleFFflag(asopposedtoadiscreteFFflagforeachdevice).ThisFFflag
details.
isonlypertinenttothequeuebeingselectedforwriteoperationsatthattime.
TheFullflagandAlmostFullflagoperationis always basedonwrites and Remember,thatwheninexpansionmodeonlyonemulti-queuedevicecanbe
readsofdatawidthsdeterminedbythewriteportwidth.Forexample,iftheinput writtentoatanymomentintime,thustheFFflagprovidesstatusoftheactive
portisx18andtheoutputportisx9,thentwodatareadsfromafullqueuewill queue on the write port.
berequiredtocausethefullflagtogoHIGH(queuenotfull).Conversely,the
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheFFflag
OutputValidflagandAlmostEmptyflagoperationsarealwaysbasedonwrites outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis
andreadsofdatawidthsdeterminedbythereadport.Forexample,iftheinput madeonlyasingledevicedrivestheFFflagbusandallotherFF flagoutputs
portisx9andtheoutputportisx18,twowriteoperationswillberequiredtocause connectedtotheFFflagbusareplacedintoHigh-Impedance.Theuserdoes
theoutputvalidflagofanemptyqueuetogoLOW,outputvalid(queueisnot nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control
empty).
devicewillautomaticallyplaceitsFFflagoutputintoHigh-Impedancewhennone
Note,thattheinputportservesallqueueswithinadevice,asdoestheoutput ofitsqueuesareselectedforwriteoperations.
port,thereforetheinputbuswidthtoallqueuesisequal(determinedbytheinput
portsize)andtheoutputbuswidthfromallqueuesisequal(determinedbythe flagoutputofthatdevicewillmaintaincontroloftheFFflagbus.ItsFFflagwill
outputportsize).
Whenqueueswithinasingledeviceareselectedforwriteoperations,theFF
simplyupdatebetweenqueueswitchestoshowtherespectivequeuefullstatus.
Themulti-queuedeviceplacesitsFFflagoutputintoHigh-Impedancebased
onthe3bitIDcodefoundinthe3mostsignificantbitsofthewritequeueaddress
bus,WRADD.Ifthe3mostsignificantbitsofWRADDmatchthe3bitIDcodesetup
onthestaticinputs,ID0,ID1andID2thentheFFflagoutputoftherespective
devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheFFflag
outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure
11,FullFlagTiminginExpansionModefordetailsofflagoperation,including
when more than one device is connected in expansion.
TABLE 3 — BUS-MATCHING SET-UP
IW
OW
Write Port
Read Port
0
0
1
1
0
1
0
1
x18
x18
x9
x18
x9
x18
x9
x9
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
OUTPUTVALIDFLAGOPERATION
13,OutputValidFlagTimingfordetailsofflagoperation,includingwhenmore
The multi-queue flow-control device provides a single Output Valid flag thanone device is connectedinexpansion.
output,OV.TheOVprovidesanemptystatusordataoutputvalidstatusforthe
datawordcurrentlyavailableontheoutputregisterofthereadport.Therising ALMOST FULL FLAG
edgeofanRCLKcyclethatplacesnewdataontotheoutputregisteroftheread
As previously mentioned the multi-queue flow-control device provides a
port, also updates the OV flag to show whether or not that new data word is singleProgrammableAlmostFullflagoutput,PAF.ThePAFflagoutputprovides
actually valid. Internally the multi-queue flow-control device monitors and astatusofthealmostfullconditionfortheactivequeuecurrentlyselectedonthe
maintainsastatusoftheemptyconditionofallqueueswithinit,howeveronly writeportforwriteoperations.Internallythemulti-queueflow-controldevice
thequeuethatisselectedforreadoperationshasitsoutputvalid(empty)status monitorsandmaintainsastatusofthealmostfullconditionofallqueueswithin
outputtotheOVflag,givingavalidstatusforthewordbeingreadatthattime. it,howeveronlythequeuethatisselectedforwriteoperationshasitsfullstatus
Thenatureofthefirstwordfallthroughoperationmeansthatwhenthelast outputtothePAFflag.Thisdedicatedflagisoftenreferredtoasthe“activequeue
datawordisreadfromaselectedqueue,theOVflagwillgoHIGHonthenext almostfullflag”.ThepositionofthePAFflagboundarywithinaqueuecanbe
enabled read, that is, on the next rising edge of RCLK while REN is LOW.
atanypointwithinthatqueuesdepth.Thislocationcanbeuserprogrammed
Whenqueueswitchesarebeingmadeonthereadport,theOVflagwillswitch viatheserialportoroneofthedefaultvalues(8or128)canbeselectedifthe
toshowstatusofthenewqueueinlinewiththedataoutputfromthenewqueue. userhasperformeddefaultprogramming.
Whenaqueueselectionismadethefirstdatafromthatqueuewillappearon
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost
theQoutdataoutputs2RCLKcycleslater,theOVwillchangestatetoindicate fullstatus,whenaqueueisselectedonthewriteport,thisstatusisoutputviathe
validityofthedatafromthenewlyselectedqueueonthis2nd RCLKcyclealso. PAFflag.ThePAFflagvalueforeachqueueisprogrammedduringmulti-queue
Thepreviouscycleswillcontinuetooutputdatafromthepreviousqueueand device programming (along with the number of queues, queue depths and
theOVflagwillindicatethestatusofthoseoutputs.Again,theOVflagalways almostemptyvalues).ThePAFoffsetvalue,m,forarespectivequeuecanbe
indicatesstatusforthedatacurrentlypresentontheoutputregister.
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory
TheOVflagissynchronoustotheRCLKandalltransitionsoftheOVflagoccur depthforthatqueue.ThePAFvalueofdifferentqueueswithinthesamedevice
basedonarisingedgeofRCLK.Internallythemulti-queuedevicemonitorsand canbedifferentvalues.
keepsarecordoftheoutputvalid(empty)statusforallqueues.Itispossiblethat
Whenqueueswitchesarebeingmadeonthewriteport,thePAFflagoutput
thestatusofanOVflagmaybechanginginternallyeventhoughthatrespective willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus,
flagisnottheactivequeueflag(selectedonthereadport).Aqueueselected onthesecondcycleafteranewqueueselectionismade,onthesameWCLK
onthewriteportmayexperienceachangeofitsinternalOVflagstatusbased cyclethatdatacanactuallybewrittentothenewqueue.Thatis,anewqueue
on write operations, that is, data may be written into that queue causing it to canbeselectedonthewriteportviatheWRADDbus,WADENenableanda
become“notempty”.
risingedgeofWCLK.OnthesecondrisingedgeofWCLKfollowingaqueue
SeeFigure12,ReadQueueSelect,ReadOperationandFigure13,Output selection,thePAFflagoutputwillshowthefullstatusofthenewlyselectedqueue.
ValidFlagTimingfordetailsofthetiming.
The PAF is flagoutputis doubleregisterbuffered,sowhenawriteoperation
occursatthealmostfullboundarycausingtheselectedqueuestatustogoalmost
fullthePAFwillgoLOW2WCLKcyclesafterthewrite.Thesameistruewhen
EXPANSION MODE – OUTPUT VALID FLAG OPERATION
Whenmulti-queuedevicesareconnectedinExpansionmode,theOVflags a read occurs, there will be a 2 WCLK cycle delay after the read operation.
of all devices should be connected together, such that a system controller
monitoring and managing the multi-queue devices read port only looks at a
singleOVflag(asopposedtoadiscreteOVflagforeachdevice).ThisOVflag
is onlypertinenttothequeuebeingselectedforreadoperations atthattime.
Remember,thatwheninexpansionmodeonlyonemulti-queuedevicecanbe
So the PAF flag delays are:
froma write operationtoPAF flagLOWis 2WCLK+tWAF
ThedelayfromareadoperationtoPAFflagHIGHistSKEW2+WCLK+tWAF
Note, if tSKEW is violated there will be one added WCLK cycle delay.
ThePAFflagissynchronoustotheWCLKandalltransitionsofthePAFflag
readfromatanymomentintime,thustheOVflagprovidesstatusoftheactive occur based on a rising edge of WCLK. Internally the multi-queue device
queue on the read port. monitorsandkeepsarecordofthealmostfullstatusforallqueues.Itispossible
ThisconnectionofflagoutputstocreateasingleflagrequiresthattheOVflag thatthestatusofaPAFflagmaybechanginginternallyeventhoughthatflagis
outputhaveaHigh-Impedancecapability,suchthatwhenaqueueselectionis nottheactivequeueflag(selectedonthewriteport).Aqueueselectedonthe
madeonlyasingledevicedrivestheOVflagbusandallotherOVflagoutputs readportmayexperienceachangeofitsinternalalmostfullflagstatusbased
connectedtotheOVflagbusareplacedintoHigh-Impedance.Theuserdoes on read operations. The multi-queue flow-control device also provides a
nothavetoselectthisHigh-Impedancestate,agivenmulti-queueflow-control duplicateofthePAFflagonthePAF[3:0]flagbus,thiswillbediscussedindetail
devicewillautomaticallyplaceitsOVflagoutputintoHigh-Impedancewhennone inalatersectionofthedatasheet.
ofitsqueuesareselectedforreadoperations.
SeeFigures 18and19forAlmostFullflagtimingandqueueswitching.
Whenqueueswithinasingledeviceareselectedforreadoperations,theOV
flagoutputofthatdevicewillmaintaincontroloftheOVflagbus.ItsOVflagwill ALMOSTEMPTYFLAG
simplyupdatebetweenqueueswitchestoshowtherespectivequeueoutput
validstatus.
As previously mentioned the multi-queue flow-control device provides a
single Programmable Almost Empty flag output, PAE. The PAE flag output
Themulti-queuedeviceplacesitsOVflagoutputintoHigh-Impedancebased providesastatusofthealmostemptyconditionfortheactivequeuecurrently
onthe3bitIDcodefoundinthe3mostsignificantbitsofthereadqueueaddress selectedonthereadportforreadoperations.Internallythemulti-queueflow-
bus,RDADD.Ifthe3mostsignificantbitsofRDADDmatchthe3bitIDcodesetup controldevicemonitorsandmaintainsastatusofthealmostemptyconditionof
onthestaticinputs,ID0,ID1andID2thentheOVflagoutputoftherespective allqueueswithinit,howeveronlythequeuethatisselectedforreadoperations
devicewillbeinaLow-Impedancestate.Iftheydonotmatch,thentheOVflag hasitsemptystatusoutputtothePAEflag.Thisdedicatedflagisoftenreferred
outputoftherespectivedevicewillbeinaHigh-Impedancestate.SeeFigure toasthe“activequeuealmostemptyflag”.ThepositionofthePAEflagboundary
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
withinaqueuecanbeatanypointwithinthatqueuesdepth.Thislocationcan newlyselectedqueue.ThePAEis flagoutputis doubleregisterbuffered,so
beuserprogrammedviatheserialportoroneofthedefaultvalues(8or128) when a read operation occurs at the almost empty boundary causing the
canbeselectediftheuserhasperformeddefaultprogramming.
selectedqueuestatustogoalmostemptythePAEwillgoLOW2RCLKcycles
Asmentioned,everyqueuewithinamulti-queuedevicehasitsownalmost after the read. The same is true when a write occurs, there will be a 2 RCLK
emptystatus,whenaqueueisselectedonthereadport,thisstatusisoutputvia cycledelayafterthewriteoperation.
thePAEflag.ThePAEflagvalueforeachqueueisprogrammedduringmulti-
queuedeviceprogramming(alongwiththenumberofqueues,queuedepths
andalmostfullvalues).ThePAEoffsetvalue,n,forarespectivequeuecanbe
programmedtobeanywherebetween‘0’and‘D’,where‘D’isthetotalmemory
depthforthatqueue.ThePAEvalueofdifferentqueueswithinthesamedevice
canbedifferentvalues.
So the PAE flag delays are:
from a read operation toPAE flag LOW is 2 RCLK + tRAE
ThedelayfromawriteoperationtoPAEflagHIGHistSKEW2+RCLK+tRAE
Note, if tSKEW is violated there will be one added RCLK cycle delay.
ThePAEflagissynchronoustotheRCLKandalltransitionsofthePAEflag
occur based on a rising edge of RCLK. Internally the multi-queue device
Whenqueueswitchesarebeingmadeonthereadport,thePAEflagoutput monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible
willswitchtothenewqueueandprovidetheuserwiththenewqueuestatus, thatthestatusofaPAEflagmaybechanginginternallyeventhoughthatflagis
onthesecondcycleafteranewqueueselectionismade,onthesameRCLK nottheactivequeueflag(selectedonthereadport).Aqueueselectedonthe
cyclethatdataactuallyfallsthroughtotheoutputregisterfromthenewqueue. writeportmayexperienceachangeofitsinternalalmostemptyflagstatusbased
That is, a new queue can be selected on the read port via the RDADD bus, on write operations. The multi-queue flow-control device also provides a
RADENenableandarisingedgeofRCLK.OnthesecondrisingedgeofRCLK duplicateofthePAEflagonthePAE[3:0]flagbus,thiswillbediscussedindetail
followingaqueueselection,thedatawordfromthenewqueuewillbeavailable inalatersectionofthedatasheet.
attheoutputregisterandthePAEflagoutputwillshowtheemptystatusofthe
SeeFigures20and21forAlmostEmptyflagtimingandqueueswitching.
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING
Output Valid, OV Flag Boundary
Full Flag, FF Boundary
I/O Set-Up
OV Boundary Condition
I/O Set-Up
FF Boundary Condition
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenotebelowfortiming)
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after D+1 Writes
(seenotebelowfortiming)
In18 to out9)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 1st Write
(seenotebelowfortiming)
In18 to out18 or In9 to out9
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after D Writes
(seenotebelowfortiming)
In9 to out18
(Bothportsselectedforsamequeue
when the 1st Word is written in)
OV Goes LOW after 2nd Write
(seenotebelowfortiming)
In18 to out9
(Bothportsselectedforsamequeue
when the 1st Word is written in)
FF Goes LOW after D Writes
(seenotebelowfortiming)
In18 to out9
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after D Writes
NOTE:
1. OV Timing
Assertion:
(seenotebelowfortiming)
Write to OV LOW: tSKEW1 + RCLK + tROV
If tSKEW1 is violated there may be 1 added clock: tSKEW1 + 2 RCLK + tROV
De-assertion:
In9 to out18
FF Goes LOW after ([D+1] x 2) Writes
(seenotebelowfortiming)
(Bothportsselectedforsamequeue
when the 1st Word is written in)
Read Operation to OV HIGH: tROV
In9 to out18
(Writeportonlyselectedforqueue
when the 1st Word is written in)
FF Goes LOW after (D x 2) Writes
(seenotebelowfortiming)
NOTE:
D = Queue Depth
FF Timing
Assertion:
Write Operation to FF LOW: tWFF
De-assertion:
Read to FF HIGH: tSKEW1 + tWFF
If tSKEW1 is violated there may be 1 added clock: tSKEW1+WCLK +tWFF
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
Programmable Almost Empty Flag Bus, PAEn Boundary
Programmable Almost Empty Flag, PAE Boundary
I/O Set-Up
PAEn Boundary Condition
PAEn Goes HIGH after
I/O Set-Up
PAE Assertion
PAE Goes HIGH after n+2
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeuewhenthe1st n+2Writes
Wordiswritteninuntiltheboundaryisreached)
In18 to out18 or In9 to out9
(Bothportsselectedforsamequeuewhenthe1st Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
(seenotebelowfortiming)
In18 to out18 or In9 to out9
(Writeportonlyselectedforsamequeuewhenthe n+1Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
PAEn Goes HIGH after
In18 to out9
PAE Goes HIGH after n+1
(Bothportsselectedforsamequeuewhenthe1st Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
In18 to out9
PAEn Goes HIGH after n+1
Writes (seebelowfortiming)
In9 to out18
PAE Goes HIGH after
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
Wordiswritteninuntiltheboundaryisreached)
In9 to out18
PAEn Goes HIGH after
(seenotebelowfortiming)
(Bothportsselectedforsamequeuewhenthe1st ([n+2] x 2) Writes
Wordiswritteninuntiltheboundaryisreached)
(seenotebelowfortiming)
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
In9 to out18
PAEn Goes HIGH after
(Writeportonlyselectedforsamequeuewhenthe ([n+1] x 2) Writes
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
PAE Timing
Assertion:
Read Operation to PAE LOW: 2 RCLK + tRAE
NOTE:
De-assertion: Write to PAE HIGH: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAEn Timing
Assertion:
Read Operation to PAEn LOW: 2 RCLK* + tPAE
De-assertion: Write to PAEn HIGH: tSKEW3 + RCLK* + tPAE
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
Programmable Almost Full Flag, PAF & PAFn Bus Boundary
I/O Set-Up
PAF & PAFn Boundary
In18 to out18 or In9 to out9
PAF/PAFn Goes LOW after
(Bothportsselectedforsamequeuewhenthe1st D+1-mWrites
Wordiswritteninuntiltheboundaryisreached) (seenotebelowfortiming)
In18 to out18 or In9 to out9
(Writeportonlyselectedforsamequeuewhenthe D-mWrites
1st Wordis writteninuntiltheboundaryis reached) (seenotebelowfortiming)
PAF/PAFn Goes LOW after
In18 to out9
In9 to out18
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
PAF/PAFn Goes LOW after
([D+1-m] x 2) Writes
(seenotebelowfortiming)
NOTE:
D = Queue Depth
m = Almost Full Offset value.
Default values: if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
PAF Timing
Assertion:
Write Operation to PAF LOW: 2 WCLK + tWAF
De-assertion: Read to PAF HIGH: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF
PAFn Timing
Assertion:
Write Operation to PAFn LOW: 2 WCLK* + tPAF
De-assertion: Read to PAFn HIGH: tSKEW3 + WCLK* + tPAF
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
passing is done via the FXO outputs and FXI inputs of the devices (“PAFn
ExpansionOut”and“PAFnExpansionIn”).TheFXOoutputofthefirstdevice
connectingtothe FXIinputofthe seconddevice inthe chain, the FXOofthe
seconddeviceconnects totheFXIofthethirddeviceandsoon.TheFXOof
thefinaldeviceinachainconnectstotheFXIofthefirstdevice,sothatoncethe
PAFn bus has cycled through all devices control is again passed to the first
device.TheFXOoutputofadevicewillbeHIGHfortheWCLKcycleithascontrol
ofthebus.
PAFn FLAG BUS OPERATION
TheIDT72V51333/72V51343/72V51353multi-queueflow-controldevices
can be configured for up to 8 queues, each queue having its own almost full
status.Anactivequeuehasitsflagstatusoutputtothediscreteflags,FFandPAF,
onthewriteport.Queuesthatarenotselectedforawriteoperationcanhave
theirPAFstatusmonitoredviathePAFnbus.ThePAFnflagbusis8bitswide,
so that all 4 queues can have their status output to the bus. When a single
multi-queuedeviceisusedanywherefrom1to4queuesmaybeset-upwithin
thepart,eachqueuehavingitsowndedicatedPAFflagoutputonthePAFnbus.
Queues 1 through 8 have their PAF status to PAF[0] through PAF[7]
respectively. If less than 8 queues are used then only the associated PAFn
outputswillberequired,unusedPAFnoutputswillbedon’tcareoutputs.When
devices are connected in expansion mode the PAFn flag bus can also be
expandedbeyond8bits toproduce a widerPAFnbus thatencompasses all
queues.
Alternatively,the8bitPAFnflagbusofeachdevicecanbeconnectedtogether
toformasingle8bitbus,i.e.PAF[0]ofdevice1willconnecttoPAF[0]ofdevice
2etc. Whenconnectingdevices inthis mannerthe PAFncanonlybe driven
byasingledeviceatanytime,(thePAFnoutputsofallotherdevicesmustbe
inhighimpedancestate).Therearetwomethodsbywhichtheusercanselect
whichdevicehas controlofthebus,theseare“Direct”(Addressed)modeor
“Polled”(Looped)mode,determinedbythestateoftheFM(flagMode)input
duringaMasterReset.
PleaserefertoFigure24,PAFnBus–PolledModefortiminginformation.
PAEn FLAG BUS OPERATION
TheIDT72V51333/72V51343/72V51353multi-queueflow-controldevices
canbeconfiguredforupto8queues,eachqueuehavingitsownalmostempty
status.Anactivequeuehasitsflagstatusoutputtothediscreteflags,OVandPAE,
onthereadport.Queues thatarenotselectedforareadoperationcanhave
theirPAEstatusmonitoredviathePAEnbus.ThePAEnflagbusis8bitswide,
sothatall8queues canhavetheirstatus outputtothebus.
Whenasinglemulti-queuedeviceisusedanywherefrom1to8queuesmay
beset-upwithinthepart,eachqueuehavingitsowndedicatedPAEnflagoutput
onthePAEnbus.Queues1through8havetheirPAEstatustoPAE[0]through
PAE[7]respectively.Iflessthan8queuesareusedthenonlytheassociated
PAEnoutputswillberequired,unusedPAEnoutputswillbedon’tcareoutputs.
WhendevicesareconnectedinexpansionmodethePAEnflagbuscanalso
beexpandedbeyond8bits toproduceawiderPAEnbus thatencompasses
allqueues.
PAFn BUS EXPANSION - DIRECT MODE
Alternatively,the8bitPAEnflagbusofeachdevicecanbeconnectedtogether
toformasingle8bitbus,i.e.PAE[0]ofdevice1willconnecttoPAE[0]ofdevice
2etc.WhenconnectingdevicesinthismannerthePAEnbuscanonlybedriven
byasingledeviceatanytime,(thePAEnoutputsofallotherdevicesmustbe
inhighimpedancestate).Therearetwomethodsbywhichtheusercanselect
whichdevicehas controlofthebus,theseare“Direct”(Addressed)modeor
“Polled”(Looped)mode,determinedbythestateoftheFM(flagMode)input
duringaMasterReset.
If FM is LOW at Master Reset then the PAFn bus operates in Direct
(addressed)mode.Indirectmodetheusercanaddressthedevicetheyrequire
tocontrolthePAFnbus.Theaddresspresentonthe3mostsignificantbitsof
the WRADD[5:0] address bus with FSTR (PAF flag strobe), HIGH will be
selectedasthedeviceonarisingedgeofWCLK.Sotoaddressthefirstdevice
inabankofdevicestheWRADD[5:0]addressshouldbe“000xxx”thesecond
device “001xxx” and so on. The 3 most significant bits of the WRADD[5:0]
address bus correspond to the device ID inputs ID[2:0]. The PAFn bus will
change status to show the new device selected 1 WCLK cycle after device
selection.Note,thatifareadorwriteoperationisoccurringtoaspecificqueue,
sayqueue‘x’onthesamecycleasaPAFnbusswitchtothedevicecontaining
queue ‘x’, thenthere maybe anextra WCLKcycle delaybefore thatqueues
statusiscorrectlyshownontherespectiveoutputofthePAFnbus.However,
the“active”PAFflagwillshowcorrectstatusatalltimes.
Devices can be selected on consecutive WCLK cycles, that is the device
controllingthe PAFnbus canchangeeveryWCLKcycle. Also, datapresent
ontheinputbus,Din,canbewrittenintoaqueueonthesameWLCKrisingedge
thatadeviceisbeingselectedonthePAFnbus,theonlyrestrictionbeingthat
awritequeueselectionandPAFnbusselectioncannotbemadeonthesame
cycle.
PAEn BUS EXPANSION- DIRECT MODE
If FM is LOW at Master Reset then the PAEn bus operates in Direct
(addressed)mode.Indirectmodetheusercanaddressthedevicetheyrequire
tocontrolthePAEnbus.Theaddresspresentonthe3mostsignificantbitsof
the RDADD[6:0] address bus with ESTR (PAE flag strobe), HIGH will be
selectedasthedeviceonarisingedgeofRCLK.Sotoaddressthefirstdevice
inabankofdevicestheRDADD[6:0]addressshouldbe“000xxx”thesecond
device “001xxx” and so on. The 3 most significant bits of the RDADD[6:0]
address bus correspond to the device ID inputs ID[2:0]. The PAEn bus will
change status to show the new device selected 1 RCLK cycle after device
selection.Note,thatifareadorwriteoperationisoccurringtoaspecificqueue,
sayqueue‘x’onthesamecycleasaPAEnbusswitchtothedevicecontaining
queue ‘x’, then there may be an extra RCLK cycle delay before that queues
statusiscorrectlyshownontherespectiveoutputofthePAEnbus.However,
the“active”PAE flagwillshowcorrectstatusatalltimes.
PAFn BUS EXPANSION– POLLED MODE
IfFMisHIGHatMasterResetthenthePAFnbusoperatesinPolled(Looped)
mode.InpolledmodethePAFnbusautomaticallycyclesthroughthedevices
connected in expansion. In expansion mode one device will be set as the
Master,MASTinputtiedHIGH,allotherdeviceswillhaveMASTtiedLOW.The
masterdeviceisthefirstdevicetotakecontrolofthePAFnbusandplacethe
PAFstatusofitsqueuesontothebusonthefirstrisingedgeofWCLKafterthe
MRSinputgoesHIGHonceaMasterResetiscomplete.TheFSYNC(PAFsync
pulse)outputofthefirstdevice(masterdevice),willbeHIGHforonecycleof
WCLKindicatingthatitishascontrolofthePAFnbusforthatcycle.
Thedevicealsopassesa“token”ontothenextdeviceinthechain,thenext
deviceassumingcontrolofthePAFnbusonthenextWCLKcycle.Thistoken
Devices can be selected on consecutive RCLK cycles, that is the device
controllingthePAEnbuscanchangeeveryRCLKcycle.Also,datacanberead
outofaFIFOqueueonthesameRCLKrisingedgethatadeviceisbeingselected
onthePAEnbus,theonlyrestrictionbeingthatareadqueueselectionandPAEn
busselectioncannotbemadeonthesamecycle.
PAEn BUS EXPANSION- POLLED MODE
If FM is HIGH at Master Reset then the PAEn bus operates in Polled
(Looped)mode.InpolledmodethePAEnbusautomaticallycyclesthroughthe
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
devices connectedinexpansion. Inexpansionmode one device willbe set passing is done via the EXO outputs and EXI inputs of the devices (“PAEn
as theMaster,MASTinputtiedHIGH,allotherdevices willhaveMASTtied ExpansionOut”and“PAEnExpansionIn”).TheEXOoutputofthefirstdevice
LOW.ThemasterdeviceisthefirstdevicetotakecontrolofthePAEnbusand connectingtotheEXIinputoftheseconddeviceinthechain,theEXOofthe
placethePAEstatusofitsqueuesontothebusonthefirstrisingedgeofRCLK seconddeviceconnects totheEXIofthethirddeviceandsoon.TheEXOof
after the MRS input goes HIGH once a Master Reset is complete. The thefinaldeviceinachainconnectstotheEXIofthefirstdevice,sothatoncethe
ESYNC (PAE sync pulse) output of the first device (master device), will be PAEn bus has cycled through all devices control is again passed to the first
HIGHforonecycleofRCLKindicatingthatitishascontrolofthePAEnbusfor device.TheEXOoutputofadevicewillbeHIGHfortheRCLKcycleithascontrol
thatcycle.
Thedevicealsopassesa“token”ontothenextdeviceinthechain,thenext
deviceassumingcontrolofthePAEnbusonthenextRCLKcycle.Thistoken
ofthebus.
PleaserefertoFigure25,PAEnBus–PolledModefortiminginformation.
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
B
Write to Queue
A
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE
IW
L
OW
L
A
B
Read from Queue
L
(a) x18 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
L
B
A
Read from Queue
H
(b) x18 INPUT to x18 OUTPUT - LITTLE ENDIAN
Q8-Q0
Q17-Q9
Q17-Q9
BE
IW
L
OW
H
A
1st: Read from Queue
2nd: Read from Queue
L
Q8-Q0
B
(c) x18 INPUT to x9 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
H
B
1st: Read from Queue
H
Q17-Q9
Q8-Q0
A
2nd: Read from Queue
(d) x18 INPUT to x9 OUTPUT - LITTLE ENDIAN
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
A
1st: Write to Queue
2nd: Write to Queue
D17-Q9
D8-Q0
B
BYTE ORDER ON OUTPUT PORT:
Q17-Q9
Q8-Q0
BE
IW OW
A
B
Read from Queue
L
H
L
(a) x9 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
H
OW
L
A
B
Read from Queue
H
(a) x9 INPUT to x18 OUTPUT - LITTLE ENDIAN
5940 drw07
Figure 3. Bus-Matching Byte Arrangement
25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
tRS
MRS
t
RSS
RSS
WEN
REN
t
tRSR
SENI
tRSS
FSTR,
ESTR
tRSS
WADEN,
RADEN
t
RSS
RSS
RSS
ID0, ID1,
ID2
t
OW, IW
FM
t
HIGH = Looped
LOW = Strobed (Direct)
tRSS
HIGH = Master Device
LOW = Slave Device
MAST
DFM
t
RSS
RSS
HIGH = Default Programming
LOW = Serial Programming
t
HIGH = Offset Value is 128
LOW = Offset value is 8
DF
t
t
t
t
RSF
HIGH-Z if Slave Device
FF
LOGIC “0" if Master Device
RSF
RSF
RSF
LOGIC "1" if Master Device
OV
PAF
PAE
HIGH-Z if Slave Device
LOGIC "1" if Master Device
HIGH-Z if Slave Device
HIGH-Z if Slave Device
LOGIC "0" if Master Device
t
RSF
RSF
LOGIC "1" if Master Device
HIGH-Z if Slave Device
PAFn
PAEn
t
HIGH-Z if Slave Device
LOGIC "0" if Master Device
tRSF
LOGIC "1" if OE is LOW and device is Master
Qn
HIGH-Z if OE is HIGH or Device is Slave
5940 drw08
NOTES:
1. OE can toggle during this period.
2. PRS should be HIGH during a MRS.
Figure 4. Master Reset
26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
w-2
w-1
w
w+1
w+2
w+3
WCLK
tQH
tQS
WADEN
WEN
tENS
tENS
t
AS
tAH
WRADD
Qx
t
WFF
FF
tWAF
PAF
t
PAF
Active Bus
PAF-Qx(5)
tPRSS
tPRSH
PRS
tPRSH
tPRSS
RCLK
tENS
tENS
REN
tQH
tQS
RADEN
t
AS
tAH
RDADD
Qx
tROV
OV
tRAE
PAE
t
PAE
Active Bus
PAE-Qx(6)
r-2
r-1
r
r+1
r+2
r+3
5940 drw09
NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 2 clock cycles before the Partial Reset takes place, on both the write and read ports.
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
Figure 5. Partial Reset
Master Reset
Default Mode
DFM = 0
MRS
MRS
DFM
DFM
MRS
DFM
MQ2
MQn
MQ1
Serial Loading
Complete
SENI
SI
SENO
SO
SENI
SI
SENI
SI
SENO
SO
SENO
SO
Serial Enable
Serial Input
SCLK
SCLK
SCLK
5940 drw10
Serial Clock
Figure 6. Serial Port Connection for Serial Programming
27
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
28
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
29
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
30
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WCLK
tENH
tENS
WEN
tDS
tDH
tDS
tDH
tDS
tDH
W1
W2
W3
Dn
RCLK
REN
t
SKEW1
1
2
tENS
tA
tA
tA
Last Word Read Out of Queue
W1 Qy
FWFT
W2 Qy
FWFT
W3 Qy
Qout
OV
tROV
tROV
5940 drw12a
NOTES:
1. Qy has previously been selected on both the write and read ports.
2. OE is LOW.
3. The First Word Latency = tSKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.
Figure 10. Write Operations & First Word Fall Through
31
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
33
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK
REN
tENS
tAS
tAH
tAS
tAH
RDADD
RADEN
D1
Q3
D1 Q2
Addr=001011
QH
Addr=0010010
QH
tQS
t
t
tQS
tA
tA
tA
tA
tOLZ
Qout
D
1
Q
3
WD
Last Word
D1 Q2
PFT We-1
D1
Q2
We
Last Word
W0 Q2
D1
(Device 1)
t
ROV
tROV
tROV
tROV
tOVLZ
HIGH-Z
OV
(Device 1)
tOVHZ
OV
(Device 2)
tSKEW1
WCLK
tENS
tENH
WEN
tAS
tAH
WRADD
D1 Q2
tQS
tQH
WADEN
Din
tDS
t
DH
D1 Q2
W0
5940 drw15
Cycle:
*A* Queue 3 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control
of Qout bus, its Qout outputs are in Low-Impedance. This diagram only shows the Qout outputs of device 1. (Reads are disabled).
*B* Reads are now enabled. A word from the previously selected queue of Device 2 will be read out.
*C* The Qout of Device 1 goes to Low-Impedance and word Wd is read from Q3 of D1. This happens to be the last word of Q3. Device 2 places its Qout outputs into
High-Impedance, device 1 has control of the Qout bus. The OV flag of Device 2 goes to High-Impedance and Device 1 takes control of OV. The OV flag of Device 1 goes LOW
to show that Wd of Q3 is valid.
*D* Queue 2 of device 1 is selected for read operations. The last word of Q3 was read on the previous cycle, therefore OV goes HIGH to indicate that the data on the Qout is
not valid (Q3 was read to empty). Word, Wd remains on the output bus.
*E* The last word of Q3 remains on the Qout bus, OV is HIGH, indicating that this word has been previously read.
*F* The next word (We-1), available from the newly selected queue, Q2 of device 1 is now read out. This will occur regardless of REN, 2 RCLK cycles after queue selection
due to the FWFT operation. The OV flag now goes LOW to indicate that this word is valid.
*G* The last word, We is read from Q2, this queue is now empty.
*H* The OV flag goes HIGH to indicate that Q2 was read to empty on the previous cycle.
*I* Due to a write operation the OV flag goes LOW and data word W0 is read from Q2. The latency is: tSKEW1 + 1*RCLK + tROV.
Figure 13. Output Valid Flag Timing (In Expansion Mode)
34
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
*J*
RCLK
tENS
tENH
tENS
tENH
REN
tAS
tAH
tAH
tAS
RDADD
Qn
QP
tQS
tQH
tQS
tQH
RADEN
tA
tA
tA
tA
tA
tA
QOUT
QP
WD
QP WD+1
Q
P
WD+2
Qn
WX
Qn
WX+1
Q
P
WD+3
QP WD+4
OV
5940 drw16
Cycle:
*A* Word Wd+1 is read from the previously selected queue, Qp.
*B* Reads are disabled, word Wd+1 remains on the output bus.
*C* A new queue, Qn is selected for read port operations.
*D* Due to FWFT operation Word, Wd+2 of Qp is read out regardless of REN.
*E* The next available word Wx of Qn is read out regardless of REN, 2 RCLK cycles after queue selection. This is FWFT operation.
*F* The queue, Qp is again selected.
*G* Word Wx+1 is read from Qn regardless of REN, this is due to FWFT.
*H* Word Wd+3 is read from Qp, this read occurs regardless of REN due to FWFT operation.
*I* Word Wd+4 is read from Qp.
*J* Reads are disabled on this cycle, therefore no further reads occur.
Figure 14. Read Queue Selection with Reads Disabled
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
RCLK
REN
tENS
tENH
tENS
tAS
tAH
tAS
tAH
RDADD
RADEN
QB
QA
tQS
tQH
tQS
tQH
OE
tA
tA
tA
tA
tOHZ
tA
tOE
tOLZ
Qout
Previous Data in O/P Register
Q
A
PFT
W
0
QA
W1
QA
W2
QA
W3
QA W4
No Read
QB is Empty
ROV
tROV
t
OV
5940 drw17
NOTES:
1. The Output Valid flag, OV is HIGH therefore the previously selected queue has been read to empty. The Output Enable input is Asynchronous, therefore the Qout output bus
will go to Low-Impedance after time tOLZ.
The data currently on the output register will be available on the output after time tOE. This data is the previous data on the output register, this is the last word read out of the
previous queue.
2. In expansion mode the OE inputs of all devices should be connected together. This allows the output busses of all devices to be High-Impedance controlled.
Cycle:
*A* Queue A is selected for reads. No data will fall through on this cycle, the previous queue was read to empty.
*B* No data will fall through on this cycle, the previous queue was read to empty.
*C* Word, W0 from Qa is read out regardless of REN due to FWFT operation. The OV flag goes LOW indicating that Word W0 is valid.
*D* Reads are disabled therefore word, W0 of Qa remains on the output bus.
*E* Reads are again enabled so word W1 is read from Qa.
*F* Word W2 is read from Qa.
*G* Queue, Qb is selected on the read port. This queue is actually empty. Word, W3 is read from Qa.
*H* Word, W4 falls through from Qa.
*I* Output Valid flag, OV goes HIGH to indicate that Qb is empty. Data on the output port is no longer valid.
Output Enable is taken HIGH, this is Asynchronous so the output bus goes to High-Impedance after time, tOHZ.
Figure 15. Read Queue Select, Read Operation and OE Timing
35
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
SELECT
NEW QUEUE
*D*
NULL QUEUE
SELECT
*A*
*B*
*C*
*E*
*F*
RCLK
tAS
tAH
tAS
tAH
0001xxx
0000011
D0 Q3
RDADD
RADEN
tQS
tQH
tQS
tQH
tENS
tENH
REN
tA
tA
tA
tA
Qout
Q1 Wn-3
Q1 Wn-2
Q1 Wn-1
Q1 Wn
Q3 W0
FWFT
tROV
tROV
OV
5940 drw18
NOTES:
1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words
from that queue.
2. Please see Figure 17, Null Queue Flow Diagram.
Cycle:
*A* Null Q of device 0 is selected, when word Wn-1 from previously selected Q1 is read.
*B* REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register.
Note: *B* and *C* are a minimum 2 RCLK cycles between Q selects.
*C* The Null Q is seen as an empty queue on the read side, therefore Wn of Q1 remains in the O/P register and OV goes HIGH.
*D* A new Q, Q3 is selected and the 1st word of Q3 will fall through present on the O/P register on cycle *F*.
Figure 16. Read Operation and Null Queue Select
*A*
*B*
*C*
*D*
*E*
*F*
Null
Queue
Queue 3
Memory
Queue 3
Memory
Queue 1
Memory
Null
Queue
Null
Queue
Q1
Q1
Q1
Q1
Q3
Q3
Wn
Wn
Wn
Wn
W0
W1
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
O/P Reg.
Qn
Q1
Q1
Q1
Q1
Q3
Wn-1
Wn
Wn
Wn
Wn
W0
5940 drw19
Figure 17. Null Queue Flow Diagram
36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
*A*
*B*
*C*
*E*
*F*
*D*
WCLK
WEN
1
2
tENH
tENS
tAS
tAH
tAS
tQS
tAH
WRADD
D1
Q2
D1 Q0
tQS
tQH
tQH
WADEN
Din
tDS
tDH
WD-m
D1 Q2
tWAF
tWAF
tAFLZ
HIGH-Z
PAF
(Device 1)
tFFHZ
PAF
(Device 2)
5940 drw20
Cycle:
*A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* Word, Wd-m is written into Q2 causing the PAF flag to go from HIGH to LOW. The flag latency is 2 WCLK cycles + tWAF.
*D* Queue 0 if device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 2 WCLK + tWAF latency.
*E* The PAF flag goes LOW based on the write 2 cycles earlier.
*F* The PAF flag goes HIGH due to the queue switch to Q0.
Figure 18. Almost Full Flag Timing and Queue Switch
tCLKL
tCLKL
WCLK
WEN
PAF
1
2
1
tENS
tENH
tWAF
tWAF
D-(m+1) words
in Queue
D - (m+1) words in Queue
D - m words in Queue
tSKEW2
RCLK
tENS
tENH
5940 drw21
REN
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + tWAF
De-assertion: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there will be one extra WCLK cycle.
Figure 19. Almost Full Flag Timing
37
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
*A*
*B*
*C*
*D*
*E*
*F*
*G*
RCLK
REN
HIGH
AS
t
tAH
tAS
tAH
RDADD
D1
Q3
D1
Q1
tQS
tQH
tQH
tQS
RADEN
Qout
tA
tA
tA
tA
tOLZ
HIGH-Z
HIGH-Z
D1
Q3
Wn
D
1
Q3
Wn+1
D
1
Q1
W0
D1 Q1 W1
t
RAE
t
RAE
tAELZ
PAE
(Device 1)
tAEHZ
PAE
(Device 2)
HIGH-Z
5940 drw22
Cycle:
*A* Queue 3 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* The PAE flag output now switches to device 1. Word, Wn is read from Q3 due to the FWFT operation. This read operation from Q3 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*D* Q1 of device 1 is selected.
*E* The PAE flag goes LOW due to the read from Q3 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*F* Word, W0 is read from Q1 due to the FWFT operation. The PAE flag goes HIGH to show that Q1 is not almost empty.
Figure 20. Almost Empty Flag Timing and Queue Switch
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
n+1 words in Queue
SKEW2
n+2 words in Queue
n+1 words in Queue
tRAE
t
tRAE
RCLK
1
2
tENS
tENH
5940 drw23
REN
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + tRAE
De-assertion: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there will be one extra RCLK cycle.
Figure 21. Almost Empty Flag Timing
38
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
*A*
*B*
1
*C*
2
*D*
*E*
*F*
WCLK
WADEN
FSTR
tQH
tQS
tQS
tQH
t
STS
tSTH
tENS
tENS
tENH
tENH
WEN
tAH
tAH
tAS
t
AS
t
AS
tAH
Device 4
D3Q2
011010
WRADD
Dn
D5Q3
100 011
tDH
100 xxx
tDS
t
DH
tDS
Wp
Wp+1
Wn+1
D5Q3
Wn
D5 Q3
Wx
D3 Q2
Writes to Previous Q
tSKEW3
RCLK
RADEN
ESTR
1
2
tQS
tQH
t
STS
t
STH
tENS
tENH
REN
tAH
t
AS
t
AS
tAH
RDADD
Device 5
D5Q3
100 0011
101 xxxx
tA
tA
tA
tA
tA
Wy
D5 Q3
Wy+1
D5 Q3
Wy+3
D5 Q3
Device 5 -Qn
Wa
D5 Qx
Wa+1
D5 Qn
Wy+2
D5 Q3
Previous value loaded on to PAE bus
Prev PAEn
t
PAEHZ
t
PAE
tPAEZL
xxxx1xxx
Device 5
xxxx1xxx
Device 5
Device 5 PAEn
xxxx1xxx
Device 5
xxxx1xxx
Device 5
Previous value loaded on to PAE bus
D5 Qx Status
Bus PAEn
t
RAE
tRAE
tRAE
D5 Q3
status
Device 5 PAE
5940 drw24
*AA*
*BB*
*CC*
*EE*
*FF*
*DD*
Cycle:
*A* Queue 3 of Device 5 is selected for write operations.
Word, Wp is written into the previously selected queue.
*AA* Queue 3 of Device 5 is selected for read operations.
Another device has control of the PAEn bus.
The discrete PAE output of device 5 is currently in High-Impedance and the PAE active flag is controlled by the previously selected device.
*B* Word Wp+1 is written into the previously selected queue.
*BB* Word, Wa+1 is read from Qx of D5, due to FWFT operation.
*C* Word, Wn is written into the newly selected queue, Q3 of D5. This write will cause the PAE flag on the read port to go from LOW to HIGH (not almost empty) after time,
tSKEW3 + RCLK + tRAE (if tSKEW3 is violated one extra RCLK cycle will be added.
*CC* Word, Wy from the newly selected queue, Q3 will be read out due to FWFT operation.
Device 5 is selected on the PAEn bus. Q3 of device 5 will therefore have is PAE status output on PAE[3]. There is a single RCLK cycle latency before the PAEn bus changes
to the new selection.
*D* Queue 2 of Device 3 is selected for write operations.
Word Wn+1 is written into Q3 of D5.
*DD* The PAEn bus changes control to D5, the PAEn outputs of D5 go to Low-Impedance and are placed onto the outputs. The previously selected device now places its
PAEn outputs into High-Impedance to prevent bus contention. Word, Wy+1 is read from Q3 of D5.
The discrete PAE flag will go HIGH to show that Q3 of D5 is not almost empty. Q3 of device 5 will have its PAE status output on PAE[3].
*E* No writes occur.
*EE* Word, Wy+2 is read from Q3 of D5.
*F* Device 4 is selected on the write port for the PAFn bus.
Word, Wx is written into Q2 of D3.
*FF* The PAEn bus updates to show that Q3 of D5 is almost empty based on the reading out of word, Wy+1.
The discrete PAE flag goes LOW to show that Q3 of D5 is almost empty based on the reading of Wy+1.
Figure 22. PAEn - Direct Mode, Flag Operation – Devices in Expansion
39
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
*A*
*B*
*C*
*D*
*E*
*F*
*G*
RCLK
tQH
tQS
tQS
tQH
RADEN
t
STH
t
STS
ESTR
REN
t
AS
tAH
tAH
t
AS
RDADD
Device 7
D6Q2
D0Q1
110 0010
111 xxxx
000 0001
OE
tA
tA
tA
tA
tOLZ
Qout
W
Prev. Q
X
W
Prev. Q
X +1
W
D0 Q1
D - M + 2
W0
D6 Q2
W
D0 Q1
D-M+1
tSKEW3
WCLK
FSTR
1
2
t
STS
t
STH
t
AS
tAH
tAS
tAH
WRADD
Device 0
000 xxxx
D0 Q1
tENS
tENH
WEN
tQS
tQH
WADEN
Din
t
DS
t
DH
tDS
tDH
tDS
tDH
Word W
y
Wy+1
Wy+2
D0 Q1
D0 Q1
D0 Q1
t
PAFLZ
tPAF
t
PAF
Device 0 PAFn
xxxxxx0x
xxxxxx0x
xxxxxx1x
xxxxxx1x
xxxxxx0x
xxxxxx0x
Device 0
Device 0
Device 0
Device 0
Device 0
HIGH-Z
Previous Device
Previous Device
Bus PAFn
Device 0
t
PAFHZ
HIGH-Z
Prev. PAFn
t
PAFLZ
tWAF
Device 0 PAF
HIGH - Z
5940 drw25
*AA*
*BB*
*CC*
*DD*
*EE*
*FF*
Cycle:
*A* Queue 1 of device 0 is selected for read operations.
The last word in the output register is available on Qout. OE was previously taken LOW so the output bus is in Low-Impedance.
*AA* Device 0 is selected for the PAFn bus. The bus is currently providing status of a previously selected device X.
*B* Word, Wx+1 is read out from the previous queue due to the FWFT effect.
*BB* Queue 1 of device 0 is selected on the write port.
The PAFn bus is updated with the device selected on the previous cycle, device 0 PAF[1] is LOW showing the status of queue 1.
The PAFn outputs of the device previously selected on the PAFn bus go to High-Impedance.
*C* Device 7 is selected for the PAFn bus.
Word, Wd-m+1 is read from Q1 D0 due to the FWFT operation. This read is at the PAFn boundary of queue D0 Q1. This read will cause the PAF[1] output to go from
LOW to HIGH (almost full to not almost full), after a delay tSKEW3 + WCLK + tPAF. If tSKEW3 is violated add an extra WCLK cycle.
*CC* PAFn continues to show status of D0.
*D* No read operations occur, REN is HIGH.
*DD* PAF[1] goes HIGH to show that D0 Q1 is not almost empty due to the read on cycle *C*.
The active queue PAF flag of device 0 goes from High-Impedance to Low-Impedance.
Word, Wy is written into D0 Q1.
*E* Queue 2 of Device 6 is selected for write operations.
*EE* Word, Wy+1 is written into D0 Q1.
*F* Word, Wd-m+2 is read out due to FWFT operation.
*FF* PAF[1] and the discrete PAF flag go LOW to show the write on cycle *DD* causes Q1 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q1.
*G* Word, W0 is read from Q0 of D6, selected on cycle *E*, due to FWFT.
Figure 23. PAFn - Direct Mode, Flag Operation – Devices in Expansion
40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WCLK
t
FSYNC
tFSYNC
t
FSYNC
t
FSYNC
FXO
FSYNC
0
(MASTER)
tFXO
t
FXO
tFXO
t
FXO /
0
FXI
1
tFSYNC
tFSYNC
FSYNC
1
(SLAVE)
tFXO
tFXO
FXO /
1
FXI
2
tFSYNC
tFSYNC
FSYNC
2
(SLAVE)
tFXO
tFXO
FXO /
2
FXI
0
t
PAF
t
PAF
tPAF
t
PAF
t
PAF
PAF[7:0]
Device 0
Device 1
Device 2
Device 0
5940 drw26
NOTE:
1. This diagram is based on 3 devices connected to expansion mode.
Figure 24. PAFn Bus - Polled Mode
41
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
RCLK
t
ESYNC
tESYNC
t
ESYNC
t
ESYNC
EXO
ESYNC
0
tEXO
t
EXO
tEXO
t
EXO /
0
EXI
1
tESYNC
tESYNC
ESYNC
1
tEXO
tEXO
EXO /
1
FXI
2
tESYNC
tESYNC
ESYNC
2
tEXO
tEXO
EXO /
2
EXI
0
t
PAE
t
PAE
tPAE
t
PAE
t
PAE
PAE
Device 0
Device 1
Device 2
Device 0
n
5940 drw27
Figure 25. PAEn Bus - Polled Mode
42
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Serial Programming Data Input
Serial Enable
SENI
SI FXI EXI
Output Data Bus
Data Bus
Q -Q
17
D -D
17
0
0
Read Clock
Write Clock
RCLK
WCLK
Write Enable
Read Enable
WEN
REN
RDADD
RADEN
Write Queue Select
Write Address
Read Queue Select
Read Address
WRADD
DEVICE
1
WADEN
FSTR
Empty Strobe
Full Strobe
ESTR
PAEn
Programmable Almost Full
Programmable Almost Empty
PAFn
Empty Sync 1
Output Valid Flag
Almost Empty Flag
Full Sync1
ESYNC
FSYNC
Full Flag
OV
FF
Almost Full Flag
Serial Clock
PAF
PAE
SCLK
SENO SO FXO EXO
SENI SI FXI EXI
Q -Q
D -D
17
0
17
0
WCLK
RCLK
WEN
REN
WRADD
WADEN
RDADD
RADEN
DEVICE
2
FSTR
PAFn
ESTR
PAEn
Empty Sync 2
Full Sync2
FSYNC
ESYNC
FF
OV
PAF
PAE
SCLK
SENO SO FXO EXO
SENI
SI FXI EXI
Q -Q
D -D
17
0
17
0
WCLK
RCLK
REN
WEN
WRADD
WADEN
RDADD
RADEN
DEVICE
n
FSTR
PAFn
FSYNC
ESTR
PAEn
Full Sync n
Empty Sync n
ESYNC
FF
OV
PAF
PAE
SCLK
SENO
FXO EXO
DONE
5940 drw28
NOTES:
1. If devices are configured for Direct operation of the PAFn/PAEn flag busses the FXI/EXI of the MASTER device should be tied LOW. All other devices tied HIGH. The FXO/EXO
outputs are DNC (Do Not Connect).
2. Q outputs must not be mixed between devices, i.e. Q0 of device 1 must connect to Q0 of device 2, etc.
Figure 26. Multi-Queue Expansion Diagram
43
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72V51333/72V51343/
72V51353incorporates thenecessarytapcontrollerandmodifiedpadcellsto
implementtheJTAG facility.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
The Figure belowshows the standardBoundary-ScanArchitecture
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5940 drw29
Figure 27. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
44
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
1
Test-Logic
Reset
0
1
Select-
IR-Scan
0
1
1
Run-Test/
Idle
Select-
DR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-DR
Pause-IR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-DR
Update-IR
1
0
1
0
5940 drw30
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal Queue operations can begin.
Figure 28. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram.
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overthe Queue andmustbe resetafterpowerupofthe device. See TRST
descriptionformoredetailsonTAPcontrollerreset.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IR This state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenabling
thenormaloperationoftheIC.TheTAPcontrollerstatemachineisdesigned
insuchawaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-
Logic-ResetstatecanbeenteredbyholdingTMSathighandpulsingTCKfive
times. This is the reasonwhythe TestReset(TRST)pinis optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-Scan This is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
45
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
THE INSTRUCTION REGISTER
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
•
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions. Instructionsaredecodedasfollows.
TESTDATAREGISTER
Hex
Value
00
01
02
Instruction
Function
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
EXTEST
SAMPLE/PRELOAD
IDCODE
HIGH-IMPEDANCE
BYPASS
SelectBoundaryScanRegister
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
JTAG
04
0F
SelectBypassRegister
JTAG INSTRUCTION REGISTER DECODING
TEST BYPASS REGISTER
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
EXTEST
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO.Duringthisinstruction,theboundary-scanregisterisaccessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
IDCODE
THE DEVICE IDENTIFICATION REGISTER
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDI and TDO. The device identification register is a 32-bit shift register
containinginformationregardingtheICmanufacturer,devicetype,andversion
code.Accessingthedeviceidentificationregisterdoesnotinterferewiththe
operationoftheIC.Also,accesstothedeviceidentificationregistershouldbe
immediatelyavailable,viaaTAPdata-scanoperation,afterpower-upofthe
ICoraftertheTAPhasbeenresetusingtheoptionalTRSTpinorbyotherwise
movingtotheTest-Logic-Resetstate.
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
FortheIDT72V51333/72V51343/72V51353,thePartNumberfieldcon-
tainsthefollowingvalues:
Device
Part# Field (HEX)
0x421
IDT72V51333
IDT72V51343
IDT72V51353
SAMPLE/PRELOAD
0x422
0x423
TherequiredSAMPLE/PRELOADinstructionallowstheICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.This instructionis alsousedtopreloadtestdata
intotheboundary-scanregisterbeforeloadinganEXTESTinstruction.
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
JTAG DEVICE IDENTIFICATION REGISTER
46
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
toTDOwithoutaffectingtheconditionoftheICoutputs.
theIC.
47
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51333/72V51343/72V513533.3V,MULTI-QUEUEFLOW-CONTROLDEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5940 drw31
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 29. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
(vcc = 3.3V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol
Test
Conditions
Min. Max. Units
SYSTEMINTERFACEPARAMETERS
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
IDT72V51333
IDT72V51343
IDT72V51353
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
48
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Plastic Ball Grid Array (PBGA, BB256-1)
BB
Commercial Only
Commercial & Industrial
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
6
7-5
L
Low Power
72V51333 589,824 bits 3.3V Multi-Queue Flow-Control Device
72V51343 1,179,648 bits 3.3V Multi-Queue Flow-Control Device
72V51353 2,359,296 bits 3.3V Multi-Queue Flow-Control Device
5940 drw32
NOTE:
1. Industrial temperature range product for the 7-5ns is available as a standard device. All other speed grades are available by special order.
DATASHEETDOCUMENTHISTORY
10/10/2001
11/16/2001
12/19/2001
01/15/2002
04/05/2002
07/01/2002
06/04/2003
pgs. 1, 7, 9, 13, 14 and 26.
pgs. 1, 4, 9, 14, 16, 17, 22, 23, 26-29 and 31.
pgs. 11 and 27.
pg. 46.
pgs. 6, 8, 10, 12 and 47.
pgs. 2 and 26.
pgs. 1 through 49.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1533
email:Flow-Controlhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
49
相关型号：
©2020 ICPDF网 联系我们和版权申明