72V81L15PA8 [IDT]
TSSOP-56, Reel;
| 型号： | 72V81L15PA8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TSSOP-56, Reel |
| 文件： | 总12页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72V81
IDT72V82
IDT72V83
IDT72V84
IDT72V85
3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
DUAL 512 x 9, DUAL 1,024 x 9
DUAL 2,048 x 9, DUAL 4,096 X 9
DUAL 8,192 X 9
FEATURES:
DESCRIPTION:
•
•
•
•
•
•
The IDT72V81 is equivalent to two IDT72V01 - 512 x 9 FIFOs
The IDT72V82 is equivalent to two IDT72V02 - 1,024 x 9 FIFOs
The IDT72V83 is equivalent to two IDT72V03 - 2,048 x 9 FIFOs
The IDT72V84 is equivalent to two IDT72V04 - 4,096 x 9 FIFOs
The IDT72V85 is equivalent to two IDT72V05 - 8,192 x 9 FIFOs
Low power consumption
TheIDT72V81/72V82/72V83/72V84/72V85aredual-FIFOmemoriesthat
loadandemptydataonafirst-in/first-outbasis.Thesedevicesarefunctionaland
compatibletotwoIDT72V01/72V02/72V03/72V04/72V05FIFOsinasingle
packagewithallassociatedcontrol,data,andflaglinesassignedtoseparate
pins. The devices use Full and Empty flags to prevent data overflow and
underflowandexpansionlogictoallowforunlimitedexpansioncapabilityinboth
word size and depth.
— Active: 330 mW (max.)
— Power-down: 18 mW (max.)
Ultra high speed—15 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
The reads and writes are internally sequential through the use of ring
pointers,withnoaddressinformationrequiredtoloadandunloaddata. Data
istoggledinandoutofthedevicesthroughtheuseoftheWrite(W)andRead
(R) pins.
•
•
•
The devices utilize a 9-bit wide data array to allow for control and parity
•
Ideal for bidirectional, width expansion, depth expansion, bus- bitsattheuser’soption.Thisfeatureis especiallyusefulindatacommunications
matching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CMOS™ technology
Space-saving TSSOP package
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
applicationswhereitisnecessarytouseaparitybitfortransmission/reception
errorchecking.ItalsofeaturesaRetransmit(RT)capabilitythatallowsforreset
of the read pointer to its initial position when RT is pulsed low to allow for
retransmissionfromthebeginningofdata.AHalf-FullFlagisavailableinthe
singledevicemodeandwidthexpansionmodes.
TheseFIFOsarefabricatedusinghigh-speedCMOStechnology.Theyare
designed for those applications requiring asynchronous and simultaneous
read/writesinmultiprocessingandratebufferapplications.
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
DATA INPUTS
(DA
0
-DA
8)
RSA
(DB
0
-DB
8)
RSB
WB
WRITE
CONTROL
WRITE
CONTROL
WA
RAM
RAM
ARRAY A
512 x 9
ARRAY A
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
WRITE
POINTER
WRITE
POINTER
READ
POINTER
READ
POINTER
THREE-
STATE
BUFFERS
THREE-
STATE
BUFFERS
READ
CONTROL
READ
CONTROL
RA
RESET
LOGIC
RESET
LOGIC
FLAG
LOGIC
FLAG
LOGIC
EXPANSION
LOGIC
EXPANSION
LOGIC
XIA
FFA EFA
RB
XIB
XOA/HFA
FLA/RTA
FFB EFB
FLB/RTB
DATA
XOB/HFB
DATA
OUTPUTS
(QB0-QB8)
OUTPUTS
3966 drw 01
(QA -QA8)
0
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheAsyncFIFO™isatrademarkofIntegratedDeviceTechnology,Inc.
JUNE 2012
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
DSC-3966/5
©
2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V853.3VCMOSDUALASYNCHRONOUSFIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
ABSOLUTEMAXIMUMRATINGS
PIN CONFIGURATION
Symbol
Rating
Com'l & Ind'l
Unit
VTERM
TerminalVoltage
–0.5 to +7.0
V
with Respect to GND
FFA
XIA
DA
DA
DA
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
QA0
0
1
2
2
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50to+50
°C
mA
QA
QA
QA
1
3
2
3
4
DA3
NOTE:
5
QA
8
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DA
8
6
GND
WA
7
RA
V
CC
4
5
6
8
QA
4
DA
DA
DA
DA
9
QA
QA
QA
5
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
6
7
7
RECOMMENDED DC OPERATING
CONDITIONS
XOA/HFA
EFA
FLA/RTA
RSA
FFB
XIB
Symbol
VCC
Parameter
Min. Typ. Max. Unit
QB
0
DB
0
SupplyVoltage
3.0 3.3
3.6
0
V
V
QB
QB
QB
1
DB
DB
DB
DB
WB
1
2
3
2
GND
VIH(1)
VIL(2)
TA
SupplyVoltage
0
2.0
—
0
0
3
InputHighVoltage
—
—
—
—
VCC+0.5
0.8
V
QB
8
8
GND
InputLowVoltage
V
RB
V
CC
4
5
6
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
70
°C
°C
QB
4
DB
DB
DB
DB
TA
-40
85
QB
QB
QB
5
6
7
NOTES:
7
1. For RT/RS/XI input, VIH = 2.6V (commercial and industrial).
2. 1.5V undershoots are allowed for 10ns once per cycle
XOB/HFB
FLB/RTB
RSB
EFB
3966 drw 02
CAPACITANCE(TA = +25°C, f = 1.0 MHz)
Symbol
CIN
Parameter(1)
InputCapacitance
OutputCapacitance
Condition
VIN = 0V
Max.
Unit
TSSOP (SO56-2, order code: PA)
TOP VIEW
8
8
pF
pF
COUT
VOUT = 0V
NOTE:
1. Characterized values, not currently tested.
DCELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3V±0.3V, TA = 0°C to +70°C;
Industrial: VCC = 3.3V±0.3V, TA = -40°C to +85°C)
Commercial
tA = 15, 20 ns
Industrial
tA = 20 ns
Symbol
Parameter
Min.
Max.
Min. Max.
Unit
(1)
ILI
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
–1
–10
2.4
—
1
10
—
0.4
100
5
–1
–10
2.4
—
1
10
—
0.4
120
5
μA
μA
V
(2)
ILO
VOH
VOL
Output Logic “1” Voltage IOH = –2mA
Output Logic “0” Voltage IOL = 8mA
Active Power Supply Current (both FIFOs)
Standby Current (R=W=RS=FL/RT=VIH)
V
3.3V
(3,4)
ICC1
—
—
mA
mA
(3,5)
ICC2
—
—
NOTES:
330Ω
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
TO
OUTPUT
PIN
3. Tested with outputs open (IOUT = 0).
4. Tested at f = 20 MHz.
5. All Inputs = VCC - 0.2V or GND + 0.2V.
30pF*
510Ω
ACTESTCONDITIONS
Input Pulse Levels
GND to 3.0V
5ns
3966 drw 03
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
or equivalent circuit
Figure 1. Output Load
*Includes scope and jib capacitances.
1.5V
See Figure 1
2
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V853.3VCMOSDUALASYNCHRONOUSFIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3V±0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V±0.3V, TA = -40°C to +85°C)
Commercial
Commercial & Industrial
IDT72V81L15
IDT72V82L15
IDT72V83L15
IDT72V84L15
IDT72V85L15
IDT72V81L20
IDT72V82L20
IDT72V83L20
IDT72V84L20
IDT72V85L20
Symbol
tS
Parameter
Min.
—
25
—
10
15
3
Max.
40
—
15
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
25
25
25
15
15
—
15
15
25
25
—
15
15
—
—
—
Min.
—
30
—
10
20
3
Max.
33.3
—
20
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
—
—
30
30
30
20
20
—
20
20
30
30
—
20
20
—
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ShiftFrequency
tRC
ReadCycleTime
AccessTime
tA
tRR
ReadRecoveryTime
ReadPulseWidth(2)
tRPW
tRLZ
tWLZ
tDV
Read Pulse Low to Data Bus at Low Z(3)
WritePulseHightoDataBusatLowZ(3,4)
DataValidfromReadPulseHigh
ReadPulseHightoDataBusatHighZ(3)
WriteCycleTime
5
5
5
5
tRHZ
tWC
—
25
15
10
11
0
—
30
20
10
12
0
tWPW
tWR
WritePulseWidth(2)
WriteRecoveryTime
tDS
DataSet-upTime
tDH
DataHoldTime
tRSC
tRS
ResetCycleTime
25
15
15
10
25
15
15
10
—
—
—
—
—
15
—
—
—
—
15
—
—
15
10
10
30
20
20
10
30
20
20
10
—
—
—
—
—
20
—
—
—
—
20
—
—
20
10
10
ResetPulseWidth(2)
tRSS
tRSR
tRTC
tRT
ResetSet-upTime(3)
ResetRecoveryTime
RetransmitCycleTime
RetransmitPulseWidth(2)
RetransmitSet-upTime(3)
RetransmitRecoveryTime
ResettoEmptyFlagLow
ResettoHalf-FullandFullFlagHigh
RetransmitLowtoFlagsValid
Read Low to Empty Flag Low
Read High to Full Flag High
ReadPulseWidthafterEFHigh
Write High to Empty Flag High
Write Low to Full Flag Low
WriteLowtoHalf-FullFlagLow
ReadHightoHalf-FullFlagHigh
WritePulseWidthafterFFHigh
Read/WritetoXOLow
tRTS
tRTR
tEFL
tHFH,FFH
tRTF
tREF
tRFF
tRPE
tWEF
tWFF
tWHF
tRHF
tWPF
tXOL
tXOH
tXI
Read/WritetoXOHigh
XIPulseWidth(2)
XI Recovery Time
XISet-upTime
tXIR
tXIS
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum value are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
3
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V853.3VCMOSDUALASYNCHRONOUSFIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
SingleDeviceMode, thispinactsastheretransmitinput. TheSingleDevice
Mode is initiated by grounding the Expansion In (XI).
SIGNALDESCRIPTIONS
INPUTS:
The IDT72V81/72V82/72V83/72V84/72V85 can be made to retransmit
datawhentheRetransmitEnablecontrol(RT)inputispulsedlow. Aretransmit
operationwillsettheinternalreadpointertothefirstlocationandwillnotaffect
the write pointer. Read Enable (R) and Write Enable (W) must be in the high
stateduringretransmitfortheIDT72V81/72V82/72V83/72V84/72V85respec-
tively.Thisfeatureisusefulwhenlessthan512/1,024/2,048/4,096/8,192writes
areperformedbetweenresets.Theretransmitfeatureisnotcompatiblewiththe
Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on
therelativelocationsofthereadandwritepointers.
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET ( RS )
ResetisaccomplishedwhenevertheReset(RS)inputistakentoalowstate.
Duringreset,bothinternalreadandwritepointersaresettothefirstlocation.
Aresetisrequiredafterpowerupbeforeawriteoperationcantakeplace.Both
the Read Enable (R ) and Write Enable (W ) inputs must be in the high
state during the window shown in Figure 2, (i.e., tRSS before the rising
edge of RS ) and should not change until tRSR after the rising edge of
RS. Half-Full Flag ( HF ) will be reset to high after Reset ( RS ).
EXPANSION IN ( XI )
Thisinputisadual-purposepin. ExpansionIn(XI)isgroundedtoindicate
an operation in the single device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth Expansion or Daisy
Chain Mode.
WRITE ENABLE ( W )
AwritecycleisinitiatedonthefallingedgeofthisinputiftheFullFlag(FF)
isnotset.Dataset-upandholdtimesmustbeadheredtowithrespecttotherising
edgeoftheWriteEnable(W).DataisstoredintheRAMarraysequentiallyand
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of the next write
operation,theHalf-FullFlag(HF)willbesettolowandwillremainsetuntilthe
differencebetweenthewritepointerandreadpointerislessthanorequalto
onehalfofthetotalmemoryofthedevice.TheHalf-FullFlag(HF)isthenreset
by the rising edge of the read operation.
OUTPUTS:
FULL FLAG ( FF )
TheFullFlag(FF)willgolow,inhibitingfurtherwriteoperation,whenthewrite
pointerisonelocationlessthanthereadpointer,indicatingthatthedeviceisfull.
If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go low
after 512 writes for the IDT72V81, 1,024 writes for the IDT72V82, 2,048 writes
for the IDT72V83, 4,096 writes for the IDT72V84 and 8,192 writes for the
IDT72V85.
Topreventdataoverflow,theFullFlag(FF)willgolow,inhibitingfurtherwrite
operations. Uponthecompletionofavalidreadoperation, theFullFlag(FF)
willgohighaftertRFF,allowingavalidwritetobegin.WhentheFIFOisfull,the
internalwritepointerisblockedfromW,soexternalchangesinWwillnotaffect
the FIFO when it is full.
EMPTY FLAG ( EF )
The Empty Flag (EF) will go low, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating that the device is
empty.
EXPANSION OUT/HALF-FULL FLAG ( XO/HF )
READ ENABLE ( R )
This is a dual-purpose output. In the single device mode, when Expan-
sionIn(XI)isgrounded,thisoutputactsasanindicationofahalf-fullmemory.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set low and will remain set until the
difference between the write pointer and read pointer is less than or equal
toonehalfofthetotalmemoryofthedevice.TheHalf-FullFlag(HF)isthenreset
by using rising edge of the read operation.
IntheDepthExpansionMode,ExpansionIn(XI)isconnectedtoExpansion
Out(XO)ofthepreviousdeviceintheDaisyChainbyprovidingapulsetothe
nextdevicewhenthepreviousdevicereachesthelastlocationofmemory.
AreadcycleisinitiatedonthefallingedgeoftheReadEnable(R)provided
theEmptyFlag(EF)isnotset.ThedataisaccessedonaFirst-In/First-Outbasis,
independentofanyongoingwriteoperations.AfterReadEnable(R)goeshigh,
theDataOutputs(Q0–Q8)willreturntoahighimpedanceconditionuntilthe
nextReadoperation.WhenalldatahasbeenreadfromtheFIFO,theEmpty
Flag (EF)willgolow, allowingthe“final”readcyclebutinhibitingfurtherread
operationswiththedataoutputsremaininginahighimpedancestate.Oncea
validwriteoperationhasbeenaccomplished,theEmptyFlag(EF)willgohigh
aftertWEFandavalidReadcanthenbegin.WhentheFIFOisempty,theinternal
readpointerisblockedfromRsoexternalchangesinRwillnotaffecttheFIFO
whenitisempty.
DATA OUTPUTS ( Q0 – Q8 )
Data outputs for 9-bit wide data. This data is in a high impedance
condition whenever Read (R) is in a high state.
FIRST LOAD/RETRANSMIT ( FL/RT )
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first loaded (see Operating Modes). In the
4
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V853.3VCMOSDUALASYNCHRONOUSFIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
tRSC
tRS
RS
W
tRSS
tRSR
tRSS
R
tEFL
EF
tHFH, tFFH
3966 drw 04
HF, FF
NOTES:
1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.
2. W and R = VIH around the rising edge of RS.
Figure 2. Reset
tRPW
tRC
tRR
tA
tA
R
tDV
tRHZ
tRLZ
Q0-Q8
DATA OUT VALID
DATA OUT VALID
tWC
tWR
tWPW
W
tDS
tDH
D0-D8
DATA IN VALID
DATA IN VALID
3966 drw 05
Figure 3. Asynchronous Write and Read Operation
LAST WRITE
IGNORED
WRITE
FIRST READ
ADDITIONAL
READS
FIRST
WRITE
R
W
t
WFF
t
RFF
3966 drw 06
FF
Figure 4. Full Flag From Last Write to First Read
5
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V853.3VCMOSDUALASYNCHRONOUSFIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
LAST READ
IGNORED
READ
FIRST WRITE
ADDITIONAL FIRST READ
WRITES
W
R
EF
tWEF
t
REF
tA
VALID
VALID
DATA OUT
3966 drw 07
Figure 5. Empty Flag From Last Read to First Write
tRTC
tRT
RT
W,R
t
RTS
tRTR
t
RTF
HF, EF, FF
FLAG VALID
3966 drw 08
Figure 6. Retransmit
W
EF
R
t
WEF
tRPE
3966 drw 09
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
R
FF
W
t
RFF
tWPF
3966 drw 10
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse
6
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V853.3VCMOSDUALASYNCHRONOUSFIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
W
R
tRHF
tWHF
HALF-FULL OR LESS
3966 drw 11
HALF-FULL OR LESS
HF
MORE THAN HALF-FULL
Figure 9. Half-Full Flag Timing
WRITE TO
LAST PHYSICAL
LOCATION
READ FROM
LAST PHYSICAL
LOCATION
W
R
tXOL
tXOH
tXOH
tXOL
3966 drw 12
XO
Figure 10. Expansion Out
tXIR
tXI
XI
tXIS
WRITE TO
FIRST PHYSICAL
LOCATION
W
R
tXIS
READ FROM
FIRST PHYSICAL
LOCATION
3966 drw 13
Figure 11. Expansion In
strates a four-FIFO Depth Expansion using two IDT72V81/72V82/72V83/
72V84/72V85s. Any depth can be attained by adding additional IDT72V81/
72V82/72V83/72V84/72V85s.TheseFIFOsoperateintheDepthExpansion
mode when the following conditions are met:
OPERATINGMODES:
Caremustbetakentoassurethattheappropriateflagismonitoredbyeach
system(i.e.FFismonitoredonthedevicewhereWisused;EFismonitoredon
the device where Ris used).
1. ThefirstFIFOmustbedesignatedbygroundingtheFirstLoad(FL)control
input.
2. All other FIFOs must have FLin the high state.
Single Device Mode
3. TheExpansionOut(XO)pinofeachdevicemustbetiedtotheExpansion
In (XI) pin of the next device. See Figure 14.
4. ExternallogicisneededtogenerateacompositeFullFlag(FF)andEmpty
Flag(EF).ThisrequirestheORingofallEFsandORingofallFFs(i.e.all
mustbesettogeneratethecorrectcompositeFForEF).SeeFigure14.
5. TheRetransmit(RT)functionandHalf-FullFlag(HF)arenotavailablein
theDepthExpansionMode.
A single IDT72V81/72V82/72V83/72V84/72V85 may be used when the
applicationrequirementsarefor512/1,024/2,048/4,096/8,192wordsorless.
TheseFIFOsareinaSingleDeviceConfigurationwhentheExpansionIn(XI)
control input is grounded (see Figure 12).
Depth Expansion
Thesedevicescaneasilybeadaptedtoapplicationswhentherequirements
are for greater than 512/1,024/2,048/4,096/8,192 words. Figure 14 demon-
7
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V853.3VCMOSDUALASYNCHRONOUSFIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
FIFOpermitsareadingofasinglewordafterwritingonewordofdataintoan
empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising
edgeofW,calledthefirstwriteedge,anditremainsonthe busuntiltheRline
israisedfromlow-to-high,afterwhichthebuswouldgointoathree-statemode
aftertRHZ ns.TheEFlinewouldhaveapulseshowingtemporarydeassertion
and then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permits the writing
of a single word of data immediately after reading one word of data from a
fullFIFO. The Rlinecausesthe FFtobedeassertedbuttheWlinebeinglow
causesittobeassertedagaininanticipationofanewdataword.Ontherising
edgeofW,thenewwordisloadedintheFIFO.TheWlinemustbetoggledwhen
FFisnotassertedtowritenewdataintheFIFOandtoincrementthewritepointer.
USAGEMODES:
Width Expansion
Word width may be increased simply by connecting the corresponding
input control signals of multiple FIFOs. Status flags (EF, FF and HF) can be
detectedfromanyoneFIFO. Figure13demonstratesan18-bitwordwidthby
usingthetwoFIFOscontainedintheIDT72V81/72V82/72V83/72V84/72V85s.
Any word width can be attained by adding FIFOs (Figure 13).
Bidirectional Operation
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT72V81/72V82/72V83/72V84/72V85sasshowninFigure16.BothDepth
ExpansionandWidthExpansionmaybeusedinthismode.
Compound Expansion
Thetwoexpansiontechniquesdescribedabovecanbeappliedtogether
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
Data Flow-Through
Two types of flow-through modes are permitted, a read flow-through
andwriteflow-throughmode.Forthereadflow-throughmode(Figure17),the
(HALF-FULL FLAG)
(HF)
WRITE (W)
READ (R)
FIFO
A or B
IDT
9
9
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
DATA OUT (Q)
72V81
72V82
72V83
72V84
72V85
EMPTY FLAG (EF)
RETRANSMIT (RT)
3966 drw 14
EXPANSION IN (XI)
Figure 12. Block Diagram of One 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 FIFO Used in Single Device Mode
9
HFA
HFB
18
9
DATA IN (D)
FIFO A
FIFO B
WRITE (W)
FULL FLAG (FFA)
RESET (RS)
READ (R)
EMPTY FLAG (EFB)
RETRANSMIT (RT)
9
72V81/72V82/72V83
72V84/72V85
9
XIA
XIB
18
OUT (Q)
DATA
3966 drw 15
Figure 13. Block Diagram of One 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 and 8,192 x 18 FIFO Memory Used in Width Expansion Mode
8
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V853.3VCMOSDUALASYNCHRONOUSFIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
TABLEI—RESETANDRETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs
InternalStatus
Outputs
Mode
RS
0
RT
X
XI
0
Read Pointer
LocationZero
LocationZero
Increment(1)
Write Pointer
LocationZero
Unchanged
EF
0
FF
1
HF
1
Reset
Retransmit
Read/Write
1
0
0
X
X
X
1
1
0
Increment(1)
X
X
X
NOTE:
1. Pointer will increment if flag is High.
TABLE II—RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs
InternalStatus
Write Pointer
Outputs
Mode
ResetFirstDevice
Reset All Other Devices
Read/Write
RS
0
FL
0
XI
(1)
(1)
(1)
Read Pointer
LocationZero
LocationZero
X
EF
FF
1
LocationZero
LocationZero
X
0
0
X
0
1
1
1
X
X
NOTE:
1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output, XI = Expan-
sion Input, HF = Half-Full Flag Output
XOA
EFA
FFA
FIFO A
FLA
XIA
72V81/72V82
72V83/72V84
72V85
XOB
W
R
EFB
FFB
FIFO B
D
Q
9
9
9
FLB
VCC
XIB
XOA
FFA
EFA
FULL
EMPTY
FIFO A
9
FLA
XIA
72V81/72V82
72V83/72V84
72V85
XOB
EFB
FFB
FIFO B
9
RSA
FLB
XIB
3966 drw 16
Figure 14. Block Diagram of 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9 and 32,768 x 9 FIFO Memory (Depth Expansion)
9
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V853.3VCMOSDUALASYNCHRONOUSFIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
Q0-Q8
Q9-Q17
Q(N-8)-Q
N
Q0-Q8
Q9-Q17
Q(N-8)-Q
N
IDT
IDT
IDT
72V81/72V82/72V83
72V84/72V85
72V81/72V82/72V83
72V84/72V85
72V81/72V82/72V83
72V84/72V85
R, W, RS
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
DEPTH
EXPANSION
BLOCK
D9-D17
D(N-8)-D
N
D0-D8
D0-DN
D9-DN
D18-D
N
D(N-8)-D
N
3966 drw 17
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
WA
RA
EF
HF
A
FIFO A
A
FFA
DA 0-8
QA 0-8
IDT
72V81
72V82
72V83
72V84
72V85
SIDE 1
SIDE 2
DA 0-8
QB 0-8
FIFO B
WB
RB
HF
B
FFB
EFB
3966 drw 18
Figure 16. Bidirectional FIFO Mode
IN
W
R
DATA
tRPE
EF
tWEF
tREF
tWLZ
tA
OUT
DATA
OUT
DATA
VALID
3966 drw 19
Figure 17. Read Data Flow-Through Mode
10
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V853.3VCMOSDUALASYNCHRONOUSFIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
R
W
tWPF
t
RFF
FF
tDH
WFF
t
IN
DATA
VALID
IN
DATA
tA
tDS
OUT
DATA
OUT
DATA
VALID
3966 drw 20
Figure 18. Write Data Flow-Through Mode
11
ORDERINGINFORMATION
XXXX
X
XXX
X
X
X
X
Device Type Power Speed Package
Process/
Temperature
Range
Blank Tube or Tray
8
Tape and Reel
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(1)
PA
Green
Thin Shrink SOIC (TSSOP, SO56-2)
15
20
Commercial Only
Commerical & Industrial
Access Time (tA)
Speed in Nanoseconds
L
Low Power
72V81 512 x 9 ⎯ 3.3V Dual FIFO
72V82 1,024 x 9 ⎯ 3.3V Dual FIFO
2,048 x 9 ⎯ 3.3V Dual FIFO
4,096 x 9 ⎯ 3.3V Dual FIFO
8,192 x 9 ⎯ 3.3V Dual FIFO
72V83
72V84
72V85
3966 drw 21
NOTE:
1. Green parts are available. For specific speeds contact your local sales office.
DATASHEETDOCUMENTHISTORY
07/17/2006
02/05/2009
06/13/2011
06/29/2012
pgs. 1 and 12.
pg. 12.
pgs. 1, 2, 3 and 12.
pgs. 1
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
12
相关型号：
72V81L15PAG
3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO DUAL 512 x 9, DUAL 1,024 x 9 DUAL 2,048 x 9, DUAL 4,096 X 9 DUAL 8,192 X 9
IDT
72V81L15PAGI
3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO DUAL 512 x 9, DUAL 1,024 x 9 DUAL 2,048 x 9, DUAL 4,096 X 9 DUAL 8,192 X 9
IDT
72V81L20PAG
3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO DUAL 512 x 9, DUAL 1,024 x 9 DUAL 2,048 x 9, DUAL 4,096 X 9 DUAL 8,192 X 9
IDT
72V81L20PAGI
3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO DUAL 512 x 9, DUAL 1,024 x 9 DUAL 2,048 x 9, DUAL 4,096 X 9 DUAL 8,192 X 9
IDT
©2020 ICPDF网 联系我们和版权申明