74ALVC08PG [IDT]
TSSOP-14, Tube;
| 型号： | 74ALVC08PG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TSSOP-14, Tube |
| 文件： | 总5页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74ALVC08
3.3V CMOS
QUADRUPLE 2-INPUT
POSITIVE-AND GATE
FEATURES:
DESCRIPTION:
–
–
0.5 MICRON CMOS Technology
This quadruple 2-inputpositive-ANDgate is builtusingadvanceddual
metalCMOStechnology.The ALVC08performs the BooleanfunctionY=
A • B or Y = A + B in positive logic.
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SOIC, SSOP and TSSOP packages
–
–
–
–
–
–
TheALVC08hasbeendesignedwitha±24mAoutputdriver. Thisdriver
is capable of driving a moderate to heavy load while maintaining speed
performance.
Drive Features for ALVC08:
APPLICATIONS:
• 3.3V High Speed Systems
• 3.3V and lower voltage computing systems
–
–
High Output Drivers: ±24mA
Suitable for heavy loads
FUNCTIONALBLOCKDIAGRAM
PIN CONFIGURATION
14
13
1
2
1
A
VCC
4B
A
1B
1Y
2A
2B
Y
12
11
10
9
4
A
3
4
5
6
7
B
SO14-1
SO14-2
SO14-3
4
Y
3B
3A
3Y
2
Y
8
GND
SOIC/ SSOP/ TSSOP
TOP VIEW
(1)
FUNCTION TABLE (each gate)
PIN DESCRIPTION
Pin Names
Description
Inputs
Output
xA
H
xB
H
X
L
xY
H
L
xA, xB
xY
Data Inputs
Data Outputs
L
X
L
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2000
1
c
1999 Integrated Device Technology, Inc.
DSC-4633/-
IDT74ALVC08
INDUSTRIALTEMPERATURERANGE
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE
ABSOLUTE MAXIMUM RATINGS (1)
(TA = +25°C, f = 1.0MHz)
CAPACITANCE
Parameter(1)
Conditions
Typ.
Max.
Unit
Symbol
Description
Max.
Unit
Symbol
(2)
CIN
Input Capacitance
VIN = 0V
5
7
pF
VTERM
Terminal Voltage with Respect to GND
– 0.5 to + 4.6
V
COUT
CI/O
Output Capacitance
I/O Port Capacitance
VOUT = 0V
VIN = 0V
7
7
9
9
pF
(3)
VTERM
Terminal Voltage with Respect to GND – 0.5 to VCC + 0.5
V
pF
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
– 65 to + 150
– 50 to + 50
± 50
°C
ALVC QUAD Link
NOTE:
mA
mA
1. As applicable to the device type.
Continuous Clamp Current,
VI < 0 or VI > VCC
IOK
Continuous Clamp Current, VO < 0
– 50
mA
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
ALVC QUAD Link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = −40°C to +85°C
(1)
Typ.
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
—
V
2
—
0.7
0.8
± 5
± 5
– 1.2
—
VIL
Input LOW Voltage Level
—
—
—
—
—
—
—
—
V
—
IIH
IIL
Input HIGH Current
VI = VCC
VI = GND
—
µA
Input LOW Current
VCC = 3.6V
—
VIK
VH
Clamp Diode Voltage
Input Hysteresis
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
– 0.7
100
0.1
V
mV
µA
ICCL
ICCH
∆ICC
Quiescent Power Supply Current
VCC = 3.6V
10
VIN = GND or VCC
Quiescent Power Supply
Current Variation
One input at VCC − 0.6V,
other inputs at VCC or GND
—
—
750
µA
ALVC QUAD Link
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
c
2
IDT74ALVC08
INDUSTRIALTEMPERATURERANGE
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
IOH = – 0.1mA
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
VCC – 0.2
—
V
IOH = – 6mA
IOH = – 12mA
2
—
—
VCC = 2.3V
1.7
2.2
2.4
2
VCC = 2.7V
—
VCC = 3.0V
—
VCC = 3.0V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
V
IOL = 12mA
IOL = 12mA
IOL = 24mA
VCC = 2.7V
VCC = 3.0V
ALVC QUAD Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to + 85°C.
o
OPERATING CHARACTERISTICS, T = 25 C
A
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Unit
Symbol
Parameter
Test Conditions
Typical
Typical
CPD
Power Dissipation Capacitance per gate
CL = 0pF, f = 10Mhz
25
26
pF
(1)
SWITCHING CHARACTERISTICS
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Max.
Min.
1.2
Max.
Min.
Max.
Unit
Propagation Delay
xA or xB to xY
1
3.2
3.4
1.2
3.3
ns
tPHL
NOTE:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
3
IDT74ALVC08
INDUSTRIALTEMPERATURERANGE
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
TEST CONDITIONS
Symbol
(1)
(1)
(2)
VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V
Unit
V
IH
VLOAD
6
6
2 xVcc
Vcc
V
SAME PHASE
INPUT TRANSITION
VT
0V
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
V
tPHL
tPLH
VOH
VT
Vcc / 2
150
OUTPUT
VLZ
VHZ
CL
mV
mV
VOL
tPHL
tPLH
150
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
30
pF
ALVC QUAD Link
ALVC Link
TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES
VLOAD
DISABLE
VCC
ENABLE
VIH
VT
Open
GND
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
Pulse(1, 2)
Generator
VLOAD/2
VT
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VOL + VLZ
VOL
500Ω
tPHZ
t
PZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VOH - VHZ
SWITCH
OPEN
VT
0V
ALVC Link
DEFINITIONS:
0V
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
ALVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SET-UP, HOLD, AND RELEASE TIMES
VIH
DATA
INPUT
SWITCH POSITION
VT
0V
tSU
tH
Test
Switch
VIH
VT
0V
TIMING
INPUT
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
GND
Open
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU
tH
ALVC QUAD Link
ALVC Link
OUTPUT SKEW - TSK (x)
VIH
VT
0V
INPUT
PULSE WIDTH
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
PULSE
VT
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
tSK (x)
tW
VOH
VT
HIGH-LOW-HIGH
PULSE
VT
VOL
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
4
IDT74ALVC08
INDUSTRIALTEMPERATURERANGE
3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-AND GATE
ORDERINGINFORMATION
IDT
XX
XXX
XX
ALVC
Device Type Package
Temp. Range
Small Outline IC (SO14-1)
Shrink Small Outline Package (SO14-2)
Thin Shrink Small Outline Package (SO14-3)
DC
PY
PG
08
74
Quadruple 2-Input Positive-AND Gate, ±24mA
– 40°C to +85°C
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5
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