74ALVCH162721PF [IDT]

TVSOP-56, Tube;


型号：	74ALVCH162721PF
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	TVSOP-56, Tube 光电二极管逻辑集成电路触发器电视
文件：	总6页 (文件大小：87K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74ALVCH162721

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

EXTENDED COMMERCIAL TEMPERATURE RANGE

3.3V CMOS 20-BIT

IDT74ALVCH162721

FLIP-FLOP WITH 3-STATE

OUTPUTS AND BUS-HOLD

DESCRIPTION:

FEATURES:

This 20-bit flip-flop is built using advanced dual metal CMOS technol-

–

0.5 MICRON CMOS Technology

Typicalt^SK(0)(Output Skew) < 250ps

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

0.635mm pitch SSOP, 0.50mm pitch TSSOP,

and 0.40mm pitch TVSOP packages

ogy. The 20 flip-flops of the ALVCH162721 are edge-triggered D-type

flip-flops with qualified clock storage. On the positive transition of the

clock (CLK) input, the device provides true data at the Q outputs if the

clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored.

–

A buffered output-enable (OE) input places the 20 outputs in either a

normal logic state (high or low) or a high-impedance state. In the high-

impedance state, the outputs neither load nor drive the bus lines

significantly. The high-impedance state and increased drive provide the

capability to drive bus lines without need for interface or pullup compo-

nents. OE does not affect the internal operation of the flip-flops. Old data

can be retained or new data can be entered while the outputs are in the

high-impedance state.

–

Extended commercial range of – 40°C to + 85°C

V^CC= 3.3V ± 0.3V, Normal Range

V^CC= 2.7V to 3.6V, Extended Range

V^CC= 2.5V ± 0.2V

CMOS power levels (0.4µW typ. static)

Rail-to-Rail output swing for increased noise margin

Drive Features for ALVCH162721:

–

Balanced Output Drivers: ±12mA

Low switching noise

The ALVCH162721 has series resistors in the device output structure

which will significantly reduce line noise when used with light loads. This

driver has been designed to drive ±12mA at the designated threshold

levels.

APPLICATIONS:

• 3.3V High Speed Systems

• 3.3V and lower voltage computing systems

The ALVCH162721 has “bus-hold” which retains the inputs’ last state

whenever the input goes to a high impedance. This prevents floating

inputs and eliminates the need for pull-up/down resistor.

Functional Block Diagram

CLK

CLKEN

Q¹

D¹

To 19 Other Channels

EXTENDED COMMERCIAL TEMPERATURE RANGE

MARCH1999

1999 Integrated Device Technology, Inc.

DSC-4566/-

IDT74ALVCH162721

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

EXTENDED COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATING ⁽¹⁾

PIN CONFIGURATION

Symbol

Description

Terminal Voltage

Max.

Unit

(2)

VTERM

– 0.5 to + 4.6

Q¹

CLK

D¹

with Respect to GND

Terminal Voltage

(3)

VTERM

– 0.5 to

VCC + 0.5

Q²

D²

with Respect to GND

Storage Temperature

GND

D³

TSTG

IOUT

IIK

– 65 to + 150

°C

Q³

Q⁴

DC Output Current

– 50 to + 50

± 50

D⁴

Continuous Clamp Current,

VI < 0 or VI > VCC

V^CC

D⁵

IOK

Continuous Clamp Current, VO < 0

– 50

Q⁵

Q⁶

Q⁷

ICC

ISS

Continuous Current through

each VCC or GND

±100

D⁶

D⁷

NEW16link

NOTES:

GND

Q⁸

GND

D⁸

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

2. V^CCterminals.

Q⁹

D⁹

SO56-1

SO56-2

SO56-3

Q¹⁰

Q¹¹

Q¹²

D¹⁰

D¹¹

D¹²

D¹³

GND

D¹⁴

D¹⁵

D¹⁶

V^CC

D¹⁷

3. All terminals except V^CC.

Q¹³

GND

Q¹⁴

CAPACITANCE (T^A= +25^oC, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

Typ.

Max.

Unit

CIN

Input Capacitance

VIN = 0V

Q¹⁵

Q¹⁶

COUT

CI/O

Output

Capacitance

I/O Port

VOUT = 0V

VIN = 0V

V^CC

Q¹⁷

Capacitance

Q¹⁸

D¹⁸

NEW16link

NOTE:

GND

1. As applicable to the device type.

Q¹⁹

Q²⁰

D¹⁹

D²⁰

FUNCTION TABLE (each flip-flop)⁽¹⁾

CLKEN

Inputs

Output

SSOP/

TSSOP/TVSOP

TOP VIEW

CLKEN

CLK

↑

L or H

PIN DESCRIPTION

Pin Names

Description

NOTE:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

3–State Output Enable Input (Active LOW)

Data Inputs⁽¹⁾

Z = High-Impedance

↑ = LOW-to-HIGHTransition

Q0 = Output level before the indicated steady-state input conditions were

established.

3-State Outputs

CLK

CLKEN

Clock Input

Clock Enable Input (Active LOW)

No Internal Connection

NOTE:

1. These pins have “Bus-Hold.” All other pins are standard inputs,

outputs, or I/Os.

IDT74ALVCH162721

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

EXTENDED COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = – 40° C to +85° C

Symbol

Parameter

Test Conditions

Min.

Typ.⁽¹⁾

Max.

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 3.6V

1.7

—

0.7

VIL

Input LOW Voltage Level

—

0.8

IIH

Input HIGH Current

VI = VCC

—

± 5

± 10

– 1.2

—

µA

IIL

Input LOW Current

VCC = 3.6V

VI = GND

VO = VCC

VO = GND

—

IOZH

IOZL

VIK

High Impedance Output Current

(3-State Output pins)

Clamp Diode Voltage

Input Hysteresis

VCC = 3.6V

—

µA

—

VCC = 2.3V, IIN = – 18mA

VCC = 3.3V

– 0.7

100

0.1

µA

ICCL

ICCH

ICCZ

∆ICC

VCC = 3.6V

VIN = GND or VCC

Quiescent Power Supply Current

Quiescent Power Supply

Current Variation

One input at VCC − 0.6V,

other inputs at VCC or GND

—

750

µA

NEW16link

NOTE:

1. Typical values are at V^CC= 3.3V, +25°C ambient.

BUS-HOLD CHARACTERISTICS

Symbol

Parameter⁽¹⁾

Test Conditions

Min.

Typ.⁽²⁾

Max.

Unit

IBHH

Bus-Hold Input Sustain Current

VCC = 3.0V

VCC = 2.3V

VCC = 3.6V

VI = 2.0V

VI = 0.8V

VI = 1.7V

VI = 0.7V

VI = 0 to 3.6V

– 75

—

µA

IBHL

– 45

—

IBHH

IBHL

Bus-Hold Input Sustain Current

Bus-Hold Input Overdrive Current

µA

—

IBHHO

IBHLO

—

± 500

µA

NEW16link

NOTES:

1. Pins with Bus-hold are identified in the pin description.

2. Typical values are at V^CC= 3.3V, +25°C ambient.

IDT74ALVCH162721

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

EXTENDED COMMERCIAL TEMPERATURE RANGE

OUTPUT DRIVE CHARACTERISTICS

Symbol

Parameter

Test Conditions⁽¹⁾

IOH = – 0.1mA

Min.

Max.

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

VCC = 2.3V

VCC – 0.2

—

IOH = – 4mA

IOH = – 6mA

IOH = – 4mA

IOH = – 8mA

IOH = – 6mA

IOH = – 12mA

IOL = 0.1mA

IOL = 4mA

1.9

1.7

2.2

—

VCC = 2.7V

VCC = 3.0V

—

2.4

—

VOL

Output LOW Voltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.55

0.4

0.6

0.55

0.8

IOL = 6mA

VCC = 2.7V

VCC = 3.0V

IOL = 4mA

IOL = 8mA

IOL = 6mA

IOL = 12mA

NEW16link

NOTE:

1. V^IHand V^ILmust be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the

appropriate V^CCrange. T^A= – 40°C to + 85°C.

OPERATING CHARACTERISTICS, T = 25 C

VCC = 2.5V ± 0.2V

VCC = 3.3V ± 0.3V

Unit

Symbol

Parameter

Power Dissipation Capacitance

Outputs enabled

Test Conditions

Typical

CPD

CL = 0pF, f = 10Mhz

CPD

Power Dissipation Capacitance

Outputs disabled

(1)

SWITCHING CHARACTERISTICS

VCC = 2.5V ± 0.2V

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

fMAX

150

—

150

—

150

—

MHz

tPLH

tPHL

tPZH

tPZL

tPHZ

tPLZ

tSU

Propagation Delay

CLK to Qx

6.7

7.2

6.3

—

6.2

5.3

5.8

Output Enable Time

OE to Qx

Output Disable Time

OE to Qx

5.4

Setup Time, data before CLK↑

3.4

—

3.6

3.1

—

3.1

2.7

—

tSU

Setup Time CLKEN before CLK↑

Hold Time, data after CLK↑

—

Hold Time, CLKEN after CLK↑

Pulse Width, CLK HIGH or LOW

—

3.3

—

3.3

—

3.3

—

(2)

tSK(o)

Output Skew

500

NOTES:

1. See test circuits and waveforms. T^A= – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74ALVCH162721

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

EXTENDED COMMERCIAL TEMPERATURE RANGE

TEST CIRCUITS AND WAVEFORMS

PROPAGATION DELAY

TEST CONDITIONS

Symbol

(1)

(2)

VCC = 3.3V±0.3V VCC = 2.7V VCC = 2.5V±0.2V

Unit

VLOAD

2 x Vcc

Vcc

SAME PHASE

INPUT TRANSITION

VIH

2.7

1.5

300

2.7

1.5

300

t^PHL

t^PLH

VOH

Vcc / 2

150

OUTPUT

VLZ

VHZ

VOL

t^PHL

t^PLH

150

VIH

OPPOSITE PHASE

INPUT TRANSITION

NEW16link

ALVC Link

TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES

V^LOAD

DISABLE

V^CC

ENABLE

V^IH

V^T

Open

GND

CONTROL

INPUT

500Ω

t^PZL

t^PLZ

V^IN

V^OUT

Pulse^{(1, 2)}

Generator

V^LOAD/2

V^T

D.U.T.

V^LOAD/2

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

V^LZ

V^OL

500Ω

t^PHZ

PZH

R^T

C^L

OUTPUT

NORMALLY

HIGH

V^OH

V^HZ

SWITCH

OPEN

V^T

ALVC Link

DEFINITIONS:

C^L= Load capacitance: includes jig and probe capacitance.

R^T= Termination resistance: should be equal to Z^OUTof the Pulse

ALVC Link

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

Generator.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t^F≤ 2.5ns; t^R≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

SET-UP, HOLD, AND RELEASE TIMES

V^IH

DATA

INPUT

SWITCH POSITION

V^T

t^SU

t^H

Test

Switch

V^IH

V^T

TIMING

INPUT

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other tests

VLOAD

t^REM

V^IH

V^T

ASYNCHRONOUS

CONTROL

GND

Open

V^IH

V^T

SYNCHRONOUS

CONTROL

t^SU

t^H

NEW16link

ALVC Link

OUTPUT SKEW - ^TSK(x)

V^IH

V^T

INPUT

PULSE WIDTH

t^PLH1

t^PHL1

V^OH

V^T

LOW-HIGH-LOW

PULSE

V^T

OUTPUT 1

t^SK(x)

V^OL

t^SK(x)

t^W

V^OH

V^T

HIGH-LOW-HIGH

PULSE

V^T

OUTPUT 2

V^OL

ALVC Link

t^PLH2

t^SK(x) = t^PLH2- t^PLH1or t^PHL2- t^PHL1

t^PHL2

ALVC Link

NOTES:

1. For t^SK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For t^SK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74ALVCH162721

3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

EXTENDED COMMERCIAL TEMPERATURE RANGE

ORDERINGINFORMATION

IDT

ALVC

Bus-Hold

XXX

Device Type Package

Family

Temp. Range

Shrink Small Outline Package (SO56-1)

Thin Shrink Small Outline Package (SO56-2)

Thin Very Small Outline Package (SO56-3)

20-Bit Flip-Flop with 3-State Outputs

Double-Density with Resistors, ±12mA

721

162

Bus-Hold

–40°C to +85°C

CORPORATE HEADQUARTERS

2975 Stender Way

Santa Clara, CA 95054

for SALES:

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com*

*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

74ALVCH162721PF [IDT]

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