74FCT16952ATPAG [IDT]
FAST CMOS 16-BIT REGISTERED TRANSCEIVER;
| 型号： | 74FCT16952ATPAG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS 16-BIT REGISTERED TRANSCEIVER |
| 文件： | 总7页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74FCT16952AT/CT/ET
FAST CMOS
16-BIT REGISTERED
TRANSCEIVER
FEATURES:
• 0.5 MICRON CMOS Technology
DESCRIPTION:
The FCT16952T 16-bit registered transceiver is built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type registered transceivers with
separateinputandoutputcontrolforindependentcontrolofdataflowineither
direction. For example, the A-to-B Enable (xCEAB) must be low to enter
datafromtheAport.xCLKABcontrolstheclockingfunction.WhenxCLKAB
togglesfromlow-to-high, thedatapresentontheAportwillbeclockedinto
theregister. xOEABperformsthe outputenablefunctionontheBport.Data
flowfromtheBporttoAportissimilarbutrequiresusingxCEBA, xCLKBA,
andxOEBAinputs. Full16-bitoperationisachievedbytyingthecontrolpins
of the independent transceivers together.
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage ≤1µA (max.)
• High drive outputs (-32mA IOH, 64mA IOL)
• Power off disable outputs permit “live insertion”
• Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
• Available in SSOP and TSSOP packages
TheFCT16952Tisideallysuitedfordrivinghigh-capacitanceloadsand
low-impedancebackplanes.Theoutputbuffersaredesignedwithpoweroff
disablecapabilityallowing"liveinsertion"ofboardswhenusedasbackplane
drivers.
FUNCTIONAL BLOCK DIAGRAM
54
31
2CEBA
1CEBA
30
55
2CLKBA
1CLKBA
28
1
2OEAB
1OEAB
26
3
2CEAB
1CEAB
2
27
2CLKAB
1CLKAB
29
56
2OEBA
1OEBA
C
CE
C
CE
5
15
2A1
1A1
42
52
D
D
1B1
2B1
C
CE
D
C
CE
D
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2018
1
© 2018 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5442/7
IDT74FCT16952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
PIN DESCRIPTION
PIN CONFIGURATION
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xCLKAB
xCLKBA
xAx
Description
A-to-BOutputEnableInput(ActiveLOW)
B-to-AOutputEnableInput(ActiveLOW)
A-to-B Clock Enable Input (Active LOW)
B-to-A Clock Enable Input (Active LOW)
A-to-B Clock Input
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEAB
1
OEBA
2
1
CLKAB
1CLKBA
3
1
CEAB
1CEBA
GND
4
GND
5
1
A
1
2
1
B
B
1
B-to-A Clock Input
6
A-to-BDataInputsorB-to-A3-StateOutputs
B-to-ADataInputsorA-to-B3-StateOutputs
1
A
1
2
xBx
VCC
7
V
CC
8
1A
1A
1A
3
4
5
1
B
3
4
5
ABSOLUTE MAXIMUM RATINGS(1)
9
1
1
B
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
B
Symbol
(2)
Description
Max
Unit
V
VTERM
Terminal Voltage with Respect to GND
–0.5 to +7
GND
GND
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
1A
1A
1A
2A
2A
2A
6
7
8
1
2
3
1
1
1
2
2
2
B
B
B
B
B
B
6
7
8
1
2
3
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
° C
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
GND
GND
2
2
A
A
A
4
5
6
2
2
2
B
B
B
4
5
CAPACITANCE (TA = +25°C, F = 1.0MHz)
2
6
Symbol
Parameter(1)
Conditions
Typ.
Max. Unit
VCC
V
CC
CIN
Input Capacitance
Output Capacitance
VIN = 0V
3.5
6
8
pF
pF
2
A
A
7
8
2
B
7
8
COUT
VOUT = 0V
3.5
NOTE:
1. This parameter is measured at characterization but not tested.
2
2
B
GND
GND
FUNCTION TABLE(1,3)
Inputs
2CEBA
2
CEAB
Outputs
2
CLKAB
2CLKBA
xCEAB
xCLKAB
xOEAB
xAx
X
xBx
B(2)
B(2)
L
2OEAB
2OEBA
H
X
L
X
L
L
L
X
↑
↑
X
L
L
TOP VIEW
L
L
H
H
PackageType
TSSOP
PackageCode
PAG56
Order Code
PAG
X
H
X
Z
NOTES:
1. A-to-B data flow is shown: B-to-A data flow is similar but uses xCEBA, xCLKBA, and
SSOP
PVG56
PVG
xOEBA.
2. Level of B before the indicated steady-state input conditions were established.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
Z = High-impedance
2
IDT74FCT16952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V 10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
0.8
1
Unit
V
VIL
InputLOWLevel
GuaranteedLogicLOWLevel
VCC = Max.
—
—
—
—
—
—
—
—
–80
—
—
—
V
IIH
InputHIGHCurrent(Inputpins)(5)
Input HIGH Current (I/O pins)(5)
InputLOWCurrent(Inputpins)(5)
InputLOWCurrent(I/Opins)(5)
HighImpedanceOutputCurrent
(3-StateOutputpins)(5)
VI = VCC
—
µA
—
1
IIL
VI = GND
—
1
—
1
IOZH
IOZL
VIK
VCC = Max.
VO = 2.7V
VO = 0.5V
—
1
µA
—
1
ClampDiodeVoltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
–0.7
–140
100
5
–1.2
–250
—
500
V
IOS
ShortCircuitCurrent
mA
mV
µA
VH
InputHysteresis
—
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
OutputDriveCurrent
Output HIGH Voltage
Test Conditions(1)
Min.
Typ.(2) Max.
Unit
IO
VCC = Max., VO = 2.5V(3)
–50
2.5
2.4
2
—
3.5
3.5
3
–180
—
mA
VOH
VCC = Min.
IOH = –3mA
IOH = –15mA
IOH = –32mA(4)
IOL = 64mA
VIN = VIH or VIL
—
V
—
VOH
OutputLOWVoltage
VCC = Min.
—
0.2
0.55
V
VIN = VIH or VIL
IOFF
Input/OutputPowerOffLeakage(5)
VCC = 0V, VIN or VO ≤ 4.5V
—
—
1
µA
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is 5µA at TA = -55°C.
3
IDT74FCT16952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Typ.(2)
Max.
Unit
ΔICC
Quiescent Power Supply
VCC = Max.
VIN = 3.4V(3)
—
0.5
1.5
mA
Current TTL Inputs HIGH
Dynamic Power Supply Current(4)
ICCD
VCC = Max.,
VIN = VCC
—
75
120
µA/
OutputsOpen
VIN = GND
MHz
xOEAB = xOEBA = GND
OneInputToggling
50% Duty Cycle
VCC = Max., Outputs Open
fCP = 10MHz (xCLKAB)
50% Duty Cycle
xOEAB = xCEAB = GND
xOEBA = VCC
IC
TotalPowerSupplyCurrent(6)
VIN = VCC
—
—
—
—
0.8
1.3
3.8
8.3
1.7
3.2
mA
VIN = GND
VIN = 3.4V
VIN = GND
fi = 5MHz
50% Duty Cycle
OneBitToggling
VCC = Max., Outputs Open
fCP = 10MHz (xCLKAB)
50% Duty Cycle
xOEAB = xCEAB = GND
xOEBA = VCC
VIN = VCC
6.5(5)
VIN = GND
VIN = 3.4V
VIN = GND
20(5)
fi = 2.5MHz
50% Duty Cycle
SixteenBitsToggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCPNCP/2 + fiNi)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fi = Input Frequency
Ni = Number of Inputs at fi
4
IDT74FCT16952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
FCT16952AT FCT16952CT FCT16952ET
Symbol
Parameter
Condition(1)
Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit
tPLH
tPHL
Propagation Delay
xCLKAB, xCLKBA to xBx, xAx
CL = 50pF
RL = 500Ω
2
10
10.5
10
2
6.3
1.5
1.5
1.5
1.5
3.7
4.4
3.6
—
ns
ns
ns
ns
tPZH
tPZL
Output EnableTime
xOEBA, xOEAB to xAx, xBx
1.5
1.5
2.5
1.5
1.5
2.5
7
tPHZ
tPLZ
Output Disable Time
xOEBA, xOEAB to xAx, xBx
6.5
—
tSU
Set-up Time, HIGH or LOW
—
xAx, xBx to xCLKAB, xCLKBA
Hold Time, HIGH or LOW
tH
2
3
2
—
—
—
1.5
3
—
—
—
0
2
0
—
—
—
ns
ns
ns
xAx, xBx to xCLKAB, xCLKBA
Set-up Time, HIGH or LOW
tSU
tH
xCEBA, xCEAB, to xCLKAB, xCLKBA
Hold Time, HIGH or LOW
2
xCEBA, xCEAB, to xCLKAB, xCLKBA
Pulse Width HIGH or LOW, xCLKAB or xCLKBA
Output Skew(4)
(3)
tW
3
—
3
—
3
—
ns
ns
tSK(o)
—
0.5
—
0.5
—
0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. This limit is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
IDT74FCT16952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
SWITCH POSITION
7.0V
Test
Switch
Closed
Open
500Ω
500Ω
Open Drain
Disable Low
Enable Low
V
OUT
V
IN
Pulse
Generator
D.U.T.
All Other Tests
50pF
R
T
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
C
L
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
3V
DATA
INPUT
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
t
H
t
SU
1.5V
TIMING
INPUT
t
W
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
t
REM
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
3V
1.5V
0V
PRESET
CLEAR
CLOCK ENABLE
ETC.
Pulse Width
tSU
t
H
Set-up, Hold, and Release Times
ENABLE
DISABLE
3V
3V
SAME PHASE
INPUT TRANSITION
1.5V
0V
CONTROL
INPUT
1.5V
0V
t
PLH
t
PHL
PHL
t
PZL
tPLZ
VOH
OUTPUT
3.5V
1.5V
3.5V
1.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPLH
t
0.3V
0.3V
VOL
3V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT16952AT/CT/ET
FASTCMOS16-BITREGISTEREDTRANSCEIVER
INDUSTRIALTEMPERATURERANGE
ORDERING INFORMATION
XX
FCT
XXX
XXXX
Device Type
X
X
X
Package
Temp. Range
Family
Tube
Tape and Reel
Blank
8
G
Green
PV
PA
Shrink Small Outline Package (PVG48)
Thin Shrink Small Outline Package (PAG48)
952AT
952CT
952ET
16-Bit Registered Transceiver
Double-Density, 5 Volt, High Drive
16
74
− 40°C to +85°C
Orderable Part Information
Speed
(ns)
Pkg.
Code
Pkg.
Type
Temp.
Grade
Orderable Part ID
A
C
E
74FCT16952ATPAG
74FCT16952ATPAG8
74FCT16952ATPVG
74FCT16952ATPVG8
74FCT16952CTPAG
74FCT16952CTPAG8
74FCT16952CTPVG
74FCT16952CTPVG8
74FCT16952ETPAG
74FCT16952ETPAG8
74FCT16952ETPVG
74FCT16952ETPVG8
PAG56
PAG56
PVG56
PVG56
PAG56
PAG56
PVG56
PVG56
PAG56
PAG56
PVG56
PVG56
TSSOP
TSSOP
SSOP
I
I
I
I
I
I
I
I
I
I
I
I
SSOP
TSSOP
TSSOP
SSOP
SSOP
TSSOP
TSSOP
SSOP
SSOP
Datasheet Document History
09/28/2009 Pg. 7
09/25/2017 Pg. 1, 2, 5, 7
Updated the ordering information by removing the "IDT" notation and non RoHS part.
Addedtableunderpinconfigurationdiagramwithdetailedpackageinformation.Updatedtheorderinginformation
diagram by adding Tube, Tape and Reel. Added orderable part information table.
Corrected typo in device name header.
05/07/2018 Pg. 2-7
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800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
7
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