74FCT823CTQG8 [IDT]
QSOP-24, Reel;
| 型号： | 74FCT823CTQG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | QSOP-24, Reel |
| 文件： | 总7页 (文件大小：516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-PERFORMANCE
IDT74FCT823AT/CT
CMOS BUS
INTERFACE REGISTER
DESCRIPTION:
FEATURES:
• A and C grades
The FCT823T series is built using an advanced dual metal CMOS
technology. The FCT823Tseries bus interface registers are designedto
eliminate the extra packages required to buffer existing registers and
provide extra data width for wider address/data paths or buses carrying
parity. The FCT823T is a 9-bit wide buffered register with Clock Enable
(EN)andClear(CLR)–idealforparitybus interfacinginhigh-performance
microprogrammedsystems.
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Power off disable outputs permit "live insertion"
• Available in the SOIC and QSOP packages
TheFCT823Thigh-performanceinterfacefamilycandrivelargecapacitive
loads, while providing low-capacitance bus loading at both inputs and
outputs.Allinputs haveclampdiodes andalloutputs aredesignedforlow-
capacitancebus loadinginhigh-impedancestate.
FUNCTIONALBLOCKDIAGRAM
D0
DN
EN
CLR
CL
CL
D
Q
D
Q
CP
CP
Q
Q
CP
OE
Y0
YN
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
February 19, 2009
1
© 2006 Integrated Device Technology, Inc.
DSC-5487/4
IDT74FCT823AT/CT
HIGH-PERFORMANCECMOSBUSINTERFACEREGISTER
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +7
24
23
22
21
20
19
18
17
16
15
14
13
1
OE
D0
VCC
Y0
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
2
3
4
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
° C
mA
D1
D2
Y1
Y2
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
D3
D4
D5
Y3
Y4
Y5
5
6
7
8
9
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
D6
D7
Y6
Y7
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
D8
Y8
10
11
CIN
VIN = 0V
6
10
12
pF
pF
CLR
EN
CP
COUT
VOUT = 0V
8
GND
12
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ QSOP
TOP VIEW
PINDESCRIPTION
FUNCTIONTABLE(1)
Internal/
Pin Names
I/O
Description
Inputs
EN
L
Outputs
Dx
I
I
D Flip-Flop Data Inputs
OE
H
H
H
L
CLR
H
H
L
Dx
L
CP
↑
↑
X
X
X
X
↑
Qx
Yx
Z
Function
CLR
When the clear input is LOW and OE is LOW, the
Qx outputs are LOW. When the clear input is HIGH,
data can be entered into the register.
L
H
HighZ
L
H
X
X
X
X
L
Z
CP
I
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
X
L
Z
Clear
Hold
Load
L
X
L
L
Yx
O
I
Register 3-State Outputs
H
L
H
H
H
H
H
H
H
N C
NC
L
Z
EN
Clock Enable. When the clock enable is LOW, data
on the Dx output is transferred to the Qx output on the
LOW-to-HIGH transition. When the clock enable is
HIGH, the Qx outputs do not change state, regardless
of the data or clock input transitions.
H
NC
Z
H
H
L
L
L
H
L
↑
↑
↑
H
Z
L
L
L
L
L
H
H
H
OE
I
Output Control. When the OE is HIGH, the Yx
outputs are in the high-impedance state. When the
OE is LOW, the TRUE register data is present at the
Yx outputs.
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
NC = No Change
↑ = LOW-to-HIGH Transition
Z = High Impedance
2
IDT74FCT823AT/CT
HIGH-PERFORMANCECMOSBUSINTERFACEREGISTER
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%
Symbol
VIH
VIL
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
0.8
1
Unit
V
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
—
—
—
—
—
—
V
IIH
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current(4)
VI = 2.7V
VI = 0.5V
VI = 2.7V
VI = 0.5V
—
µA
µA
µA
IIL
VCC = Max.
—
1
IOZH
IOZL
II
VCC = Max., VI = VCC (Max.)
—
1
—
1
Input HIGH Current(4)
Clamp Diode Voltage
Input Hysteresis
VCC = Max., VI = VCC (Max.)
VCC = Min., IIN = –18mA
—
1
µA
V
VIK
VH
–0.7
200
0.01
–1.2
—
1
—
mV
mA
ICC
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
IOH = –8mA
Min.
2.4
2
Typ.(2)
3.3
Max.
—
Unit
VOH
OutputHIGHVoltage
VCC = Min
V
VIN = VIH or VIL
VCC = Min
IOH = –15mA
IOL = 48mA
3
—
VOL
Output LOWVoltage
—
0.3
0.5
V
VIN = VIH or VIL
(3)
IOS
Short Circuit Current
Input/Output Power Off Leakage(5)
VCC = Max., VO = GND
–60
—
–120
—
–225
1
mA
µA
IOFF
VCC = 0V, VIN or VO ≤ 4.5V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
3
IDT74FCT823AT/CT
HIGH-PERFORMANCECMOSBUSINTERFACEREGISTER
INDUSTRIALTEMPERATURERANGE
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ΔICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V
—
0.5
2
mA
(3)
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
OE = EN = GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
VIN = VCC
VIN = GND
—
1.5
3.5
5.5
mA
Outputs Open
fCP = 10MHz
50% Duty Cycle
OE = EN = GND
One Bit Toggling
at fi = 5MHz
VIN = 3.4V
VIN = GND
—
—
2
(5)
7.3
VCC = Max.
Outputs Open
fCP = 10MHz
VIN = VCC
VIN = GND
3.8
50% Duty Cycle
(5)
16.3
OE = EN = GND
Eight Bits Toggling
at fi = 2.5MHz
VIN = 3.4V
VIN = GND
—
6
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ΔICC DHNT + ICCD (fCP/2+ fiNi)
ICC = Quiescent Current
ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT74FCT823AT/CT
HIGH-PERFORMANCECMOSBUSINTERFACEREGISTER
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
FCT823AT
FCT823CT
(2)
(2)
Symbol
tPLH
Parameter
PropagationDelay
Condition(1)
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
Min.
Max.
Min.
Max.
Unit
1.5
10
1.5
6
ns
tPHL
CP to Yx (OE = LOW)
1.5
20
1.5
12.5
ns
tSU
tH
Set-up Time HIGH or LOW Dx to CP
Hold Time HIGH or LOW Dx to CP
Set-up Time HIGH or LOW EN to CP
Hold Time HIGH or LOW EN to CP
Propagation Delay, CLR to Yx
Recovery Time CLR to CP
4
2
—
—
—
—
14
3
1.5
3
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSU
tH
4
2
0
tPHL
tREM
tW
1.5
6
1.5
6
—
—
—
12
—
—
—
7
Clock Pulse Width HIGH or LOW
CLR Pulse WidthLOW
7
6
tW
6
6
tPZH
tPZL
Output Enable Time OE to Yx
CL = 50pF
RL = 500Ω
CL = 300pF(4)
RL = 500Ω
CL = 5pF(4)
RL = 500Ω
CL = 50pF
RL = 500Ω
1.5
1.5
1.5
1.5
1.5
23
7
1.5
1.5
1.5
12.5
6
ns
ns
ns
tPHZ
tPLZ
Output Disable Time OE to Yx
8
6.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. This condition is guaranteed but not tested.
5
IDT74FCT823AT/CT
HIGH-PERFORMANCECMOSBUSINTERFACEREGISTER
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
VCC
SWITCHPOSITION
7.0V
Test
Switch
Closed
Open
500W
Open Drain
Disable Low
Enable Low
VOUT
VIN
Pulse
Generator
D.U.T
.
All Other Tests
50pF
500W
T
R
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
L
C
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal Link
Test Circuits for All Outputs
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Octal Link
Octal Link
Set-Up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
VOH
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
0V
Octal Link
Octal Link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT74FCT823AT/CT
HIGH-PERFORMANCECMOSBUSINTERFACEREGISTER
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
XXXX
X
FCT
Temp. Range
Device Type
Package
Small Outline IC
SOIC - Green
Quarter-size Small Outline Package
QSOP - Green
SO
SOG
Q
QG
823AT
823CT
Bus Interface Register
- 40°C to +85°C
74
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7
相关型号：
74FCT825AFCQR
IC FCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP24, CERAMIC, FP-24, Bus Driver/Transceiver
TI
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