74LVC16244APV [IDT]
Bus Driver, LVC/LCX/Z Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, SSOP-48;
| 型号： | 74LVC16244APV |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Bus Driver, LVC/LCX/Z Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, SSOP-48 光电二极管 |
| 文件： | 总6页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 16-BIT
BUFFER/DRIVER
IDT74LVC16244A
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
DESCRIPTION:
FEATURES:
The LVC16244A16-bitbuffer/driveris builtusingadvanceddualmetal
CMOS technology. The LVC16244A is designed specifically to improve
boththeperformanceanddensityof3-statememoryaddressdrivers,clock
drivers, and bus-oriented receivers and transmitters. The device can be
usedasfour4-bitbuffers,two8-bitbuffers,orone16-bitbuffer.Thisdevice
provides true outputs and symmetrical active-low output-enable (OE)
inputs.
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V
devices. This featureallows theuseofthedeviceas atranslatorinamixed
3.3V/5Vsupplysystem.
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
The LVC16244Ahas beendesignedwitha ±24mAoutputdriver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
25
1
1OE
3OE
13
47
2
36
1A1
3A1
1Y1
1Y2
3Y1
3Y2
46
44
3
5
6
35
33
14
16
1A2
1A3
3A2
3A3
1Y3
1Y4
3Y3
3Y4
43
32
24
17
1A4
3A4
48
41
2OE
2A1
4OE
4A1
8
30
29
27
19
2Y1
2Y2
4Y1
4Y2
20
22
40
38
9
2A2
2A3
4A2
4A3
11
2Y3
2Y4
4Y3
4Y4
12
23
37
26
2A4
4A4
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MARCH 2006
1
© 2006 Integrated Device Technology, Inc.
DSC-4726/5
IDT74LVC16244A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
–0.5 to +6.5
–0.5 to +6.5
–65 to +150
–50 to +50
–50
(3)
1
2
48
47
46
45
44
VTERM
V
1OE
1Y1
2OE
1A1
1A2
TSTG
IOUT
° C
mA
mA
DC Output Current
3
1Y2
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
GND
4
5
6
GND
1A3
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
1Y3
NOTES:
1Y4
1A4
43
42
41
40
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VCC
7
VCC
2A1
8
2Y1
2Y2
2. VCC terminals.
3. All terminals except VCC.
9
2A2
GND
2A3
2A4
3A1
10
39
38
37
36
GND
2Y3
2Y4
3Y1
3Y2
11
12
13
14
15
16
17
18
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
COUT
CI/O
6.5
35
34
3A2
6.5
GND
NOTE:
GND
1. As applicable to the device type.
3A3
33
3Y3
3Y4
32
31
30
3A4
PINDESCRIPTION
Pin Names
VCC
VCC
4A1
Description
4Y1
4Y2
19
20
21
22
23
xAx
xYx
xOE
Data Inputs
3-State Outputs
29
28
27
26
25
4A2
3-State Output Enable Inputs (Active LOW)
GND
GND
4Y3
4A3
4A4
4Y4
(1)
FUNCTION TABLE (EACH 4-BIT BUFFER)
24
4OE
3OE
Inputs
Outputs
xOE
xAx
xYx
SSOP/ TSSOP/ TVSOP
TOP VIEW
L
L
L
L
H
H
H
X
Z
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2
IDT74LVC16244A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
5
µA
µ A
IOZH
IOZL
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
10
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
50
µ A
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
(2)
3.6 ≤ VIN ≤ 5.5V
—
—
—
—
10
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
500
µ A
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC– 0.2
2
Max.
—
Unit
VOH
OutputHIGHVoltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2.2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74LVC16244A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
PowerDissipationCapacitanceperBuffer/DriverOutputsenabled
PowerDissipationCapacitanceperBuffer/DriverOutputsdisabled
CL = 0pF, f = 10Mhz
34
3
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
Max.
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Min.
Max.
Unit
PropagationDelay
xAx to xYx
—
4.7
1.1
4.1
ns
ns
ns
ns
tPHL
tPZH
OutputEnableTime
xOE to xYx
—
—
—
5.8
6.2
—
1
4.6
5.8
1
tPZL
tPHZ
OutputDisableTime
1.8
—
tPLZ
xOE to xYx
(2)
tSK(o)
OutputSkew
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC16244A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
(1)
(1)
(2)
Symbol VCC =3.3V±0.3V VCC =2.7V VCC =2.5V±0.2V Unit
tPHL
VLOAD
VIH
6
6
2 x Vcc
Vcc
V
V
tPLH
VOH
VT
VOL
OUTPUT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
VT
Vcc / 2
150
V
tPHL
tPLH
VLZ
VHZ
CL
mV
mV
pF
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
150
30
LVC Link
VLOAD
Open
GND
Propagation Delay
VCC
DISABLE
ENABLE
VIH
VT
0V
500Ω
CONTROL
INPUT
VIN
VOUT
(1, 2)
Pulse
tPZL
tPLZ
D.U.T.
Generator
VLOAD/2
VT
VLOAD/2
VOL+VLZ
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
500Ω
RT
CL
tPHZ
tPZH
VOH
VOH-VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
LVC Link
VT
0V
Test Circuit for All Outputs
0V
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
SWITCHPOSITION
DATA
INPUT
VT
0V
Test
Switch
VLOAD
GND
Open
tSU
tH
VIH
TIMING
INPUT
Open Drain
Disable Low
Enable Low
VT
0V
tREM
VIH
ASYNCHRONOUS
CONTROL
VT
Disable High
Enable High
0V
VIH
SYNCHRONOUS
CONTROL
All Other Tests
VT
tSU
0V
tH
LVC Link
VIH
VT
0V
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
VOH
LOW-HIGH-LOW
VT
VOL
VT
PULSE
OUTPUT 1
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
OUTPUT 2
LVC Link
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC16244A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
Device Type Package
X
XX
LVC
XXXX
IDT
XX
Bus-Hold
Family
Temp. Range
Shrink Small Outline Package
PV
SSOP - Green
Thin Shrink Small Outline Package
PVG
PA
TSSOP - Green
Thin Very Small Outline Package
TVSOP - Green
PAG
PF
PFG
244A 16-Bit Buffer/Driver with 3-State Outputs
16
Double-Density, 24mA
No Bus-hold
Blank
74
-40°C to +85°C
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6
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