74LVC244APG8 [IDT]

TSSOP-20, Reel;
74LVC244APG8
型号: 74LVC244APG8
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

TSSOP-20, Reel

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中文:  中文翻译
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3.3V CMOS  
OCTAL BUFFER/DRIVER  
IDT74LVC244A  
WITH 3-STATE OUTPUTS,  
5 VOLT TOLERANT I/O  
DESCRIPTION:  
FEATURES:  
TheLVC244Adeviceis organizedas two4-bitlinedrivers withseparate  
output-enable (OE)inputs.WhenOE is low,the device passes data from  
the Ainputs tothe Youtputs.WhenOEis high,the outputs are inthe high-  
impedancestate.  
• 0.5 MICRON CMOS Technology  
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using  
machine model (C = 200pF, R = 0)  
VCC = 3.3V ± 0.3V, Normal Range  
The LVC244A has been designed with a ±24mA output driver. This  
driver is capable of driving a moderate to heavy load while maintaining  
speedperformance.  
To ensure the high-impedance state during power up or power down,  
OE shouldbe tiedtoVCC througha pullupresistor;the minimumvalue of  
the resistoris determinedbythe current-sinkingcapabilityofthe driver.  
Inputs canbe drivenfromeither3.3Vor5Vdevices.This feature allows  
theuseofthisdeviceasatranslatorinamixed3.3V/5Vsystemenvironment.  
VCC = 2.7V to 3.6V, Extended Range  
• CMOS power levels (0.4μ W typ. static)  
• Rail-to-rail output swing for increased noise margin  
All inputs, outputs, and I/O are 5V tolerant  
• Supports hot insertion  
Available in SOIC, SSOP, QSOP, and TSSOP packages  
DRIVE FEATURES:  
High Output Drivers: ±24mA  
• Reduced system switching noise  
APPLICATIONS:  
• 5V and 3.3V mixed voltage systems  
Data communication and telecommunication systems  
FUNCTIONALBLOCKDIAGRAM  
1
19  
1OE  
2OE  
18  
9
2
11  
1Y1  
1Y2  
1Y3  
1Y4  
1A1  
2A1  
2A2  
2A3  
2A4  
2Y1  
2Y2  
2Y3  
2Y4  
16  
14  
4
6
8
13  
15  
17  
7
5
1A2  
1A3  
3
12  
1A4  
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
INDUSTRIAL TEMPERATURE RANGE  
OCTOBER 1999  
1
© 1999 Integrated Device Technology, Inc.  
DSC-4614/3  
IDT74LVC244A  
3.3VCMOSOCTALBUFFER/DRIVERWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
ABSOLUTEMAXIMUMRATINGS(1)  
PINCONFIGURATION  
Symbol  
VTERM  
TSTG  
Description  
Terminal Voltage with Respect to GND  
Storage Temperature  
Max  
Unit  
V
–0.5 to +6.5  
–65 to +150  
–50 to +50  
–50  
° C  
mA  
mA  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
2
VCC  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
IOUT  
DC Output Current  
IIK  
IOK  
Continuous Clamp Current,  
VI < 0 or VO < 0  
ICC  
ISS  
Continuous Current through each  
VCC or GND  
±100  
mA  
3
4
NOTE:  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect reliability.  
5
6
2Y2  
1A4  
7
8
CAPACITANCE (TA = +25°C, F = 1.0MHz)  
Symbol  
Parameter(1)  
Conditions  
VIN = 0V  
VOUT = 0V  
VIN = 0V  
Typ.  
Max. Unit  
2Y1  
9
CIN  
Input Capacitance  
Output Capacitance  
I/O Port Capacitance  
4.5  
6
8
8
pF  
pF  
pF  
COUT  
CI/O  
5.5  
GND  
10  
6.5  
NOTE:  
1. As applicable to the device type.  
SOIC/ SSOP/ QSOP/ TSSOP  
TOP VIEW  
PINDESCRIPTION  
Pin Names  
Description  
xAx  
xYx  
xOE  
Data Inputs  
3-State Outputs  
Output Enable Inputs (Active LOW)  
(1)  
FUNCTION TABLE (EACH BUFFER)  
Inputs  
Outputs  
xYx  
xOE  
xAx  
L
L
H
L
H
L
H
X
Z
NOTES:  
1. H = HIGH Voltage Level  
X = Don’t Care  
L = LOW Voltage Level  
Z = High-Impedance  
2
IDT74LVC244A  
INDUSTRIALTEMPERATURERANGE  
3.3VCMOSOCTALBUFFER/DRIVERWITH3-STATEOUTPUTS  
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE  
FollowingConditionsApplyUnlessOtherwiseSpecified:  
OperatingCondition:TA = –40°C to +85°C  
Symbol  
Parameter  
Test Conditions  
Min.  
1.7  
2
Typ.(1)  
Max.  
Unit  
VIH  
Input HIGH Voltage Level  
VCC = 2.3V to 2.7V  
VCC = 2.7V to 3.6V  
V
VIL  
Input LOW Voltage Level  
Input Leakage Current  
VCC = 2.3V to 2.7V  
VCC = 2.7V to 3.6V  
0.7  
0.8  
V
IIH  
IIL  
VCC = 3.6V  
VI = 0 to 5.5V  
5
µA  
µ A  
IOZH  
IOZL  
High Impedance Output Current  
(3-State Output pins)  
VCC = 3.6V  
VO = 0 to 5.5V  
10  
IOFF  
VIK  
VH  
Input/Output Power Off Leakage  
Clamp Diode Voltage  
VCC = 0V, VIN or VO 5.5V  
50  
µ A  
V
VCC = 2.3V, IIN = –18mA  
–0.7  
–1.2  
Input Hysteresis  
VCC = 3.3V  
VCC = 3.6V  
100  
10  
mV  
µA  
ICCL  
ICCH  
ICCZ  
Quiescent Power Supply Current  
VIN = GND or VCC  
(2)  
3.6 VIN 5.5V  
10  
ΔICC  
Quiescent Power Supply Current  
Variation  
One input at VCC - 0.6V, other inputs at VCC or GND  
500  
µ A  
NOTES:  
1. Typical values are at VCC = 3.3V, +25°C ambient.  
2. This applies in the disabled state only.  
OUTPUTDRIVECHARACTERISTICS  
Symbol  
Parameter  
TestConditions(1)  
Min.  
VCC – 0.2  
2
Max.  
Unit  
VOH  
OutputHIGHVoltage  
VCC = 2.3V to 3.6V  
IOH = – 0.1mA  
IOH = – 6mA  
IOH = – 12mA  
V
VCC = 2.3V  
VCC = 2.3V  
VCC = 2.7V  
VCC = 3V  
1.7  
2.2  
2.4  
VCC = 3V  
IOH = – 24mA  
IOL = 0.1mA  
IOL = 6mA  
2.2  
VOL  
OutputLOWVoltage  
VCC = 2.3V to 3.6V  
VCC = 2.3V  
0.2  
0.4  
0.7  
0.4  
0.55  
V
IOL = 12mA  
IOL = 12mA  
IOL = 24mA  
VCC = 2.7V  
VCC = 3V  
NOTE:  
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.  
TA = – 40°C to + 85°C.  
3
IDT74LVC244A  
3.3VCMOSOCTALBUFFER/DRIVERWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C  
Symbol  
Parameter  
Test Conditions  
Typical  
Unit  
CPD  
PowerDissipationCapacitanceperBuffer/DriverOutputsenabled  
PowerDissipationCapacitanceperBuffer/DriverOutputsdisabled  
CL = 0pF, f = 10Mhz  
44  
2
pF  
CPD  
SWITCHINGCHARACTERISTICS(1)  
VCC = 2.7V  
Max.  
VCC = 3.3V ± 0.3V  
Symbol  
tPLH  
Parameter  
Min.  
Min.  
Max.  
Unit  
PropagationDelay  
xAx to xYx  
6.9  
1.5  
5.9  
ns  
ns  
ns  
ps  
tPHL  
tPZH  
OutputEnableTime  
xOE to xYx  
8.6  
6.8  
1.5  
1.5  
7.6  
6.5  
500  
tPZL  
tPHZ  
OutputDisableTime  
tPLZ  
xOE to xYx  
(2)  
tSK(o)  
OutputSkew  
NOTES:  
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.  
2. Skew between any two outputs of the same package and switching in the same direction.  
4
IDT74LVC244A  
INDUSTRIALTEMPERATURERANGE  
3.3VCMOSOCTALBUFFER/DRIVERWITH3-STATEOUTPUTS  
TESTCIRCUITSANDWAVEFORMS  
TESTCONDITIONS  
VIH  
VT  
0V  
SAME PHASE  
INPUT TRANSITION  
(1)  
(1)  
(2)  
tPHL  
tPHL  
Symbol VCC =3.3V±0.3V VCC =2.7V VCC =2.5V±0.2V Unit  
tPLH  
tPLH  
VOH  
VT  
VOL  
OUTPUT  
VLOAD  
VIH  
6
6
2 x Vcc  
Vcc  
V
V
2.7  
1.5  
300  
300  
50  
2.7  
1.5  
300  
300  
50  
VT  
Vcc / 2  
150  
V
VIH  
VT  
0V  
OPPOSITE PHASE  
INPUT TRANSITION  
VLZ  
VHZ  
CL  
mV  
mV  
pF  
150  
LVC Link  
30  
Propagation Delay  
VLOAD  
Open  
GND  
VCC  
DISABLE  
ENABLE  
VIH  
VT  
0V  
CONTROL  
INPUT  
500Ω  
tPZL  
tPLZ  
VIN  
VOUT  
(1, 2)  
Pulse  
D.U.T.  
VLOAD/2  
VLOAD/2  
Generator  
OUTPUT  
NORMALLY  
LOW  
SWITCH  
VLOAD  
VT  
VOL+VLZ  
VOL  
500Ω  
RT  
tPHZ  
tPZH  
CL  
VOH  
VOH-VHZ  
OUTPUT  
NORMALLY  
HIGH  
SWITCH  
GND  
VT  
0V  
LVC Link  
0V  
Test Circuit for All Outputs  
LVC Link  
DEFINITIONS:  
CL = Load capacitance: includes jig and probe capacitance.  
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.  
Enable and Disable Times  
NOTE:  
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.  
NOTES:  
1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.  
2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.  
VIH  
DATA  
INPUT  
SWITCHPOSITION  
VT  
0V  
Test  
Switch  
VLOAD  
GND  
Open  
tSU  
tH  
VIH  
TIMING  
INPUT  
Open Drain  
Disable Low  
Enable Low  
VT  
0V  
tREM  
VIH  
ASYNCHRONOUS  
CONTROL  
VT  
Disable High  
Enable High  
0V  
VIH  
SYNCHRONOUS  
CONTROL  
All Other Tests  
VT  
tSU  
0V  
tH  
VIH  
LVC Link  
VT  
0V  
Set-up, Hold, and Release Times  
INPUT  
tPLH1  
tPHL1  
VOH  
VT  
VOL  
LOW-HIGH-LOW  
OUTPUT 1  
VT  
PULSE  
tSK (x)  
tSK (x)  
VOH  
tW  
VT  
VOL  
HIGH-LOW-HIGH  
PULSE  
OUTPUT 2  
VT  
LVC Link  
tPLH2  
tPHL2  
Pulse Width  
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1  
LVC Link  
Output Skew - tSK(X)  
NOTES:  
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.  
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.  
5
IDT74LVC244A  
3.3VCMOSOCTALBUFFER/DRIVERWITH3-STATEOUTPUTS  
INDUSTRIALTEMPERATURERANGE  
ORDERINGINFORMATION  
IDT  
XX  
LVC  
X
XXXX  
XX  
Device Type Package  
Temp. Range  
Bus-Hold  
SO  
Small Outline IC (gull wing)  
SOG  
PY  
SOIC - Green  
Shrink Small Outline Package  
PYG  
Q
QG  
SSOP - Green  
Quarter Size Small Outline Package  
QSOP - Green  
PG  
PGG  
Thin Shrink Small Outline Package  
TSSOP - Green  
244A  
Octal Buffer/Driver with 3-State Outputs, 24mA  
Blank  
74  
No Bus-hold  
–40°C to +85°C  
CORPORATE HEADQUARTERS  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
for SALES:  
800-345-7015 or 408-284-8200  
fax: 408-284-2775  
www.idt.com  
for Tech Support:  
logichelp@idt.com  
6

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