74LVCH16540APV [IDT]
SSOP-48, Tube;
| 型号： | 74LVCH16540APV |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | SSOP-48, Tube |
| 文件： | 总6页 (文件大小：65K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74LVCH16540A
3.3V CMOS16-BIT
BUFFER/DRIVER WITH 3-STATE
OUTPUTS, 5 VOLT TOLERANT I/O
AND BUS-HOLD
DESCRIPTION:
This 16-bit buffer/driver is built using advanced dual metal CMOS
technology. The 3-state control gate is a 2-input AND gate with active-low
inputs so that if either output-enable (OE1 or OE2) input is high, all
correspondingoutputsareinthehigh-impedancestate.Toensurethehigh-
impedancestateduringpoweruporpowerdown,OEshouldbetiedtoVcc
through a pullup resistor; the minimum value of the resistor is determined
by the current-sinking capabiltiy of the driver.
FEATURES:
–
–
Typical tSK(0) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
Extended commercial range of -40°C to +85°C
VCC = 3.3V ±0.3V, Normal Range
–
–
–
–
–
–
–
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4µW typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
All pins of this 16-bit buffer/driver can be driven from either 3.3V or 5V
devices. Thisfeatureallowstheuseofthisdeviceasatranslatorinamixed
3.3V/5V supply system.
Drive Features for LVCH16540A:
The LVCH16540A has been designed with a ±24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
–
–
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
The LVCH16540A has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs
and eliminates the need for pull-up/down resistors.
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
1
4
1OE1
2E1
48
25
1OE2
2OE2
47
36
13
1Y1
2Y1
1A1
2A1
TO SEVEN R ANNELS
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OCTOBER 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4622/-
IDT74LVCH16540A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Max.
Unit
V
Terminal Voltage with Respect to GND
Storage Temperature
– 0.5 to +6.5
– 65 to +150
°C
1
2
48
47
46
45
44
1OE1
1Y1
1OE2
1A1
IOUT
DC Output Current
– 50 to +50
– 50
mA
mA
IIK
IOK
ICC
Continuous Clamp Current,
VI < 0 or VO < 0
3
1Y2
1A2
Continuous Current through
±100
mA
GND
4
5
6
ISS
each VCC or GND
GND
1A3
LVC Link
1Y3
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
1Y4
1A4
43
42
41
40
VCC
7
VCC
1A5
8
1Y5
1Y6
9
1A6
GND
1A7
CAPACITANCE (TA = +25OC, f = 1.0MHz)
10
39
38
37
36
GND
1Y7
1Y8
2Y1
2Y2
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
11
12
13
14
15
16
17
18
SO48-1
SO48-2
SO48-3
COUT
CI/O
Output
Capacitance
I/O Port
VOUT = 0V
VIN = 0V
6.5
8
pF
1A8
6.5
8
pF
2A1
Capacitance
LVC Link
35
34
2A2
NOTE:
1. As applicable to the device type.
GND
GND
2A3
33
2Y3
2Y4
PIN DESCRIPTION
32
31
30
2A4
Pin Names
Description
VCC
VCC
2A5
xOEx
xAx
3–State Output Enable Inputs (Active LOW)
Data Inputs(1)
2Y5
2Y6
19
20
21
22
23
xYx
3-State Outputs
29
28
27
26
25
2A6
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs,
outputs, or I/Os.
GND
GND
2Y7
2A7
2A8
(1)
FUNCTION TABLE (each 8-bit section)
2Y8
24
Inputs
xOE2
Outputs
xYx
2OE1
2OE2
xOE1
xAx
L
L
L
L
L
H
L
H
SSOP/ TSSOP/ TVSOP
TOP VIEW
H
X
X
H
X
Z
Z
X
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
c
1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVCH16540A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40OC to +85OC
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max. Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
—
V
2
—
—
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
—
—
—
0.7
0.8
±5
V
IIH
IIL
VI = 0 to 5.5V
µA
µA
IOZH
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOZL
IOFF
VIK
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
µA
V
VH
Input Hysteresis
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
10
(2)
—
—
—
—
10
3.6 ≤ VIN ≤ 5.5V
∆ICC
Quiescent Power Supply
Current Variation
One input at VCC - 0.6V
other inputs at VCC or GND
500
µA
LVC Link
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
Parameter(1)
Test Conditions
Min.
Typ.(2)
Max.
Unit
IBHH
Bus-Hold Input Sustain Current
VCC = 3.0V
VCC = 2.3V
VCC = 3.6V
VI = 2.0V
VI = 0.8V
VI = 1.7V
VI = 0.7V
VI = 0 to 3.6V
– 75
75
—
—
—
—
—
—
—
—
µA
IBHL
IBHH
IBHL
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
—
µA
—
—
IBHHO
IBHLO
—
± 500
µA
LVC Link
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74LVCH16540A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Output HIGH Voltage
Test Conditions(1)
IOH = – 0.1mA
Min.
Max.
Unit
VOH
VCC = 2.3V to 3.6V
VCC = 2.3V
VCC – 0.2
—
V
IOH = – 6mA
IOH = – 12mA
2
—
—
VCC = 2.3V
1.7
2.2
2.4
2.2
—
VCC = 2.7V
—
VCC = 3.0V
—
VCC = 3.0V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3.0V
—
—
LVC Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
OPERATING CHARACTERISTICS, V
= 3.3V ± 0.3V, T = 25°C
CC
A
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
Power Dissipation Capacitance per buffer/driver Outputs enabled
Power Dissipation Capacitance per buffer/driver Outputs disabled
CL = 0pF, f = 10Mhz
34
pF
CPD
2
pF
SWITCHING CHARACTERISTICS (1)
VCC = 2.7V
VCC = 3.3V±0.3V
Min.
Symbol
tPLH
tPHL
Parameter
Min.
Max.
Max.
Unit
Propagation Delay
xAx to xYx
4.5
1
3.7
ns
tPZH
tPZL
Output Enable Time
xOEx to xYx
Output Disable Time
xOEx to xYx
5.9
6.3
1.5
1.6
4.8
5.9
500
ns
tPHZ
tPLZ
ns
ps
tSK(o) Output Skew(2)
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH16540A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
PROPAGATIONDELAY
VIH
VT
0V
SAME PHASE
(1)
(1)
(2)
VCC = 3.3V ±0.3V VCC = 2.7V VCC = 2.5V ±0.2V
Symbol
Unit
INPUT TRANSITION
tPHL
tPHL
tPLH
VLOAD
6
6
2 x Vcc
Vcc
V
VOH
VT
OUTPUT
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VOL
VCC / 2
150
V
tPLH
VIH
VT
0V
VLZ
VHZ
CL
mV
mV
OPPOSITE PHASE
INPUT TRANSITION
150
30
pF
LVC Link
LVC Link
ENABLEANDDISABLETIMES
TEST CIRCUITS FOR ALL OUTPUTS
DISABLE
ENABLE
VLOAD
VIH
VT
VCC
CONTROL
INPUT
Open
GND
0V
tPZL
tPLZ
500Ω
VIN
VLOAD/2
VT
VOUT
VLOAD/2
OUTPUT
NORMALLY
LOW
Pulse (1, 2)
Generator
SWITCH
CLOSED
D.U.T.
VLZ
VOL
tPHZ
tPZH
500Ω
RT
VOH
VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
CL
VT
0V
0V
LVC Link
DEFINITIONS:
LVC Link
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTE:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SET-UP, HOLD, AND RELEASE TIMES
VIH
VT
0V
DATA
INPUT
SWITCHPOSITION
tSU
tH
Test
Switch
VIH
VT
0V
TIMING
INPUT
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
GND
VIH
VT
0V
SYNCHRONOUS
CONTROL
Open
tSU
tH
LVC Link
LVC Link
OUTPUT SKEW - tsk (x)
VIH
VT
0V
PULSEWIDTH
INPUT
tPLH1
tPHL1
VOH
LOW-HIGH-LOW
PULSE
VT
VT
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
tSK (x)
tW
VOH
HIGH-LOW-HIGH
PULSE
VT
VT
VOL
LVC Link
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVCH16540A
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
XX
X
XX
XXXX
XX
LVC
IDT
Device Type Package
Temp. Range
Bus-Hold
Family
Shrink Small Outline Package (SO48-1)
Thin Shrink Small Outline Package (SO48-2)
Thin Very Small Outline Package (SO48-3)
PV
PA
PF
16-Bit Buffer/Driver with 3 State Outputs
Double-Density with Resistors, ±24mA
540A
16
Bus-hold
H
74
-40°C to +85°C
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6
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