74LVCH373ASO [IDT]
SOIC-20, Tube;
| 型号： | 74LVCH373ASO |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | SOIC-20, Tube |
| 文件： | 总6页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS OCTAL
IDT74LVCH373A
TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS, 5 VOLT
TOLERANT I/O AND BUS-HOLD
DESCRIPTION:
FEATURES:
–
–
0.5 MICRON CMOS Technology
The LVCH373A octal transparent D-type latch is built using advanced
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
1.27mm pitch SOIC, 0.65mm pitch SSOP,
0.635mm pitch QSOP, 0.65mm pitch TSSOP packages
Extended commercial range of – 40°C to +85°C
VCC = 3.3V ±0.3V, Normal Range
dualmetalCMOStechnology.Whilethelatch-enable(LE)inputishigh,the
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs
are latched at the logic levels set up at the D inputs.
–
–
–
–
–
–
–
–
A buffered output-enable (OE) input can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a high-
impedancestate.Inthehigh-impedancestate,theoutputsneitherloadnor
drivethebuslinessignificantly. OEdoesnotaffecttheinternaloperations
of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
VCC = 2.3V to 3.6V, Extended Range
CMOS power levels (0.4µW typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
The LVCH373A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
Drive Features for LVCH373A:
–
–
High Output Drivers: ±24mA
Reduced system switching noise
Inputscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows
the use of this device as a translator in a mixed 3.3V/5V system environ-
ment.
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
The LVCH373A has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance.Thispreventsfloatinginputs
and eliminates the need for pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
OE
11
LE
C1
1D
2
1Q
1D
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OCTOBER 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4630/-
IDT74LVCH373A
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
EXTENDEDCOMMERCIALTEMPERATURERANGE
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Max.
Unit
V
Terminal Voltage with Respect to GND
Storage Temperature
– 0.5 to +6.5
– 65 to +150
20
19
18
17
16
15
14
13
12
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
1
OE
1Q
°C
IOUT
DC Output Current
– 50 to +50
– 50
mA
mA
2
3
4
IIK
IOK
ICC
Continuous Clamp Current,
VI < 0 or VO < 0
1D
Continuous Current through
±100
mA
2D
ISS
each VCC or GND
8LVC
SO20-2
SO20-7
SO20-8
SO20-9
NOTE:
2Q
5
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
3Q
6
3D
7
4D
8
4Q
9
CAPACITANCE (TA = +25°C, f = 1.0MHZ)
Symbol
GND
Parameter(1)
Conditions
Typ.
Max. Unit
10
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
CI/O
Output
Capacitance
I/O Port
VOUT = 0V
VIN = 0V
5.5
6.5
8
pF
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
8
pF
Capacitance
8LVC Link
NOTE:
PIN DESCRIPTION
1. As applicable to the device type.
Pin Names
Description
OE
LE
xD
xQ
Output-enable Input (Active LOW)
Latch-enable Input
(1)
FUNCTION TABLE (each latch)
(1)
Data Inputs
Data Outputs
Inputs
Outputs
OE
L
LE
H
xD
H
xQ
H
NOTE:
1. These pins have “Bus-hold”. All other pins are standard inputs,
outputs, or I/Os.
L
H
L
L
Q0
L
L
X
X
H
X
Z
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
Q
0 = Level of Q before the indicated steady-state input conditions
were established.
2
IDT74LVCH373A
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
EXTENDEDCOMMERCIALTEMPERATURERANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = – 40°C To +85°C
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
V
2
—
—
—
—
—
0.7
0.8
±5
VIL
Input LOW Voltage Level
Input Leakage Current
—
—
—
V
IIH
IIL
VI = 0 to 5.5V
µA
µA
IOZH
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOZL
IOFF
VIK
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
µA
V
VH
Input Hysteresis
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
10
(2)
—
—
—
—
10
3.6 ≤ VIN ≤ 5.5V
∆ICC
Quiescent Power Supply
Current Variation
One input at VCC - 0.6V,
other inputs at VCC or GND
500
µA
8LVC Link
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol
Parameter(1)
Test Conditions
Min.
Typ.(2)
Max.
Unit
IBHH
Bus-Hold Input Sustain Current
VCC = 3.0V
VCC = 2.3V
VCC = 3.6V
VI = 2.0V
VI = 0.8V
VI = 1.7V
VI = 0.7V
VI = 0 to 3.6V
– 75
—
—
µA
IBHL
75
—
—
—
—
—
—
—
—
—
IBHH
IBHL
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
µA
—
IBHHO
IBHLO
± 500
µA
8LVC Link
NOTES:
1. Pins with Bus-hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74LVCH373A
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
EXTENDEDCOMMERCIALTEMPERATURERANGE
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Output HIGH Voltage
Test Conditions(1)
IOH = – 0.1mA
Min.
Max.
Unit
VOH
VCC = 2.3V to 3.6V
VCC = 2.3V
VCC – 0.2
—
V
IOH = – 6mA
IOH = – 12mA
2
—
—
VCC = 2.3V
1.7
2.2
2.4
2.2
—
VCC = 2.7V
—
VCC = 3.0V
—
VCC = 3.0V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3.0V
—
—
8LVC Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
OPERATING CHARACTERISTICS, V
= 3.3V ± 0.3V, T = 25°C
CC
A
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
Power Dissipation Capacitance per latch Outputs enabled
CL = 0pF, f = 10Mhz
46
3
pF
CPD
Power Dissipation Capacitance per latch Outputs disabled
pF
SWITCHING CHARACTERISTICS (1)
VCC = 2.5±0.2V
VCC = 2.7V
VCC = 3.3V±0.3V
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
Parameter
Propagation Delay
xD to xQ
Min.
Max.
Min.
Max.
Min.
Max.
Unit
—
—
—
—
—
—
7.8
1.5
6.8
ns
ns
ns
ns
Propagation Delay
LE to xQ
—
—
—
—
—
—
8.2
8.7
7.6
2
7.6
7.7
7
Output Enable Time
OE to xQ
Output Disable Time
OE to xQ
1.5
1.5
tPHZ
tPLZ
tW
Pulse Duration, LE HIGH
—
—
—
—
—
—
—
—
3.3
2
—
—
—
—
3.3
2
—
—
ns
ns
ns
ps
tSU
tH
Setup Time, data before LE↓
Hold Time, data after LE↓
1.5
—
1.5
—
—
(2)
tSK(0)
500
Output Skew
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVCH373A
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
EXTENDEDCOMMERCIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
PROPAGATIONDELAY
VIH
VT
0V
(1)
(1)
(2)
VCC = 3.3V ±0.3V VCC = 2.7V VCC = 2.5V ±0.2V
Symbol
Unit
SAME PHASE
VLOAD
6
6
2 x Vcc
Vcc
V
INPUT TRANSITION
tPHL
tPHL
tPLH
tPLH
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VOH
VT
OUTPUT
VCC / 2
150
V
VOL
VLZ
VHZ
CL
mV
mV
VIH
VT
0V
150
OPPOSITE PHASE
INPUT TRANSITION
30
pF
8LVC Link
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
ENABLEANDDISABLETIMES
VLOAD
VCC
DISABLE
ENABLE
VIH
VT
Open
GND
CONTROL
INPUT
500Ω
500Ω
0V
tPZL
tPLZ
VIN
VOUT
Pulse (1, 2)
Generator
D.U.T.
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VOL+VLZ
VOL
RT
tPHZ
tPZH
CL
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
VT
0V
VOH-VHZ
LVC Link
0V
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
LVC Link
RT = Termination resistance: should be equal to ZOUT of the Pulse
NOTE:
Generator.
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SET-UP, HOLD, AND RELEASE TIMES
SWITCHPOSITION
VIH
VT
0V
DATA
INPUT
Test
Switch
tSU
tH
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
VIH
VT
0V
TIMING
INPUT
tREM
VIH
VT
0V
GND
ASYNCHRONOUS
CONTROL
Open
VIH
VT
0V
SYNCHRONOUS
CONTROL
8LVC Link
tSU
tH
OUTPUT SKEW - tsk (x)
VIH
LVC Link
VT
0V
INPUT
PULSEWIDTH
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
PULSE
OUTPUT 1
OUTPUT 2
VOL
VT
tSK (x)
tSK (x)
VOH
tW
VT
HIGH-LOW-HIGH
PULSE
VT
VOL
LVC Link
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVCH373A
3.3VCMOSOCTALTRANSPARENTD-TYPELATCH
EXTENDEDCOMMERCIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
XX
LVC
X
XXXX
XX
Device Type Package
Temp. Range
Bus-Hold
Small Outline IC (gull wing) (SO20-2)
SO
PY
Q
Shrink Small Outline Package (SO20-7)
Quarter Size Small Outline Package (SO20-8)
Thin Shrink Small Outline Package (SO20-9)
PG
373A
Octal Transparent D-Type Latch with 3-State Outputs, ±24mA
H
Bus-hold
–40°C to +85°C
74
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6
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