74SSTV16859NLG [IDT]

VFQFPN-56, Tray;


型号：	74SSTV16859NLG
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	VFQFPN-56, Tray 逻辑集成电路触发器电视
文件：	总6页 (文件大小：78K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74SSTV16859

INDUSTRIALTEMPERATURERANGE

13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O

IDT74SSTV16859

13-BIT TO 26-BIT REGISTERED

BUFFER WITH SSTL I/O

FEATURES:

DESCRIPTION:

• 2.3V to 2.7V Operation

TheSSTV16859isa13-bitto26-bitregisteredbufferdesignedfor2.3V-

2.7VVDD andsupportslowstandbyoperation. Alldatainputsandoutputs

are SSTL_2 level compatible with JEDEC standard for SSTL_2.

RESETisanLVCMOSinputsinceitmustoperatepredictablyduringthe

power-upphase.RESET,whichcanbeoperatedindependentofCLKand

CLK, must be held in the low state during power-up in order to ensure

predictable outputs (low state) before a stable clock has been applied.

RESET, when in the low state, will disable all input receivers, reset all

registers,andforcealloutputstoalowstate,beforeastableclockhasbeen

applied. Withinputsheldlowandastableclockapplied,outputswillremain

low during the Low-to-High transition of RESET.

• SSTL_2 Class II style data inputs/outputs

• Differential CLK input

• RESET control compatible with LVCMOS levels

• Latch-up performance exceeds 100mA

• ESD >2000V per MIL-STD-883, Method 3015; >200V using

machine model (C = 200pF, R = 0)

• Available in 56 pin VFQFPN and 64 pin TSSOP packages

APPLICATIONS:

• Ideally suited for DIMM DDR registered applications

FUNCTIONALBLOCKDIAGRAM

RESET

CLK

VREF

Q^1A

Q1B

TO 12 OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

NOVEMBER 2008

2008 Integrated Device Technology, Inc.

DSC-5947/9

IDT74SSTV16859

INDUSTRIALTEMPERATURERANGE

13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O

PINCONFIGURATIONS

Q13A

Q12A

Q^11A

Q10A

VDDQ

GND

D13

D12

Q9A

VDD

VDDQ

Q7A

D10

GND

Q8A

Q7A

GND

D11

Q6A

Q5A

D10

Q4A

Q3A

Q6A

Q5A

RESET

GND

Q2A

Q1A

Q4A

Q3A

CLK

GND

Q13B

CLK

VDDQ

VDD

VREF

VDDQ

RESET

GND

Q2A

GND

Q1A

Q12B

Q11B

Q10B

CLK

VDDQ

VDD

VREF

Q^13B

VDDQ

Q9B

29 D4

Q8B

Q12B

Q11B

Q10B

GND

Q9B

Q8B

Q7B

VFQFPN

TOP VIEW

Q6B

GND

V^DDQ

VDD

V^DDQ

Q5B

Q4B

Q3B

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

Symbol

Description

Max.

–0.5to3.6

–0.5 to VDD +0.5

–0.5toVDDQ +0.5

–50

Unit

VDD orVDDQ SupplyVoltageRange

GND

Q2B

Q1B

(2)

InputVoltageRange

V^DDQ

(3)

OutputVoltageRange

Input Clamp Current, VI < 0

OutputClampCurrent,

VO < 0 or VO > VDDQ

ContinuousOutputCurrent,

VO = 0 to VDDQ

TSSOP

TOP VIEW

IIK

IOK

±50

±100

°C

FUNCTION TABLE ⁽¹⁾

VDD

ContinuousCurrentthrougheach

VDD, VDDQ or GND

Input

RESET

CLK

↑

CLK

↓

Q Outputs

TSTG

StorageTemperatureRange

–65to+150

Qo⁽²⁾

↑

↓

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. The input and output negative voltage ratings may be exceeded if the ratings of the

I/P and O/P clamp current are observed.

3. The output current will flow if the following conditions are observed:

a) Output in HIGH state

L or H

NOTES:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

↑ = LOW to HIGH

↓ = HIGH to LOW

b) VO = VDDQ

2. Qo = Output level before the indicated steady-state conditions were established.

IDT74SSTV16859

INDUSTRIALTEMPERATURERANGE

13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O

PINDESCRIPTION

Pin Names

Description

Q1 - Q13

DataOutput

GND

Ground

VDDQ

Output-stagedrainpowervoltage

Logicpowervoltage

VDD

RESET

VREF

Asynchronousresetinput-resetsregistersanddisablesdataandclockdifferentialinputrecievers

Inputreferencevoltage

CLK

Positivemasterclockinput

CLK

Negativemasterclockinput

D1 - D13

Center PAD

Data Input - clocked in on the crossing of the rising edge of CLK and the falling edge of CLK

Ground(MLFpackageonly)

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

Operating Condition: TA = –40°C to +85°C, VDD = 2.5V ±0.2V, VDDQ = 2.5V ±0.2V

Symbol

VIK

Parameter

Test Conditions

Min.

Typ.

—

Max.

–1.2

—

Unit

ControlInputs

VDD = 2.3V, II= −18mA

—

VDD – 0.2

1.95

—

VOH

VDD = 2.3V to 2.7V, IOH = -100μA

VDD = 2.3V, IOH = -16mA

—

VOL

VDD = 2.3V to 2.7V, IOL = 100μA

0.2

0.35

VDD = 2.3V, IOL = 16mA

—

AllInputs

VDD = 2.7V,VI = VDD or GND

—

μA

IDD

StaticStandby

IO = 0, VDD = 2.7V, RESET = GND

IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC)

IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),

CLK and CLK Switching 50% Duty Cycle.

IO = 0, VDD = 2.7V, RESET = VDD, VI = VIH (AC) or VIL (AC),

CLK and CLK Switching 50% Duty Cycle. One Data Input

Switching at Half Clock Frequency, 50% Duty Cycle.

VDD = 2.3V to 2.7V, IOH = -20mA

—

0.01

StaticOperating

—

Dynamic Operating (Clock Only)

—

μA/Clock

MHz

IDDD

DynamicOperating

(PerEachDataInput)⁽¹⁾

—

μA/Clock

MHz/Data

Input

rOH

rOL

Output HIGH

OutputLOW

—

VDD = 2.3V to 2.7V, IOH = 20mA

rO(Δ)

| rOH-rOL| each separate bit

DataInputs

VDD = 2.5V, TA = 25°C, IOH = -20mA

VDD = 2.5V, VI = VREF 310mV

—

CLK and CLK

RESET

VICR = 1.25V, VI (PP) = 360mV

VI = VDD or GND

NOTE:

1. Power dissipation levels will allow operation at DDR333 speeds without excessive die temperature.

IDT74SSTV16859

INDUSTRIALTEMPERATURERANGE

13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O

OPERATING CHARACTERISTICS, TA = 25ºC ⁽¹⁾

Symbol

VDD

VDDQ

VREF

VTT

Parameter

Min.

Typ.⁽¹⁾

—

Max.

Unit

SupplyVoltage

VDDQ

2.7

OutputSupplyVoltage

ReferenceVoltage(VREF=VDDQ/2)

TerminationVoltage

2.3

2.5

1.25

VREF

—

2.7

1.15

1.35

VREF– 40mV

VREF+ 40mV

InputVoltage

VDD

VIH

AC High-Level Input Voltage

AC Low-Level Input Voltage

DCHigh-LevelInputVoltage

DCLow-LevelInputVoltage

High-LevelInputVoltage

Low-LevelInputVoltage

Common-ModeInputRange

Peak-to-PeakInputVoltage

High-LevelOutputCurrent

Low-LevelOutputCurrent

OperatingFree-AirTemperature

DataInputs

RESET

VREF+ 310mV

—

VIL

—

VREF–310mV

VIH

VREF+ 150mV

—

VIL

—

1.7

—

VREF–150mV

VIH

—

0.7

1.53

—

VIL

RESET

—

VICR

VI(PP)

IOH

CLK, CLK

0.97

360

—

– 20

IOL

—

– 40

—

+85

°C

NOTE:

1. The RESET input of the device must be held at VDD or GND to ensure proper device operation.

TIMINGREQUIREMENTSOVERRECOMMENDEDOPERATINGFREE-AIR

TEMPERATURERANGE

VDD = 2.5V ± 0.2V

Symbol Parameter

Min.

—

Max.

200

—

Unit

CLOCK

Clock Frequency

MHz

Pulse Duration, CLK, CLK HIGH or LOW

DifferentialInputsActiveTime⁽¹⁾

DifferentialInputsInactiveTime⁽²⁾

Setup Time, Fast Slew Rate^{(3, 5)}

Setup Time, Slow Slew Rate^{(4, 5)}

Hold Time, Fast Slew Rate^(3,5)

Hold Time, Slow Slew Rate^(2,5)

2.5

—

tACT

tINACT

tSU

—

Data Before CLK↑, CLK↓

Data Before CLK↑, CLK ↓

0.75

0.9

0.75

0.9

—

NOTES:

1. Data inputs must be low a minimum time of tACT max., after RESET is taken HIGH.

2. Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max., after RESET is taken LOW.

3. For data signal input slew rate is ≥1V/ns.

4. For data signal input slew rate is ≥0.5V/ns and <1V/ns.

5. CLK, CLK signal input slew rates are ≥1V/ns.

SWITCHINGCHARACTERISTICSOVERRECOMMENDEDFREE-AIROPERATING

RANGE(UNLESSOTHERWISENOTED)

VDD = 2.5V ± 0.2V

Symbol

fMAX

Parameter

Min

200

1.1

—

Max.

—

2.8

Unit

MHz

tPD

CLK and CLK to Q

RESET to Q

tPHL

IDT74SSTV16859

INDUSTRIALTEMPERATURERANGE

13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O

TEST CIRCUITS AND WAVEFORMS (VDD = 2.5V ± 0.2V)

VTT

RL = 50Ω

From Output

Test Point

Under Test

CL = 30 pF

(see note 1)

Load Circuit

LVCMOS

RESET

VDD

Timing

Input

VI(PP)

VDD/2

VICR

Input

tINACT

tACT

tPLH

tPHL

VTT

VOH

VOL

90%

VTT

IDD

10%

Output

(see note 2)

Voltage and Current Waveforms

Inputs Active and Inactive Times

Voltage Waveforms - Propagation Delay Times

LVCMOS

RESET

Input

VIH

VIL

VDD/2

tPHL

VTT

VOH

VOL

VIH

VIL

Output

Input

VREF

Voltage Waveforms - Propagation Delay Times

Voltage Waveforms - Pulse Duration

Timing

Input

VICR

VI(PP)

tSU

VIH

VIL

Input

VREF

Voltage Waveforms - Setup and Hold Times

NOTES:

1. CL includes probe and jig capacitance.

2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.

3. All input pulses are supplied by generators having the following characteristics: PRR ≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).

4. The outputs are measured one at a time with one transition per measurement.

5. VTT = VREF = VDDQ/2

6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.

7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.

8. tPLH and tPHL are the same as tPD.

IDT74SSTV16859

INDUSTRIALTEMPERATURERANGE

13-BITTO26-BITREGISTEREDBUFFERWITHSSTLI/O

ORDERINGINFORMATION

XX X

SSTV

Temp. Range

Family Device Type Package

Thin Shrink Small Outline Package

Thermally Enhanced Plastic Very Fine Pitch

Quad Flat No Lead Package

859

13-Bit to 26-Bit Registered Buffer with SSTL I/O

Double-Density

–40°C to +85°C

CORPORATE HEADQUARTERS

for SALES:

San Jose, CA 95138

fax: 408-284-2775

www.idt.com

74SSTV16859NLG [IDT]

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