810252BKI-03LF [IDT]
VCXO Jitter Attenuator and FemtoClock™ Multiplier; VCXO抖动衰减器和FemtoClock ™乘法器
| 型号： | 810252BKI-03LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | VCXO Jitter Attenuator and FemtoClock™ Multiplier |
| 文件： | 总24页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VCXO Jitter Attenuator and
FemtoClock™ Multiplier
ICS810252BI-03
DATA SHEET
GENERAL DESCRIPTION
FEATURES
• Two LVCMOS/LVTTL outputs, 17Ω impedance
Each output supports independent frequency selection at
25MHz, 62.5MHz, 125MHz, and 156.25MHz
The ICS810252BI-03 is a member of the
ICS
HiperClockS™ family of high performance clock
solutions from IDT. The ICS810252BI-03 is a PLL
based synchronous multiplier that is optimized for
PDH or SONET to Ethernet clock jitter attenuation
HiPerClockS™
• Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series.
The first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock™ frequency multiplier that provides the low jitter,
high frequency Ethernet output clock that easily meets Gigabit
and 10 Gigabit Ethernet jitter requirements. Pre-divider and
output divider multiplication ratios are selected using device
selection control pins. The multiplication ratios are optimized
to support most common clock rates used in PDH, SONET
and Ethernet applications. The VCXO requires the use of an
external, inexpensive pullable crystal. The VCXO uses external
passive loop filter components which allows configuration of
the PLL loop bandwidth and damping characteristics. The
device is packaged in a space-saving 32-TQFP, E-Pad and 32-
VFQFN packages and supports industrial temperature range.
• Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
• Attenuates the phase jitter of the input clock by using a low-
cost pullable fundamental mode VCXO crystal
• VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
• FemtoClock frequency multiplier provides low jitter, high
frequency output
• Absolute pull range: 50ppm
• FemtoClock VCO frequency: 625MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz - 20MHz): 1.1ps (typical)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
1
2
3
4
5
6
LF1
LF0
GND
24
23
22
21
20
19
18
17
VDDO_QB
QB
ISET
GND
GND
ICS810252BI-03
CLK_SEL
VDD
VDDO_QA
QA
RESERVED
GND
7
8
GND
ODASEL_0
9 10 11 12 13 14 15 16
32-Lead TQFP, E-Pad
7mm x 7mm x 1.0mm package body
Y package
Top View
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
BLOCK DIAGRAM
Loop
Filter
3
PU
Output
Divider
PDSEL_[2:0]
QA
00 = 25
01 = 5
10 = 4
VCXO Input
Pre-Divider
25MHz
PD
11 = 10
CLK0
Phase
Detector
000 = 1
PU/PD
0
1
nCLK0
2
001 = 193
010 = 256
011 = 2430
100 = 3125
101 = 9720
110 = 15625
111 = 19440
PD
ODASEL_[1:0]
FemtoClock PLL
625MHz
VCXO
PD
Charge
Pump
CLK1
PU/PD
nCLK1
Output
Divider
VCXO Feedback Divider
÷3125
Pulldown
CLK_SEL
QB
00 = 25
01 = 5
VCXO Jitter Attenuation PLL
10 = 4
11 = 10
2
PD
ODBSEL_[1:0]
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Analog
Input/Output
Analog
Input/Output
Description
1, 2
LF1, LF0
Loop filter connection node pins.
Charge pump current setting pin.
Power supply ground.
3
ISET
GND
4, 8, 18,
21, 24
Power
Input
Input clock select. When HIGH selects CLK1/nCLK1.
When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels.
5
CLK_SEL
Pulldown
Pullup
6, 12, 27
7
VDD
Power
Core power supply pins.
RESERVED
Reserved
Reserved pin. Do not connect.
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Input
13
VDDA
Power
Input
Analog supply pin.
14,
15
16,
17
ODBSEL_1,
ODBSEL_0
ODASEL_1,
ODASEL_0
Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
Frequency select pins for Bank A output. See Table 3B.
LVCMOS/LVTTL interface levels.
Pulldown
Pulldown
Input
Bank A single-ended clock output. LVCMOS/LVTTL interface levels.
17Ω output impedance.
19
20
QA
Output
Power
VDDO_QA
Output power supply pin for QA clock output.
Bank B single-ended clock output. LVCMOS/LVTTL interface levels.
17Ω output impedance.
22
23
25
26
28
29
QB
Output
Power
Input
VDDO_QB
nCLK1
CLK1
Output power supply pin for QB clock output.
Pullup/
Pulldown
Inverting differential clock input. VDD/2 bias voltage when left floating.
Input
Pulldown Non-inverting differential clock input.
Pullup/
nCLK0
Input
Inverting differential clock input. VDD/2 bias voltage when left floating.
Pulldown
CLK0
Input
Pulldown Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Input
32
VDDX
Power
Power supply pin for VCXO charge pump.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDX, VDDO_QA, VDDO_QB = 3.465V
10
pF
RPULLUP
Input Pullup Resistor
51
51
17
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 3A. PRE-DIVIDER FUNCTION TABLE
Inputs
Pre-Divider Value
PDSEL_2
PDSEL_1 PDSEL_0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
193
256
2430
3125
9720
15625
19440 (default)
TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Divider Value
ODxSEL_1
ODxSEL_0
0
0
1
1
0
1
0
1
25 (default)
5
4
10
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 3C. FREQUENCY FUNCTION TABLE
Input Frequency Pre-Divider VCXO Frequency
Femtoclock
Output Divider Output Frequency
(MHz)
Value
(MHz)
VCO Frequency (MHz)
Value
(MHz)
0.008
1
25
625
25
25
0.008
0.008
0.008
1.544
1.544
1.544
1.544
2.048
2.048
2.048
2.048
19.44
19.44
19.44
19.44
25
1
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
5
4
125
156.25
62.5
25
1
1
10
25
5
193
193
125
193
4
156.25
62.5
25
193
10
25
5
256
256
125
256
4
156.25
62.5
25
256
10
25
5
2430
2430
2430
2430
3125
3125
3125
3125
9720
9720
9720
9720
15625
15625
15625
15625
19440
19440
19440
19440
125
4
156.25
62.5
25
10
25
5
25
125
25
4
156.25
62.5
25
25
10
25
5
77.76
77.76
77.76
77.76
125
125
4
156.25
62.5
25
10
25
5
125
125
125
4
156.25
62.5
25
125
10
25
5
155.52
155.52
155.52
155.52
125
4
156.25
62.5
10
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
I
Outputs, VO
Package Thermal Impedance, θ
32 Lead VFQFN
32 Lead TQFP
JA
37°C/W (0 mps)
32.2°C/W (0 mps)
Storage Temperature, T
-65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum Typical Maximum Units
Core Supply Voltage
Analog Supply Voltage
3.135
3.3
3.3
3.465
VDD
V
V
VDDA
VDD – 0.13
VDDO_QA,
VDDO_QB
Output Supply Voltage
3.135
3.135
3.3
3.3
3.465
V
VDDX
Charge Pump Supply Voltage
3.465
190
V
Power and Charge Pump
Supply Current
IDD + IDDX
IDDA
mA
Analog Supply Current
13
2
mA
mA
IDDO_QA + IDDO_QB Output Supply Current
No Load
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
Input Low Voltage
CLK_SEL,
2
VDD + 0.3
V
VIL
-0.3
0.8
V
ODASEL_[0:1],
ODBSEL_[0:1]
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
PDSEL[0:2]
CLK_SEL,
ODASEL_[0:1],
ODBSEL_[0:1]
VDD = 3.465V, VIN = 0V
-5
Input
Low Current
IIL
PDSEL[0:2]
VDD = 3.465V, VIN = 0V
-150
2.6
µA
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO_QA,_QB/2.
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VDD = 3.465V
VIN = 0V, VDD = 3.465V
Minimum Typical Maximum Units
CLK0/nCLK0,
CLK1/nCLK1
150
µA
CLK0, CLK1
-5
-150
µA
µA
V
IIL
Input Low Current
nCLK0, nCLK1
VIN = 0V, VDD = 3.465V
VPP
Peak-to-Peak Input Voltage; NOTE 1
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD - 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5. AC CHARACTERISTICS, VDD = VDDO_QA = VDDO_QB = VDDX = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fIN
Input Frequency
0.008
25
155.52
156.25
MHz
MHz
fOUT
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
125MHz, 25MHz crystal
Integration Range: 12kHz - 20MHz
tjit(Ø)
1.1
ps
tsk(o)
odc
Output Skew; NOTE 2, 3
Output Duty Cycle
130
53
ps
ꢀ
47
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
200
500
ps
VCXO & FemtoClock PLL
Lock Time; NOTE 4
Reference Clock Input is 50ppm
from Nominal Frequency
tLOCK
3
s
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: Characterized with outputs at the same frequency using the loop filter components for the high loop bandwidth.
Refer to VCXO-PLL Loop Bandwidth Selection Table.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage, same frequency and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Lock time measured from power-up to stable output frequency.
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TYPICAL PHASE NOISE AT 125MHZ
125MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 1.1ps (typical)
OFFSET FREQUENCY (HZ)
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.65V 5ꢀ
VDD
SCOPE
,
VDD
VDDO_QA,
VDDO_QB,
VDDX
nCLK0,
nCLK1
VDDA
Qx
VPP
VCMR
Cross Points
LVCMOS
CLK0,
CLK1
GND
GND
-1.65V 5ꢀ
DIFFERENTIAL INPUT LEVEL
3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VDDO_Q
FOUTx
FOUTy
2
VDDO_Q
2
tsk(o)
Offset Frequency
f1
f2
RMS Jitter = Area Under Offset Frequency Markers
PHASE JITTER
OUTPUT SKEW
VDDO_Q
2
80ꢀ
tF
80ꢀ
QA, QB
tPW
20ꢀ
20ꢀ
tPERIOD
QA, QB
tR
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
OUTPUT RISE/FALL TIME
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PARAMETER MEASUREMENT INFORMATION, CONTINUED
VCXO & FEMTOCLOCK PLL LOCK TIME
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUTS
LVCMOS OUTPUTS
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
All unused LVCMOS output can be left floating. There should be
no trace attached.
LVCMOS CONTROL PINS
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS810252BI-03
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDX, VDDA, VDDO_QA
and VDDO_QB should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic VDD pin and
also shows that VDDA requires that an additional10Ω resistor
along with a 10µF bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
VDDX
10Ω
.01µF
VDDA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V /2 is
generated by the bias resistors R1, R2 and C1. This bias DcDircuit
should be located as close as possible to the input pin. The ratio
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the
most common driver types. The input interfaces suggested here
are examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
HIPERCLOCKS LVHSTL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
nCLK
nCLK
HiPerClockS
HiPerClockS
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
VFQFN EPADTHERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor
Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”.The number of vias (i.e. “heat pipes”)
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
ICS810252BYI-03 REVISION A AUGUST 20, 2009
13
©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TQFP EPADTHERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 5. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor
Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”.The number of vias (i.e. “heat pipes”)
SOLDER
SOLDER
SOLDER
EXPOSED HEAT SLUG
PIN
PIN
LAND PATTERN
(GROUND PAD)
PIN PAD
GROUND PLANE
PIN PAD
THERMAL VIA
FIGURE 5. ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
ICS810252BYI-03 REVISION A AUGUST 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
LAYOUT GUIDELINE
Figure 6 shows an example of the 810252IB-03 application
schematic. In this example, the device is operated at V = 3.3V.
The decoupling capacitors should be located as close asDpD ossible
to the power pin. The input is driven by a 3.3V LVPECL driver. An
optional 3-pole filter can also be used for additional spur reduction.
It is recommended that the loop filter components be laid out for
the 3-pole option. This will also allow the 2-pole filter to be used.
VDD
R11
125
R13
125
CLK1
Zo = 50
Zo = 50
nCLK1
R12
84
R14
84
LVPECL Driv er
VDD
R7
VDD = VDDX = VDDO_QA = VDDO_QB = 3.3V
R9
125
125
CLK0
Zo = 50
Zo = 50
C28 and C29 are used for additional capacitance
to center VCXO tuning curve. For most layouts,
it is recommended to add an additional 3pf.
For boards with high parasitics, C28 and 29
might not be required.
nCLK0
XTAL_OUT
R8
84
R10
85
LVPECL Driv er
C28
3pf
25MHz, CL =10pf
XTAL_IN
VDD
VDD
C29
3pf
R26 10
C15
0.1u
VDDX
C47
0.01u
C46
10u
U1
R1
35
Zo = 50
VDDO_QB
VDDO_QA
Receiv er
2-pole loop filter example
LF0
LF1
LF0
LF1
LF0
GND
LF1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
LF1
LF0
ISET
GND
CLK_SEL
VDD
nc
GND
VDDO_QB
QB
GND
VDDO_QA
QA
Rs
GND
CLK_SEL
GND
221k
Cs
VDD
Cp
0.001uF
R2
35
Zo = 50
GND
GND
ODASEL_0
ODASEL_0
0.1uF
GND
Receiv er
R20
2.21K
C12
0.1u
VDDO_QB
VDDO_QA
ICS810252Bi-03
VDD
3-pole loop filter example - (optional)
C17
0.1u
C18
0.1u
R3
LF0
LF1
Rs
820k
200k
Cp
0.01uF
C3
220pF
R25
Cs
1.0uF
10
VDDA
VDD
C14
0.1u
C30
0.01u
C45
10u
FIGURE 6. SCHEMATIC OF RECOMMENDED LAYOUT
ICS810252BYI-03 REVISION A AUGUST 20, 2009
15
©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality
operation of the VCXO-PLL. In choosing a crystal, special
precaution must be taken with the package and load
the crystal specification. In either case, the absolute tuning
range is reduced. The correct value of C is dependant on the
L
characteristics of the VCXO. The recommended C in the
L
Crystal Parameter Table balances the tuning range by
centering the tuning curve.
capacitance (C ). In addition, frequency, accuracy and
L
temperature range must also be considered. Since the pulling
range of a crystal also varies with the package, it is
recommended that a metal-canned package like HC49 be
used. Generally, a metal-canned package has a larger pulling
range than a surface mounted device (SMD). For crystal
selection information, refer to the VCXO Crystal Selection
Application Note.
The frequency of oscillation in the third overtone mode is not
necessarily at exactly three times the fundamental frequency.
The mechanical properties of the quartz element dictate the
position of the overtones relative to the fundamental. The
oscillator circuit may excite both the fundamental and overtone
modes simultaneously. This will
LF0
cause a nonlinearity in the
LF1
The crystal’s load capacitance C characteristic determines its
tuning curve. This potential
problem is the reason VCXO
crystals are required to be
tested for absence of any
activity inside a 200ppm
window at three times the
fundamental frequency. Refer to
ISET
L
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance,
IC package lead capacitance, internal varactor capacitance and
RS RSET
CP CS
any installed tuning capacitors (C ).
TUNE
XTAL_IN
If the crystal C is greater than the total external capacitance,
CTUNE
25MHz
CTUNE
L
F
and F
in the Crystal
L_30VT
L_30VT_SPURS
the VCXO will oscillate at a higher frequency than the crystal
Characterization Table.
specification. If the crystal C is lower than the total external
XTAL_OUT
L
capacitance, the VCXO will oscillate at a lower frequency than
The crystal and external loop
filter components should be
VCXO CHARACTERISTICS TABLE
kept as close as possible to the device. Loop filter and crystal
traces should be kept short and separated from each other.
Other signal traces should be kept separate and not run
underneath the device, loop filter or crystal components.
Symbol Parameter
Typical
8000
8
Unit
Hz/V
pF
kVCXO
VCXO Gain
CV_LOW
CV_HIGH
Low Varactor Capacitance
High Varactor Capacitance
17
pF
VCXO-PLL LOOP BANDWIDTH SELECTION TABLE
Bandwidth
10Hz (Low)
50Hz (Mid)
125Hz (High)
Crystal Frequency (MHz)
RS (kΩ)
CS (µF)
1.0
CP (µF)
0.01
RSET (kΩ)
8.8
25MHz
25MHz
25MHz
120
221
620
0.1
0.001
0.0004
2.21
0.022
2.21
CRYSTAL CHARACTERISTICS
Symbol
Parameter
Minimum Typical
Maximum
Units
Mode of Operation
Frequency
Fundamental
fN
fT
fS
25
MHz
ppm
ppm
°C
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
20
20
-40
85
CL
10
4
pF
CO
pF
CO/C1
220
200
200
240
FL_30VT
3rd Overtone FL
FL_30VT_SPURS 3rd Overtone FL Spurs
ESR Equivalent Series Resistance
40
1
Ω
Drive Level
mW
ppm
Aging @ 25°C
3 per year
ICS810252BYI-03 REVISION A AUGUST 20, 2009
16
©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS810252BI-03.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS810252BI-03 is the sum of the core power plus the analog plus the power dissipated in the
load(s). The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
Core Power Dissipation
•
Power (core)MAX = VDD_MAX * ((IDD + IDDX) + IDDA) = 3.465V * (190mA + 13mA) = 703.4mW
Output Power Dissipation
•
•
•
Output Impedance ROUT Power Dissipation due to Loading 50Ω to VDDO/2
Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 17Ω)] = 25.9mA
Power Dissipation on the ROUT per LVCMOS output
2
Power (ROUT) = ROUT * (IOUT
)
= 17Ω * (25.9mA)2 = 11.4mW per output
Total Power Dissipation on the ROUT
Total Power (ROUT) = 11.4mW * 2 = 22.8mW
Dynamic Power Dissipation at 125MHz
2
Power (125MHz) = CPD * Frequency * (VDDO
)
= 10pF * 125MHz * (3.465V)2 = 15mW per output
Total Dynamic Power (125MHz) = 15mW * 2 = 30mW
Total Power Dissipation
Total Power
•
= Power (core)MAX + Total Power (ROUT) + Total Dynamic Power (125MHz)
= 703.4mW + 22.8mW + 30mW
= 756.2mW
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
TM
recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 37°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.756W * 37°C/W = 113°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of terminated outputs, supply voltage, air flow,
and the number of board layers.
TABLE 6A. THERMAL RESISTANCE θJA FOR 32 LEAD VFQFN, FORCED CONVECTION
θJA vs. 0 Air Flow (Meters per Second)
0
1
2.5
29.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
TABLE 6B. θJA VS. AIR FLOW TABLE FOR 32 LEAD TQFP, E-PAD
θJA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
32.2°C/W
26.3°C/W
24.7°C/W
ICS810252BYI-03 REVISION A AUGUST 20, 2009
17
©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
3. Case Temperature calculated from Junction Temperature θJC Calculations
In applications where there is a heatsink present, and the majority of the power is dissipated through the top of the device, the
junction temperature can be calculated from the case temperature, TC, using the junction-to-case thermal resistance value θJC. In
practical application is it the average of the case temperature of the surface of the device on which the heatsink is attached.
The equation for calculating the junction temperature is as follows:
Tj = θJC * Pd_case+ TC
Tj = Junction Temperature
θJC= Junction-to-Case Thermal Resistance
Pd_case= Total Device Power Dissipation through the case
TC = Average Case Temperature
It is important to emphasize that case temperature calculations using θJC do not use Pd_total, rather they use Pd_case, which is the
portion of power dissipated through the case. In real applications it is difficult to quantify the power dissipated through the case, so
the value of θJC is best used for a package-to-package comparison, rather than a junction temperature calculation. As such, the
JEDEC standard (JESD51-2) uses another parameter, ψJT (PsiJT), which can be used to calculate junction temperature from a
measured case temperature.
ψJT Calculations
ψJT is the thermal characterization parameter which reports the differences between junction temperature and the temperature at
the top dead center of the outside surface of the component package, divided by the power applied to the component. This requires
knowing the total power dissipation and a measured case temperature in order to calculate the junction temperature. It can also be
calculated using an estimated case temperature for a given junction temperature. In the following equation, TT, is used to indicate
the single-point temperature measurement at the top-center of the case. The change in the naming convention from TC to TT is to
differentiate the use between the θJC and ψJT calculations.
The equation for TJ is as follows: TJ = TT + ψJT * Pd_total
Solving for TT yields:
TT = TJ - ψJT * Pd_total
TJ = Junction Temperature
ψJT = (PsiJT) Junction-to-Top of Package Parameter
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TT = Temperature at the top-center of the package
The advantage of this method is that it allows for the calculation of the junction temperature or case temperature using total power
dissipation and eliminates the need to quantify power dissipation through the top of the device. In order to calculate TT, the
appropriate ψJT factor must be used. Assuming no air flow, a multi-layer board, and E-Pad soldered to the board, the appropriate
value is 0.3°C/W per Table 7 below. Therefore, TT for a TJ value of 113°C (from the example in section 2) with all outputs switching
is:
TT = 113.0°C – 0.756W * 0.3°C/W = 112.8°C.
This calculation is only an example. TJ will vary depending on the number of terminated outputs, supply voltage, air flow and the
number of board layers.
Table 7. ψJT for 32 Lead VFQFN, Forced Convection
ψ by Velocity (Meters per Second)
JT
0
Multi-Layer PCB, JEDEC Standard Test Boards
0.3°C/W
ICS810252BYI-03 REVISION A AUGUST 20, 2009
18
©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
RELIABILITY INFORMATION
TABLE 8A. θ VS. AIR FLOW TABLE FOR 32 LEAD VFQFN
JA
θ vs. 0 Air Flow (Meters per Second)
JA
0
1
2.5
29.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
TABLE 8B. θ VS. AIR FLOW TABLE FOR 32 LEAD TQFP, E-PAD
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
32.2°C/W
26.3°C/W
24.7°C/W
TRANSISTOR COUNT
The transistor count for ICS810252BI-03 is: 6597
ICS810252BYI-03 REVISION A AUGUST 20, 2009
19
©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP, E-PAD
-HD VERSION
EXPOSED PAD DOWN
TABLE 9A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
ABA-HD
SYMBOL
MINIMUM
NOMINAL
32
MAXIMUM
N
A
--
--
1.20
0.15
1.05
0.40
0.20
A1
0.05
0.95
0.30
0.09
0.10
A2
1.0
b
0.35
c
D, E
D1, E1
D2, E2
e
--
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
L
0.45
0.75
θ
--
--
0
°
7°
ccc
--
3.0
0.10
4.0
D3 & D3
3.5
Reference Document: JEDEC Publication 95, MS-026
ICS810252BYI-03 REVISION A AUGUST 20, 2009
20
©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
(Ref.)
N & N
Even
Seating Plane
(N -1)x e
(Ref.)
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
Singulation
1
2
(N -1)x e
(Ref.)
OR
E2
2
TopView
b
e
Thermal
Base
A
(Ref.)
D2
2
D
N &N
Odd
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package.This draw-
ing is not intended to convey the actual pin count or pin layout of
this device.The pin count and pinout are shown on the front page.
The package dimensions are in Table 9B below.
TABLE 9B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
0.80
0
1.00
0.05
A1
A3
b
--
0.25 Ref.
0.25
0.18
0.30
8
ND
NE
D
8
5.00 BASIC
3.15
D2
E
3.0
3.0
3.3
3.3
5.00 BASIC
3.15
E2
e
0.50 BASIC
0.40
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS810252BYI-03 REVISION A AUGUST 20, 2009
21
©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 10. ORDERING INFORMATION
Part/Order Number
810252BKI-03LF
810252BKI-03LFT
810252BYI-03LF
810252BYI-03LFT
Marking
Package
Shipping Packaging
tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS252BI03L
ICS252BI03L
ICS0252BI03L
ICS0252BI03L
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
32 lead "Lead-Free" TQFP, E-Pad
32 lead "Lead-Free" TQFP, E-Pad
2500 tape & reel
tray
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
ICS810252BYI-03 REVISION A AUGUST 20, 2009
22
©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
16
VCXO-PLL External Components - replace 2nd to last paragraph.
Crystal Characteristics Table - add 3rd Overtone specs.
VFQFN Package Dimensions - corrected D2/E2 dimensions.
A
8/20/09
T9B
21
ICS810252BYI-03 REVISION A AUGUST 20, 2009
23
©2009 Integrated Device Technology, Inc.
ICS810252BI-03 Data Sheet
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
www.IDT.com
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Techical Support
netcom@idt.com
+480-763-2056
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion.All information
in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products are
determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any
kind, whether express or implied, including, but not limited to, the suitablity of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property
rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users.
Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Techology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or
their respective third party owners.
Copyright 2009. All rights reserved.
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