810525AGILF [IDT]
VCXO-TO-LVCMOS/LVTTL OUTPUT; VCXO - TO- LVCMOS / LVTTL输出
| 型号： | 810525AGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | VCXO-TO-LVCMOS/LVTTL OUTPUT |
| 文件： | 总12页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VCXO-TO-LVCMOS/LVTTL OUTPUT
ICS810525I
GENERAL DESCRIPTION
FEATURES
The ICS810525I is a high performance, low jit-
• One single-ended LVCMOS/LVTTL output
ICS
HiPerClockS™
ter/low phase noise VCXO from IDT. The
ICS810525I works in conjunction with a 25MHz
• One single-ended clock accepts the following input types:
LVCMOS, LVTTL
pullable crystal to generate an LVCMOS/LVTTL
output clock of 25MHz from an input clock of
• Accepts input frequency of 5MHz
5MHz. The frequency of the VCXO is adjusted by the VC
control voltage input. The output range is 100ppm around
the nominal crystal frequency. The LF1 control voltage range
is 0 – V . The device is packaged in a small 16 TSSOP
packageDaD nd is ideal for use on space constrained boards.
• Absolute pull range: 100ppm
• Proprietary multiplier provides low jitter, high frequency output
• RMS phase jitter @ 25MHz, using a 25MHz crystal
(1kHz – 1MHz): 0.27ps (typical)
• Full 3.3V supply, or 3.3V core/2.5V output supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
PIN ASSIGNMENT
nc
1
2
3
4
5
6
7
8
VDD
CLK
GND
16
15
14
GND
Q
VDDO
nc
(External
Loop Filter Inputs)
13 LF1
LF1
LF0
12
11
10
9
LF0
25MHz
nc
VDDA
VDD
XTAL_IN
XTAL_OUT
GND
ICS810525I
x5 VCXO
PLL
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Pulldown
Q
CLK
5MHz
Top View
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
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ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
TABLE 1. PIN DESCRIPTIONS
Number
Name
nc
Type
Unused
Description
1, 5, 6
No connect.
2, 9, 14
GND
Q
Power
Output
Power
Power
Power
Power supply ground.
3
4
Single-ended clock output. LVCMOS/LVTTL interface levels.
Output power supply pin.
Analog supply pin.
VDDO
VDDA
VDD
7
8, 16
Core power supply pins.
10,
11
XTAL_OUT,
XTAL_IN
VCXO crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Input
Analog
Input/Output
12, 13
15
LF0, LF1
CLK
Loop filter connection node pins.
Input
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
4
8
pF
pF
pF
kΩ
Ω
VDDO = 3.465V
CPD
Power Dissipation Capacitance
V
DDO = 2.625V
5
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
51
15
20
VDDO = 3.3V
VDDO = 2.5V
Ω
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
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ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
92.4°C/W (0 mps)
-65°C to 150°C
I
Outputs, VO
Package Thermal Impedance, θ
JA
Storage Temperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Power Supply Voltage
3.465
VDD
3.465
35
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
VDD – 0.05
3.135
3.3
3.3
V
mA
mA
IDDA
5
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
VDD
2.625
35
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
VDD – 0.05
2.375
3.3
2.5
V
mA
mA
IDDA
5
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
VLF1
IIH
Input High Voltage
2
-0.3
0
VDD + 0.3
0.8
V
V
Input Low Voltage
VCXO Control Voltage
Input High Current
Input Low Current
VDD
V
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
VDD = 3.465V or 2.625V
150
µA
µA
µA
V
IIL
-5
-100
2.6
II
Input Current of VLF1 pin
100
0.5
V
V
DDO = 3.3V 5ꢀ, IOH = -12mA
DDO = 2.5V 5ꢀ, IOH = -12mA
VOH
VOL
Output High Voltage
Output Low Voltage
1.8
V
VDDO = 3.3V or 2.5V 5ꢀ IOL = 12mA
V
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
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ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
25
MHz
RMS Phase Jitter (Random);
NOTE 1
Integration Range:
1kHz – 1MHz
tjit(Ø)
0.27
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
500
48
1200
52
ps
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
Characterized using a 3kHz bandwidth filter.
NOTE 1: Please refer to the Phase Noise Plot.
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
25
MHz
RMS Phase Jitter (Random);
NOTE 1
Integration Range:
1kHz – 1MHz
tjit(Ø)
0.26
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
600
44
2100
56
ps
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
Characterized using a 3kHz bandwidth filter.
NOTE 1: Please refer to the Phase Noise Plot.
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
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ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
TYPICAL PHASE NOISE AT 25MHZ @ 3.3V/3.3V
25MHz
RMS Phase Jitter (Random)
Filter
1kHz to 1MHz = 0.27ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
a Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 25MHZ @ 3.3V/2.5V
25MHz
RMS Phase Jitter (Random)
1kHz to 1MHz = 0.26ps (typical)
Filter
Raw Phase Noise Data
Phase Noise Result by adding
a Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
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ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2.05V 5ꢀ
1.25V 5ꢀ
1.65V 5ꢀ
2.05V 5ꢀ
SCOPE
VDD,
VDDO
VDD
SCOPE
VDDA
Qx
VDDO
LVCMOS
GND
VDDA
Qx
LVCMOS
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VDD
2
Q
tPW
tPERIOD
Phase Noise Mask
tPW
x 100ꢀ
odc =
Offset Frequency
f1
f2
tPERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80ꢀ
tF
80ꢀ
tR
20ꢀ
20ꢀ
Q
OUTPUT RISE/FALL TIME
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
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ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
APPLICATION INFORMATION
SCHEMATIC EXAMPLE
Figure 1 shows an example of the ICS810525I application
driver. A 2-pole filter loop filter with Low LBW setting is used in
this example. It is recommended to refer to the ICS810525I
datasheet for more detail on loop filter values.
schematic. In this example, the device is operated at V = 3.3V.
The decoupling capacitors should be located as close as
possible to the power pin.The input is driven by a 3.3V LVCMOS
DD
VDD
VDD = VDDO = 3.3V
Q1
R1
33
C6
0.1u
Zo = 50
R2
Q
Zo = 50
Driver_LVCMOS
U2
33
Receiver
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDDO
VDD
CLK
GND
LF1
nc
GND
Q
VDDO
nc
nc
VDDA
2-pole loop filter with low LBW Setting
LF0
LF1
LF0
C7
0.1u
LF0
Rs
1k
XTAL_IN
XTAL_OUT
GND
VDD
R3
VDD
10
VDDA
Cp
Cs
10nF
VDD
10uF
C3
C4
ICS810525I
0.01u
10u
C5
0.1u
XTAL_I N
C1
TUNE
X1
XTAL_OUT
C2
TUNE
FIGURE 1. ICS810525I SCHEMATIC EXAMPLE
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
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ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality
operation of the VCXO-PLL. In choosing a crystal, special
precaution must be taken with the package and load
capacitance (C ). In addition, frequency, accuracy and
temperature rangLe must also be considered. Since the pulling
range of a crystal also varies with the package, it is
recommended that a metal-canned package like HC49 be used.
Generally, a metal-canned package has a larger pulling range
than a surface mounted device (SMD). For crystal selection
information, refer to the VCXO Crystal Selection Application
Note.
the crystal specification. In either case, the absolute tuning
range is reduced. The correct value of C is dependent on the
L
characteristics of the VCXO.The recommended C in the Crystal
Parameter Table balances the tuning range by Lcentering the
tuning curve.
The VCXO-PLL Loop Bandwidth Selection Table shows R , C
S
S
and C values for recommended high, mid and low loop
P
bandwidth configurations. The device has been characterized
using these parameters. For other configurations, refer to the
Loop Filter Component Selection for VCXO Based PLLs
Application Note.
LF0
LF1
The crystal and external loop
The crystal’s load capacitance C characteristic determines its
L
filter components should be
kept as close as possible to the
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance,
IC package lead capacitance, internal varactor capacitance and
RS
device. Loop filter and crystal
CP
CS
traces should be kept short and
separated from each other.
Other signal traces should be
kept separate and not run
underneath the device, loop
filter or crystal components.
any installed tuning capacitors (C ).
TUNE
XTAL_IN
If the crystal’s C is greater than the total external capacitance,
the VCXO will oLscillate at a higher frequency than the crystal
CTUNE
25MHz
specification. If the crystal’s C is lower than the total external
XTAL_OUT
L
CTUNE
capacitance, the VCXO will oscillate at a lower frequency than
VCXO CHARACTERISTICS TABLE
Symbol Parameter
Typical
15
Unit
kHz/V
pF
kVCXO
VCXO Gain
CV_LOW
CV_HIGH
Low Varactor Capacitance
High Varactor Capacitance
9.8
22.7
pF
VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE
Bandwidth
125Hz (Low)
1.5kHz (Mid)
3kHz (High)
Crystal Frequency (MHz)
RS (kΩ)
CS (µF)
CP (pF)
10000
100
25MHz
25MHz
25MHz
1
10
12
25
0.1
0.1
100
CRYSTAL CHARACTERISTICS
Symbol Parameter
Mode of Operation
Minimum Typical
Maximum
Units
Fundamental
fN
fT
fS
Frequency
25
MHz
ppm
ppm
°C
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
20
20
-40
85
CL
10
4
pF
CO
pF
CO/C1
ESR
220
240
Equivalent Series Resistance
Drive Level
40
1
Ω
mW
ppm
Aging @ 25°C
3 per year
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
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ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
RELIABILITY INFORMATION
TABLE 5. θ VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92.4°C/W
88.0°C/W
85.9°C/W
TRANSISTOR COUNT
The transistor count for ICS810525I is: 635
PACKAGE OUTLINE & PACKAGE DIMENSIONS
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 6. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
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ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
TABLE 7. ORDERING INFORMATION
Part/Order Number
810525AGILF
Marking
10525AIL
10525AIL
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
810525AGILFT
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
10
ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
REVISION HISTORY SHEET
Description of Change
LVCMOS DC Characteristics - added to VOH/VOL test conditions.
Rev
Table
Page
Date
B
T3C
3
2/24/09
IDT™ / ICS™ VCXO-TO-LVCMOS/LVTTL OUTPUT
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ICS810525AGI REV. B FEBRUARY 24, 2009
ICS810525I
VCXO-TO-LVCMOS/LVTTL OUTPUT
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www.IDT.com/go/contactIDT
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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