82P33714_技术文档

82P33714

Synchronous Equipment Timing Source

for Synchronous Ethernet

Datasheet

(SEC); and Telcordia GR-253-CORE/ GR-1244-CORE for Stratum 3

and SONET Minimum Clock (SMC)

DPLL1 generates clocks with PDH, TDM, GSM, CPRI/OBSAI, 10/100/

1000 Ethernet and GNSS frequencies; these clocks are directly avail-

able on OUT1 and OUT8

DPLL2 generates N x 8 kHz clocks up to 100 MHz that are output on

OUT9 and OUT10

APLL1 and APLL2 are connected to DPLL1

APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or

SONET/SDH frequencies

Any of eight common TCXO/OCXO frequencies can be used for the

System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,

24.576 MHz, 25 MHz or 30.72 MHz

The I2C slave, SPI or the UART interface can be used by a host pro-

cessor to access the control and status registers

The I2C master interface can automatically load a device configura-

tion from an external EEPROM after reset

Differential outputs OUT3 to OUT6 output clocks with frequencies

between 1 PPS and 650 MHz

Single ended outputs OUT1, OUT2, OUT7 and OUT8 output clocks

with frequencies between 1 PPS and 125 MHz

Single ended outputs OUT9 and OUT10 output clocks N*8 kHz multi-

ples up to 100 MHz

DPLL1 supports independent programmable delays for each of IN1 to

IN6; the delay for each input is programmable in steps of 0.61 ns with

a range of ~±78 ns

The input to output phase delay of DPLL1 is programmable in steps of

0.0745 ps with a total range of ±20 s

The clock phase of each of the output dividers for OUT1 (from APLL1)

to OUT8 is individually programmable in steps of ~200 ps with a total

range of +/-180°

Highlights

•

Synchronous Equipment Timing Source (SETS) for Synchronous

Ethernet (SyncE) per ITU-T G.8264

•

DPLL1 generates ITU-T G.8262 compliant SyncE clocks, Telcordia

GR-1244-CORE/GR-253-CORE, and ITU-T G.813 compliant SONET/

SDH clocks

•

DPLL2 performs rate conversions for synchronization interfaces or for

other general purpose timing applications

DPLL1 can be configured as a Digitally Controlled Oscillators (DCOs)

for PTP clock synthesis

DCO frequency resolution is [(77760 / 1638400) * 2^-48] or

~1.686305041e-10 ppm

APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to

20 MHz) for: 1000BASE-T and 1000BASE-X

Fractional-N input dividers support a wide range of reference frequen-

cies

•

Locks to 1 Pulse Per Second (PPS) references

DPLLs, APLL1 and APLL2 can be configured from an external

EEPROM after reset

Features

•

Differential reference inputs (IN1 to IN4) accept clock frequencies

between 1 PPS and 650 MHz

Single ended inputs (IN5 to IN6) accept reference clock frequencies

between 1 PPS and 162.5 MHz

Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any

clock reference input

•

Reference monitors qualify/disqualify references depending on activ-

ity, frequency and LOS pins

Automatic reference selection state machines select the active refer-

ence for each DPLL based on the reference monitors, priority tables,

revertive and non-revertive settings and other programmable settings

Fractional-N input dividers enable the DPLLs to lock to a wide range

of reference clock frequencies including: 10/100/1000 Ethernet, 10G

Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI, and GNSS fre-

quencies

•

1149.1 JTAG Boundary Scan

72-QFN green package

•

Applications

•

Access routers, edge routers, core routers

Carrier Ethernet switches

•

Any reference inputs (IN1 to IN6) can be designated as external sync

pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select-

able reference clock input

FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses

that are aligned with the selected external input sync pulse input and

frequency locked to the associated reference clock input

DPLL1 can be configured with bandwidths between 0.09 mHz and

567 Hz

DPLL1 locks to input references with frequencies between 1 PPS and

650 MHz

DPLL2 locks to input references with frequencies between 8 kHz and

650 MHz

Multi-service access platforms

PON OLT

LTE eNodeB

ITU-T G.8264 Synchronous Equipment Timing Source (SETS)

ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC)

ITU-T G.813 Synchronous Equipment Clock (SEC)

Telcordia GR-253-CORE/GR1244-CORE Stratum 3 Clock (S3) and

SONET Minimum Clock (SMC)

•

DPLL1 complies with ITU-T G.8262 for Synchronous Ethernet Equip-

ment Clock (EEC), and G.813 for Synchronous Equipment Clock

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August 21, 2018

82P33714 Datasheet

Description

The 82P33714 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) provides tools to manage timing references,

clock generation and timing paths for SyncE based clocks, per ITU-T G.8264 and ITU-T G.8262. 82P33714 meets the requirements of ITU-T G.8262

for synchronous Ethernet Equipment Clocks (EECs) and ITU-T G.813 for Synchronous Equipment Clocks (SEC). The device outputs low-jitter clocks

that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces.

The 82P33714 accepts four differential reference inputs and two single ended reference inputs that can operate at common GNSS, Ethernet,

SONET/SDH and PDH frequencies that range from 1 Pulse Per Second (PPS) to 650 MHz. The references are continually monitored for loss of sig-

nal and for frequency offset per user programmed thresholds. All of the references are available to both Digital PLLs (DPLLs). The active reference for

each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allowances and based on

the reference monitors and LOS inputs.

The 82P33714 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1 can lock to the clock reference and

align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended reference inputs

to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync signals can

have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 to phase align its frame sync and multi-frame sync outputs with a sync

input without the need use a low bandwidth setting to lock directly to the sync input.

The DPLLs support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode the DPLLs synthesize clocks based on

the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output fre-

quency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses frequency data

acquired while in Locked mode to generate accurate frequencies when input references are not available.

DPLL1 also supports DCO mode. In DCO mode the DPLL control loop is opened and the DCO can be controlled by an IEEE 1588 clock recovery

servo running on an external processor to synthesize IEEE 1588 clocks.

The 82P33714 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter-

mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the

DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked mode.

When used with a suitable system clock, DPLL1 meets the frequency accuracy, pull-in, hold-in, pullout, noise generation, noise tolerance, tran-

sient response, and holdover performance requirements of the following applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, Telcordia GR-

1244 Stratum 3 (S3), Telcordia GR-253-CORE S3 and SONET Minimum Clock (SMC).

DPLL1 can be configured with a range of selectable filtering bandwidths from 0.09 MHz to 567 Hz. The 17 MHz bandwidth can be used to lock the

DPLL directly to a 1 PPS reference. The 92 MHz bandwidth can be used for G.8262/G.813 Option 2, or Telcordia GR-253-CORE S3, or SMC applica-

tions. The bandwidths in the range 1.1 Hz to 8.9 Hz can be used for G.8262/G.813 Option 1 applications. The bandwidth of 1.1 Hz or 2.2 Hz can be

used for Telcordia GR-1244-CORE S3 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications.

DPLL2 is a wideband (BW > 25Hz) frequency translator that can be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048

MHz synchronization interface clock.

For SETS applications per ITU-T G.8264, DPLL1 is configured as an EEC/SEC to output clocks for the T0 reference point and DPLL2 is used to

output clocks for the T4 reference point.

Clocks generated by DPLL1 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The output

clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces.

All 82P33714 control and status registers are accessed through an I2C slave, SPI or UART interface. For configuring the DPLLs, APLL1 and

APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.

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82P33714 Datasheet

Block Diagram

System Clock

SYS PLL

LOS0 / XO_FREQ0

LOS1 / XO_FREQ1

LOS2 / XO_FREQ2

OutDiv

OUT1

OUT2

LOS3

APLL1

APLL2

OutDiv

OUT3 (P/N)

OUT4 (P/N)

IN1(P/N)

IN2(P/N)

IN3(P/N)

DPLL1

(T0)

Reference

monitors

OutDiv

OUT5 (P/N)

OUT6 (P/N)

OUT7

IN4(P/N)

Reference

selection

IN5

IN6

Frac-N input

dividers

OutDiv

OUT8

OutDiv

OUT9

DPLL2

(T4)

OUT10

ex_sync module

FRSYNC_8K_1PPS

MFRSYNC_2K_1PPS

I2C Master

Control and

Status

Registers

I2C Slave,

SPI, UART

JTAG

Figure 1. Functional Block Diagram

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82P33714 Datasheet

Contents

Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Recommendations for Unused Input and Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

RESET OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MS/SL PIN USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Synchronous Ethernet, sonet, and sdh Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Hardware functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

System clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Input Clocks and frame sync. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DPLL Locking Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

APLL1 and APLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Output Clocks & Frame Sync Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Input and output Phase control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Power Supply Filtering Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Microprocessor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

I2C Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

I2C Device Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

I2C Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Supported Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

I2C Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

I2C Boot-up Initialization Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

EEPROM memory map notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

JTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Thermal Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Thermal Release Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Recommended Operation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

CMOS Input / Output Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

LVPECL / LVDS Input / Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

LVDS Input / Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Output Clock Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Input / Output Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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82P33714 Datasheet

Output / output CLOCK TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

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82P33714 Datasheet

1

PIN ASSIGNMENT

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

DPLL2_LOCK

VDDD_1_8

RSTB

VC2

VDDA

OSCi

2

3

4

SDO/I2C_SDA/UART_TX

SCLK/I2C_SCL

CS/I2C_AD0

CLKE/I2C_AD1

SDI/I2C_AD2/UART_RX

MPU_MODE1/I2CM_SCL

MPU_MODE0/I2CM_SDA

MFRSYNC_2K_1PPS

FRSYNC_8K_1PPS

VDDD_1_8

5

6

8XXXXXX

7

XO_FREQ0/LOS0

XO_FREQ1/LOS1

8

9

XO_FREQ2/LOS2

VDDA

VC1

82P33714

10

11

12

13

14

15

16

17

18

IN6

VDDD

IN4_NEG

TMS

TRSTB

TCK

TDI

TDO

38 IN4_POS

37

IN5

Figure 1. Pin Assignment (Top View)

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August 21, 2018

82P33714 Datasheet

2

PIN DESCRIPTION

Table 1: Pin Description

Pin No.

Name

I/O

Type

Description

Global Control Signal

OSCI: Crystal Oscillator System Clock

A clock provided by a crystal oscillator is input on this pin. It is the system clock for the

6

OSCI

I

CMOS

device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ2

MS/SL: Master / Slave Selection

This pin, together with the MS_SL_CTRL bit, controls whether the device is configured as the

Master or as the Slave. The signal level on this pin is reflected by the MASTER_SLAVE bit.

MS_SL = 0: Slave

I

58

MS/SL

CMOS

pull-up

MS_SL = 1: Master (default with internal pull-up)

SONET/SDH: SONET / SDH Frequency Selection

During reset, this pin determines the default value of the IN_SONET_SDH bit:

High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);

Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).

After reset, the value on this pin takes no effect.

SONET/SDH/

LOS3

I

59

52

CMOS

pull-down

LOS3- This pin is used to disqualify input clocks. See input clocks section for more details.

I

RSTB: Reset

Refer to section 2.2 reset operation for details.

RSTB

pull-up

XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency.

XO_FREQ[2:0] Oscillator Frequency (MHz)

000

001

010

011

100

101

110

111

10.000

12.800

13.000

19.440

20.000

24.576

25.000

30.720

XO_FREQ0/

LOS0

XO_FREQ1/

LOS1

XO_FREQ2/

LOS2

7

8

9

I

CMOS

pull-down

LOS0 ~ LOS2 - These pins are used to disqualify input clocks. See input clocks section for

more details. After reset, this pin takes on the operation of LOS0-LOS2

Input Clock and Frame Synchronization Input Signal

IN1_POS / IN1_NEG: Positive / Negative Input Clock 1

A reference clock is input on this pin. This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

31

32

IN1_POS

IN1_NEG

I

PECL/LVDS

CMOS

IN2_POS / IN2_NEG: Positive / Negative Input Clock 1

A reference clock is input on this pin. This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

33

34

IN2_POS

IN2_NEG

IN3_POS / IN3_NEG: Positive / Negative Input Clock 3

A reference clock is input on this pin. This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

35

36

IN3_POS

IN3_NEG

IN4_POS / IN4_NEG: Positive / Negative Input Clock 4

A reference clock is input on this pin. This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

38

39

IN4_POS

IN4_NEG

IN5: Input Clock 5

I

37

41

IN5

IN6

A reference clock is input on this pin. This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

pull-down

IN6: Input Clock 6

I

CMOS

A reference clock is input on this pin. This pin can also be used as a sync input, and in this

case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.

pull-down

7

August 21, 2018

82P33714 Datasheet

Table 1: Pin Description (Continued)

Pin No.

Name

I/O

Type

Description

Output Frame Synchronization Signal

FRSYNC

_8K_1PPS

FRSYNC_8K_1PPS: 8 kHz Frame Sync Output

An 8 kHz signal or a 1PPS sync signal is output on this pin.

43

44

O

CMOS

MFRSYNC

_2K_1PPS

MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output

A 2 kHz signal or a 1PPS sync signal is output on this pin.

Output Clock

30

28

OUT1

OUT2

OUT1 ~ OUT2: Output Clock 1 ~ 2

O

CMOS

PECL/LVDS

CMOS

25

26

OUT3_POS

OUT3_NEG

OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3

This output is set to LVDS by default.

21

22

OUT4_POS

OUT4_NEG

OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4

This output is set to LVDS by default.

71

70

OUT5_POS

OUT5_NEG

OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5

This output is set to LVDS by default.

68

67

OUT6_POS

OUT6_NEG

OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6

This output is set to LVDS by default.

65

63

OUT7

OUT8

OUT7 ~ OUT8: Output Clock 7 ~ 8

61

60

OUT9

OUT10

OUT9 ~ OUT10: Output Clock 9 ~ 10

CMOS

Miscellaneous

VC1: APLL1 VC Output

An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in

parallel) should be connected to this pin.

13

1

VC1

VC2

O

Analog

VC2: APLL2 VC Output

An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in

parallel) should be connected to this pin.

Lock Signal

DPLL2_LOCK

This pin goes high when DPLL2 is locked

DPLL1_LOCK

This pin goes high when DPLL1 is locked

DPLL2_LOCK

DPLL1_LOCK

54

55

O

CMOS

Microprocessor Interface

O

INT_REQ: Interrupt Request

This pin is used as an interrupt request.

57

INT_REQ

CMOS

Tri-state

MPU_MODE[1:0]: Microprocessor Interface Mode Selection

During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol-

lows:

00: I2C mode

01: SPI mode

10: UART mode

11: I2C master (EEPROM) mode

I2CM_SCL: Serial Clock Line

MPU_MODE1/

I2CM_SCL

46

45

I/O

pull-up

CMOS/

Open Drain

MPU_MODE0/

I2CM_SDA

In I2C master mode, the serial clock is output on this pin.

I2CM_SDA: Serial Data Input for I2C Master Mode

In I2C master mode, this pin is used as the input for the serial data.

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August 21, 2018

82P33714 Datasheet

Table 1: Pin Description (Continued)

Pin No.

Name

I/O

Type

Description

SDI: Serial Data Input

In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri-

ally clocked into the device on the rising edge of SCLK.

SDI/I2C_AD2/

UART_RX

I

I2C_AD2: Device Address Bit 2

In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.

47

CMOS

pull-down

UART_RX

In UART mode, this pin is used as the receive data (UART Receive)

CLKE: SCLK Active Edge Selection

In Serial mode, this pin is an input, it selects the active edge of SCLK to update the SDO:

High - The falling edge;

Low - The rising edge.

I

48

49

50

CLKE/I2C_AD1

CS/I2C_AD0

CMOS

pull-down

I2C_AD1: Device Address Bit 1

In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.

CS: Chip Selection

In Serial modes, this pin is an input. A transition from high to low must occur on this pin for

each read or write operation and this pin should remain low until the operation is over.

I

pull-up

I2C_AD0: Device Address Bit 0

In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.

SCLK: Shift Clock

In Serial mode, a shift clock is input on this pin.

Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated

on the active edge of SCLK. The active edge is determined by the CLKE.

I

SCLK/I2C_SCL

pull-down

I2C_SCL: Serial Clock Line

In I2C mode, the serial clock is input on this pin.

SDO: Serial Data Output

In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked

out of the device on the active edge of SCLK.

SDO/I2C_SDA/

UART_TX

I/O

pull-up

CMOS/

Open Drain

I2C_SDA: Serial Data Input/Output

In I2C mode, this pin is used as the input/output for the serial data.

51

I2C_SDA

UART_TX:

In UART mode, this pin is used as the transmit data (UART Transmit)

JTAG (per IEEE 1149.1)

TMS: JTAG Test Mode Select

The signal on this pin controls the JTAG test performance and is sampled on the rising edge

of TCK.

I

14

15

TMS

CMOS

pull-up

TRSTB: JTAG Test Reset (Active Low)

A low signal on this pin resets the JTAG test port.

This pin should be connected to ground when JTAG is not used.

I

TRSTB

pull-up

TCK: JTAG Test Clock

The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge

of TCK and TDO is updated on the falling edge of TCK.

If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely

retain their state.

I

16

17

TCK

TDI

CMOS

pull-down

TDI: JTAG Test Data Input

The test data are input on this pin. They are clocked into the device on the rising edge of

TCK.

I

pull-up

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August 21, 2018

82P33714 Datasheet

Table 1: Pin Description (Continued)

Pin No.

Name

I/O

Type

Description

TDO: JTAG Test Data Output

The test data are output on this pin. They are clocked out of the device on the falling edge of

TCK.

O

18

TDO

CMOS

tri-state

TDO pin outputs a high impedance signal except during the process of data scanning.

Power & Ground

2, 3, 4, 5, 10 11, 12

20, 24, 69, 72

27, 29, 64, 66

40, 62

VDDA

VDDAO

VDDDO

VDDD

Power

Ground

-

VDDA: Analog Core Power - +3.3V DC nominal

VDDAO: Analog Output Power - +3.3V DC nominal

VDDDO: Digital Output Power - +3.3V DC nominal

VDDD: Digital Core Power - +3.3V DC nominal

VDDD_1_8: Digital Core Power - +1.8V DC nominal

VSSAO: Ground

42, 53

VDDD_1_8

VSSAO

VSS

19,23

73 (e_PAD)

-

VSS: Ground

Other

IC: Internal Connection

Internal Use. This pin must be left open for normal operation.

56

IC

-

Differential Clock Outputs

2.1

RECOMMENDATIONS FOR UNUSED INPUT

AND OUTPUT PINS

All unused differential outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

2.1.1

INPUTS

Control Pins

2.2

RESET OPERATION

All control pins have internal pull-ups or pull-downs; additional resis-

tance is not required but can be added for additional protection. A 1kΩ

resistor can be used.

The device must be reset properly in order to ensure operations

conform with specification.

To properly reset the device, the RSTB pin must be held at a low

value for at least 50 usec. The device should be brought out of reset

only at the time when power supplies are stabilized and the system

clock is available on OSCi pin. The RSTB can be held low until this time,

or pulsed low for at least 50us after this time.

Single-Ended Clock Inputs

For protection, unused single-ended clock inputs should be tied to

ground.

Differential Clock Inputs

For applications not requiring the use of a differential input, both

*_POS and *_NEG can be left floating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from _POS to ground.

The bootstrap pins (XO_FREQ[2:0], MPU_MODE[1:0], I2C_AD[2:0],

MS/SL, SONET/SDH) need to be held at desired states for at least 2ms

after de-assertion of RSTB pin to allow correct sampling. See Figure 3

for detail.

2.1.2

OUTPUTS

If loading from an EEPROM, the maximum time from RSTB de-

assert to have stable clocks is 100ms. Note that if there is a bad

EEPROM read sequence and the EEPROM loading is repeated once or

twice (three times halts the device), then this time can be 2 or 3 times

longer respectively. If not loading from EEPROM the maximum time

from RSTB de-assert to have stable clocks is 10ms.

Status Pins

For applications not requiring the use of a status pin, we recommend

bringing out to a test point for debugging purposes.

Single-Ended Clock Outputs

All unused single-ended clock outputs can be left floating, or can be

brought out to a test point for debugging purposes.

An on-board reset circuit or a commercially available voltage

supervisory can be used to generate the reset signal. It is also feasible

to use a standalone power-up RC reset circuit. When using a power-up

RC reset circuit, careful consideration must be taken into account to fine

tune the circuit properly based on each power supply's specification to

ensure the power supply rise time is fast enough with respect to the RC

time constant of the RC circuit.

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August 21, 2018

82P33714 Datasheet

VDDD

VDDA

OSCI

RSTB

Bootstrap

Pins*

50ȝs

2ms

* Bootstrap pins are: XO_FREQ[2:0], MPU_MODE[1:0], I2C_AD[2:0], MS/SL, SONET/SDH

Figure 2. Reset timing diagram

For more information, see AN-901, How to Implement Master/Slave

for SETS and SMU Devices on Timing Redundancy Designs.

2.3

MS/SL PIN USAGE

The MS/SL pin is used for timing card redundancy applications

where there is a primary and secondary timing card in the system. For

other applications, this pin should be left unconnected or connected to

an external pull-up.

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August 21, 2018

82P33714 Datasheet

3

FUNCTIONAL DESCRIPTION

3.1

SYNCHRONOUS ETHERNET, SONET, AND

SDH ARCHITECTURE

Single

Blade

82P33714 integrates key features that allows the device to be used

in Synchronous Ethernet, SONET and SDH applications. There are sev-

eral key synchronization standards that are important to meet for such a

system, they are:

SyncE/

SONET

/SDH

PHY

SyncE-TxCK

SyncE-RxCK

LOS

A

P

L

Ethernet

•

ITU-T Recommendation G.8262, Timing characteristics of Syn-

chronous Ethernet Equipment slave clock (EEC)

ITU-T Recommendation G.8264, Distribution of timing through

packet networks

ITU-T Recommendation G.812, Timing requirements of slave

clocks suitable for use as node clocks in synchronization networks.

ITU-T Recommendation G.813, Timing characteristics of SDH

equipment slave clocks (SEC).

GR-253-CORE - Telcordia Technologies Generic Requirements -

Issue 5, October 2009

GR-1244-CORE - Telcordia Technologies Generic Requirements -

Issue 4, October 2009

SyncE (T0)

BITS/SSU

CDR

T4

TCXO

Figure 3. SyncE/SONET/SDH single blade application

Figure 4 shows an active/redundant architecture, as described

before it is usually used in Telecom equipment that are designed to have

a redundant timing card in case of primary timing card failure. The

redundant timing card mimics the output of the active timing card, so in

case of failure the system will still provide proper synchronization.

ATIS-0900101.2006 - T1.101 - Synchronization Interface Standard

Figure 3 shows a single blade architecture that it is usually used in

simple equipment.

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August 21, 2018

82P33714 Datasheet

Timing Card

Line Card

SSU/BITS

SyncE-TxCK

A

P

L

SyncE (T0)

A

P

L

SyncE-TxCK

SyncE-RxCK

LOS

SyncE/

SONET/

SDH

DPLL1

T4

DPLL2

PHY

XO

TCXO

Active/

redundant

connection

Line Card

A

P

L

SyncE-TxCK

SyncE-RxCK

LOS

SyncE/

SONET/

SDH

DPLL1

DPLL2

Timing Card

PHY

SSU/BITS

XO

A

P

L

SyncE-TxCK

SyncE (T0)

T4

Line Card

A

P

L

SyncE-TxCK

SyncE-RxCK

LOS

TCXO

SyncE/

SONET/

SDH

DPLL1

DPLL2

PHY

XO

Figure 4. SyncE/SONET/SDH active/redundant application

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August 21, 2018

82P33714 Datasheet

3.2.2

MODES OF OPERATION

DPLL1 Operating Mode

3.2

HARDWARE FUNCTIONAL DESCRIPTION

SYSTEM CLOCK

3.2.2.1

3.2.1

The DPLL1 can operate in several different modes as shown in

Table 3.

A crystal oscillator should be used as an input on the OSCI pin. This

clock is provided for the device as a system clock. The system clock is

used as a reference clock for all the internal circuits. The active edge of

the system clock can be selected by the OSC_EDGE bit in xo_freq_cnfg

register.

The DPLL1 operating mode is controlled by the DPLL1_OPERAT-

ING_MODE[4:0] bits.

Table 3: DPLL1 Operating Mode Control

Eight common oscillator frequencies can be used for the stable Sys-

tem Clock. The oscillator frequency can be set by pins or by xo_fre-

q_cnfg register as shown in Table 2.

DPLL1_OPERATING_MODE[4:0]

DPLL1 Operating Mode

00000

00001

Automatic

Forced - Free-Run

Forced - Holdover

Reserved

Table 2: Oscillator Frequencies

00010

xo_freq[2:0] pins

00011

Oscillator Frequency (MHz)

xo_freq_cnfg[2:0] bits

00100

Forced - Locked

Forced - Pre-Locked2

Forced - Pre-Locked

Forced - Lost-Phase

Reserved

00101

000

10.000

00110

00111

001

010

011

12.800

13.000

19.440

01000-01001

DCO write frequency

see Chapter 3.2.2.1.6

01010

10010 - 11111

10011-11111

Reserved

100

20.000

101

110

111

24.576

25.000

30.720

When the operating mode is switched automatically, the operation of

the internal state machine is shown in Figure 5.

Whether the operating mode is under external control or is switched

automatically, the current operating mode is always indicated by the

DPLL1_OPERATING_STS[4:0] bits. When the operating mode

switches, the DPLL1_OPERATING_STS bit will be set. If the

DPLL1_OPERATING_STS bit is ‘1’, an interrupt will be generated if the

corresponding mask bit is set to “1”, the mask bit is set to “0” by default.

An offset from the nominal frequency may be compensated by set-

ting the NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is

within ±741 ppm.

The crystal oscillator should be chosen accordingly to meet different

applications and standard requirements. (See AN-807 Recommended

Crystal Oscillators for NetSynchro WAN PLL).

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August 21, 2018

82P33714 Datasheet

1

Free-Run m ode

3

2

Pre-Locked

mode

4

5

Locked

mode

6

10

Holdover

mode

9

8

7

11

Pre-Locked2

mode

12

15

Lost-Phase

mode

13

14

Figure 5. DPLL Automatic Operating Mode

Notes to Figure 5:

1. Reset.

2. An input clock is selected.

3. The DPLL selected input clock is disqualified AND No qualified input clock is available.

4. The DPLL selected input clock is switched to another one.

5. The DPLL selected input clock is locked (the DPLL_LOCK bit is ‘1’).

6. The DPLL selected input clock is disqualified AND No qualified input clock is available.

7. The DPLL selected input clock is unlocked (the DPLL_LOCK bit is ‘0’).

8. The DPLL selected input clock is locked again (the DPLL_LOCK bit is ‘1’).

9. The DPLL selected input clock is switched to another one.

10. The DPLL selected input clock is locked (the DPLL_LOCK bit is ‘1’).

11. The DPLL selected input clock is disqualified AND No qualified input clock is available.

12. The DPLL selected input clock is switched to another one.

13. The DPLL selected input clock is disqualified AND No qualified input clock is available.

14. An input clock is selected.

15. The DPLL selected input clock is switched to another one.

The causes of Item 4, 9, 12, 15 - ‘the DPLL selected input clock is

switched to another one’ - are: (The DPLL selected input clock is dis-

qualified AND Another input clock is switched to) OR (In Revertive

switching, a qualified input clock with a higher priority is switched to) OR

(The DPLL selected input clock is switched to another one Forced selec-

tion).

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August 21, 2018

82P33714 Datasheet

3.2.2.1.1 Free-Run Mode

In the first two seconds when the DPLL1 attempts to lock to the

selected input clock, the starting bandwidth and damping factor are

used. They are set by the DPLL1_START_BW[4:0] bits and the

DPLL1_START_DAMPING[2:0] bits respectively.

In Free-Run mode, the DPLL1 output refers to the system clock and

is not affected by any input clock. The accuracy of the DPLL1 output is

equal to that of the system clock.

During the acquisition, the acquisition bandwidth and damping factor

are used. They are set by the DPLL1_ACQ_BW[4:0] bits and the

DPLL1_ACQ_DAMPING[2:0] bits respectively.

3.2.2.1.2 Pre-Locked Mode

In Pre-Locked mode, the DPLL1 output attempts to track the

selected input clock.

When the DPLL1 is locked, the locked bandwidth and damping factor

are used. They are set by the DPLL1_LOCKED_BW[4:0] bits and the

DPLL1_LOCKED_DAMPING[2:0] bits respectively.

The Pre-Locked mode is a secondary, temporary mode.

3.2.2.1.3 Locked Mode

The corresponding bandwidth and damping factor are used when the

DPLL1 operates in different locking stages: starting, acquisition and

locked, as controlled by the device automatically.

In Locked mode, the DPLL1 is locked to the input clock. The phase

and frequency offset of the DPLL1 output track those of the DPLL1

selected input clock.

The locked bandwidth is selectable can be set as shown in Table 4.

For a closed loop, different bandwidths and damping factors can be

used depending on DPLL locking stages: starting, acquisition and

locked.

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August 21, 2018

82P33714 Datasheet

Table 4: DPLL1 Locked Bandwidth

DPLL1_LOCKED_BW[4:0]

00000

BW

Application

0.090 mHz

00001

00010

00011

00100

00101

00110

00111

01000

0.27 mHz

0.90 mHz

2.9 mHz

4.3 mHz

8.7 mHz

17 mHz

35 mHz

69 mHz

stratum 3E, BW<1mHz

G.812 Type I, BW< 3mHz

GR-253 stratum 3, SMC and EEC-

option, 2, BW < 0.1Hz

01001

92 mHz

01010

01011

277 mHz

554 mHz

EEC-option 1, 1< BW <10

GR-1244 stratum 3, BW<3Hz

01100

01101

01110

01111

1.1 Hz

2.2 Hz

4.4 Hz

8.9 Hz

EEC-option 1, 1< BW <10

GR-1244 stratum 3, BW<3Hz

EEC-option 1, 1< BW <10

10000

10001

18 Hz

35 Hz

10010

71 Hz

10011

142 Hz

283 Hz

567 Hz

Reserved

10100

10101

10110-11111

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August 21, 2018

82P33714 Datasheet

3.2.2.1.4 Pre-Locked2 Mode

Figure 6 shows the DCO being controlled by writing a frequency off-

set word into the DCO, then by changing temporarily the DCO’s fre-

quency, the phase of the clock (or 1PPS) being generated by the DCO

will also change. The output phase change is the product of the fre-

quency change times the duration for which the frequency change is

applied for. Because the DCO's frequency word has a very fine resolu-

tion, the output phase can be adjusted in very fine steps. In this case the

clock recovery servo algorithm controls the bandwidth and phase slope

limiting. The frequency offset word can be written into DPLL1_hold-

over_freq_cnfg[39:0] bits of frequency configuration registers for

DPLL12. This value is 2’s complement signed number. Total range is +/-

92 ppm, and the DCO programming resolution is [(77760 / 1638400) *

2^-48] or ~1.686305041e-10 ppm. The DCO resolution is affected by the

offset applied into the DCO, so when writing into the DCO, the program-

ming resolution is [(77760/1638400) * 2^-48] * (1 + offset-in-ppm / 1e6).

In Pre-Locked2 mode, the DPLL1 output attempts to track the

selected input clock.

The Pre-Locked2 mode is a secondary, temporary mode.

3.2.2.1.5 Lost-Phase Mode

In Lost-Phase mode, the DPLL1 output attempts to track the selected

input clock.

The Lost-Phase mode is a secondary, temporary mode.

3.2.2.1.6 DCO control modes

Figure 6 show a high level diagram of the DCO control architecture, it

shows the DCO in DPLL1 being controlled. The DCO is a phase accu-

mulator running at an internal clock. The DCO is controlled by a digital

word that can represent phase offset or frequency offset. In the case of

an IEEE 1588 application, the external processor will run the clock

recovery servo algorithm and it will generate a frequency offset word to

control the DCO.

Controlling the DCO’s frequency for smaller fine resolution phase

changes is a good method, but for bigger phase changes it is better to

use the snap-alignment method. The snap phase alignment is fast but

only provides coarse adjustment. The 82P33714 allows for both the fine

phase adjustment by controlling the frequency of the DCO and the

coarse phase adjustment by snap-aligning the output clock (or 1PPS),

for details, see section 3.2.7.3 Output Phase control on page 31.

The DCO control modes can be set by registers DPLL1_operating_-

mode_cnfg for DPLL1.

S y s te m

C lo c k

O s c illa to r

D P L L 1

O u tp u t

C lo c k

P D

L P F

D C O

+

F re q u e n c y

O ffs e t

M ic r o p o r t

I n te r fa c e

M ic ro p o rt

Figure 6. DCO frequency offset control functional block diagram

3.2.2.1.7 Holdover Mode

is selected by the man_holdover bit, auto_avg bit, the hist_mode [1:0]

bits, and the avg_mode[1:0] bits in DPLL1_holdover_mode_cnfg regis-

ters as shown in Table 5.

In Holdover mode, the DPLL1 resorts to the stored frequency data

acquired in Locked mode to control its output. The DPLL1 output is not

phase locked to any input clock. The frequency offset acquiring method

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August 21, 2018

82P33714 Datasheet

Table 5: Frequency Offset Control in Holdover Mode

man_hold

auto_avg

hist_mode [1:0]

avg_mode[1:0]

Frequency Offset Acquiring Method

over

0

don’t-care

Averaged

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Current averaged value with holdover filter BW of ~0.18mHz

Current averaged value with holdover filter BW of ~1.5mHz

0

1

0

Current averaged value with holdover filter BW of ~12mHz

Current averaged value with holdover filter BW of ~0.15Hz

Averaged value 1 second before with holdover filter BW of ~0.18mHz

Averaged value 1 second before with holdover filter BW of ~1.5mHz

Averaged value 1 second before with holdover filter BW of ~12mHz

Averaged value 1 second before with holdover filter BW of ~0.15Hz

Averaged value 8 seconds before with holdover filter BW of ~0.18mHz

Averaged value 8 seconds before with holdover filter BW of ~1.5mHz

Averaged value 8 seconds before with holdover filter BW of ~12mHz

Averaged value 8 seconds before with holdover filter BW of ~0.15Hz

Averaged value 64 seconds before with holdover filter BW of ~0.18mHz

Averaged value 64 seconds before with holdover filter BW of ~1.5mHz

Averaged value 64 seconds before with holdover filter BW of ~12mHz

Averaged value 64 seconds before with holdover filter BW of ~0.15Hz

Manual - values is set by DPLL1_holdover_freq_cnfg register

0

1

don’t-care

The default value for holdover mode is set to current averaged value

with holdover filter BW of ~1.5mHz. In this mode the initial frequency off-

set is better than 1.1e-5ppm assuming that there is no in-band jitter/wan-

der at the input just before entering holdover state. The default mode is

used for Telcordia GR-1244, Telcordia GR-253, ITU-T G.8262 and ITU-T

G.813 to meet holdover requirements.

3.2.2.1.8 Hitless Reference Switching

Bit hitless_switch_en in DPLL1_mon_sw_pbo_cnfg register can be

used to set hitless reference switching. When a Hitless Switching (HS)

event is triggered, the phase offset of the selected input clock with

respect to the DPLL1 output is measured. The device then automatically

accounts for the measured phase offset and compensates for the appro-

priate phase offset into the DPLL output so that the phase transients on

the DPLL1 output are minimized. The input frequencies should be set to

frequencies equal to 8 kHz or higher.

In Manual Mode, the frequency offset is set by the DPLL1_hold-

over_freq_cnfg[39:0] bits. The accuracy is1.686305041e-10 ppm, how-

ever the resolution is affected by the frequency offset applied, so when

writing the frequency offset, the programming resolution is [(77760/

1638400) * 2^-48] * (1 + offset-in-ppm / 1e6).

If hitless_switch_en is set to “1”, a HS event is triggered if any one of

the following conditions occurs:

The offset value, which is acquired by the modes shown in Table 5,

can be read from the holdover_freq_cnfg[39:0] bits by setting the

read_avg bit to “1”. If read_avg bit is set to “0” then the value in hold-

over_freq_cnfg[39:0] bits is the value written into it. The value is 2’s

complement signed number, and the total range is +/- 92 ppm.

• DPLL1 selected input clock switches to a different reference

• DPLL1 exits from Holdover mode or Free-Run mode

For the two conditions, the phase transients on the DPLL1 output are

minimized to be no more than 0.61 ns with HS. The HS can also be fro-

zen at the current phase offset by setting the hitless_switch_freeze bit in

DPLL1_mon_sw_pbo_cnfg register. When the HS is frozen, the device

will ignore any further HS events triggered by the above two conditions,

and maintain the current phase offset.

The holdover frequency resolution is calculated as follows:

Holdover Frequency resolution: HO_freq_res = (77760/1638400) *

2^-48

The Holdover value read from register bits holdover_freq_cnfg[[39:0]

must be converted to decimal:

When the HS is disabled, there may be a phase shift on the DPLL1

output, as the DPLL1 output tracks back to 0 degree phase offset with

respect to the DPLL1 selected input clock. This phase shift can be lim-

ited; see section 3.2.2.1.9 Phase Slope Limit.

HO_value_dec = holdover_freq_cnfg[39:0] value in decimal

The frequency offset in ppm is calculated as follows:

Holdover Frequency Offset (ppm) = (HO_freq_res * HO_value_dec)/

(1-((HO_freq_res * HO_value_dec)/1e6))

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3.2.2.1.9 Phase Slope Limit

When the operating mode is switched automatically, the operation of

the internal state machine is shown in Figure 7:

To meet the phase slope requirements of Telcordia and new ITU-T

standards, both DPLL1 provides a phase slope limiting feature to limit

the rate of output phase movement. The limit level is selectable via

DPLL1_ph_limit[2:0] bits in DPLL1_bw_overshoot_cnfg register. The

options are shown in Table 6.

1

Free-Run mode

Table 6: DPLL1 Phase Slope Limit

2

DPLL1_ph_limit[2:0]

Phase Slope Limit

000

61µs/s (GR-1244 ST3)

885ns/s (GR-1244-CORE ST2 and 3E,

GR-253-CORE ST3 and

001

Locked mode

G.8262 EEC option 2)

7.5 µs/s (G.813 opt1, G.8262 EEC-

option 1)

010

3

4

011

100

101

110

111

unlimited / 1.4 ms/s (default)

1 ns/s

5 ns/s

Holdover

mode

10 ns/s

programmable (default)*

*Note: The default phase slope limiting is set to programmable with a default

value set to 0 ns/s, therefore the phase slope limiting must be set to the proper

value to meet different standards according to this table.

5

Figure 7. DPLL2 Automatic Operating Mode

The programmable phase slope limiting can be set by writing into

registers DPLL1_prog_ph_limit_cnfg[23:0]. The range of the program-

mable limit is 1484.3614 us/s.

Notes to Figure 7:

1. Reset.

2. An input clock is selected.

3.2.2.1.10 Frequency Offset Limit

3. (The DPLL2 selected input clock is disqualified) OR (A qualified

input clock with a higher priority is switched to) OR (The DPLL2

selected input clock is switched to another one by Forced selec-

tion).

The DPLL1 output is limited to be within the programmed DPLL hard

limit (refer to Chapter 3.2.4.3).

3.2.2.2

DPLL2 Operating Mode

4. An input clock is selected.

5. No input clock is selected.

The DPLL2 operating mode is controlled by the DPLL2_OPERAT-

ING_MODE[2:0] bits, as shown in Table 7. DPLL2 is disabled by default,

write “0” to bit DPLL2_pdn in pdn_conf register to enable it.

3.2.2.2.1 Free-Run Mode

Table 7: DPLL2 Operating Mode Control

In Free-Run mode, the DPLL2 output refers to the system clock and

is not affected by any input clock. The accuracy of the DPLL2 output is

equal to that of the system clock.

DPLL2_OPERATING_MODE[2:0]

DPLL2 Operating Mode

000

001

010

100

Automatic

3.2.2.2.2 Locked Mode

Forced - Free-Run

Forced - Holdover

Forced - Locked

In Locked mode, the DPLL2 is locked to the input clock. The phase

and frequency offset of the DPLL2 output track those of the DPLL2

selected input clock.

DPLL2 is a wide BW DPLL, with loop bandwidth higher than 25Hz.

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82P33714 Datasheet

3.2.2.2.3 Holdover Mode

The 82P33714 supports Telecom and Ethernet frequencies from

1PPS up to 650 MHz.

In Holdover mode, the DPLL2 has 2 modes of operation for the hold-

over set by DPLL2_auto_avg bit in DPLL2_holdover_mode_cnfg regis-

ter.

Any of the input clocks can be used as a frame pulse or sync signal.

The SYNC_sel[3:0] bits in INn_los_sync_cnfg (1 < n < 6) registers sets

which pin is used as frame pulse or sync signal.

DPLL2_auto_avg = 0: holdover frequency is the instantaneous value

of integral path just before entering holdover. If the DPLL2 was locked to

an input clock reference that has no in-band jitter/wander and was then

manually set to go into holdover, the initial frequency accuracy is

4.4X10-8 ppm.

IN1 to IN6 can be used for 2 kHz, 4 kHz or 8 kHz frame pulses or

1PPS sync signal. The input frequency should match the setting in the

sync_freq[1:0] bits in DPLL1_input_mode_cnfg register.

3.2.3.1

Input Clock Pre-divider

DPLL2_auto_avg = 1: averaged frequency value is used as holdover

frequency. The holdover average bandwidth is about 1.5mHz. In this

mode the initial frequency offset is 1.1e-5ppm assuming that there is no

in-band jitter/wander at the input just before entering holdover state.

Each input clock is assigned an internal Pre-divider. The Pre-divider

can be used to divide the clock frequency down to a convenient fre-

quency, such as 8 kHz for the internal DPLL1. Note that T1 and E1 refer-

ences can exhibit substantial jitter with frequencies above 4 kHz. These

references should be applied to DPLL1 without being divided down to

8kHz.

3.2.2.2.4 Frequency Offset Limit

The DPLL2 output is limited to be within the DPLL hard limit (refer to

Chapter 3.2.4.3).

For IN1 ~ IN6, the DPLL required frequency is set by the correspond-

ing IN_FREQ[3:0] bits.

3.2.3

INPUT CLOCKS AND FRAME SYNC

The 82P33714 has 6 input clocks that can also be used for frame

sync pulses.

Table 8: IN_FREQ[3:0] DPLL Frequency

IN_FREQ[3:0] Bits

DPLL Frequency

0000

0001

8 kHz

1.544 MHz / 2.048 MHz (depends on SONET/ SDH bit)

0010

6.48 MHz

Reserved

2 kHz

0011–1000

1001

1010

4 kHz

1011

1 PPS

1100

6.25 MHz

Reserved

1101–1111

Each Pre-divider consists of an FEC divider and a DivN divider,.

IN1~IN4 also include an HF (High Frequency) divider. Figure 8 shows a

block diagram of the pre-dividers for an input clock.

When the DivN divider is used for INn (1  n  6), the division factor

setting should observe the following order:

1. Write the lower eight bits of the division factor to the

PRE_DIVN_VALUE[7:0] bits;

For 1 PPS, 2 kHz, 4 kHz or 8 kHz input clock frequency only, the Pre-

divider should be bypassed by setting INn_DIV[1:0] bits = “0” (1 < n < 4),

DIRECT_DIV bit = “0”, and LOCK_8K bit = “0”. The corresponding IN_-

FREQ[3:0] bits should be set to match the input frequency.

2. Write the higher eight bits of the division factor to the

PRE_DIVN_VALUE[14:8] bits.

The division factor is calculated as follows:

Division Factor = (the frequency of the clock input to the DivN

divider ÷ the frequency of the DPLL required clock set by the IN_-

FREQ[3:0] bits) - 1

The HF divider, which is available for IN1 ~ IN4, should be used

when the input clock is higher than () 162.5 MHz. The input clock can

be divided by 4, 5 or can bypass the HF divider, as determined by the

INn_DIV[1:0] bits (1 < n < 4).

The Pre-divider configuration and the division factor setting depend

on the input clock on one of the IN1 ~ IN6 pins and the DPLL required

clock.

The DivN divider can be bypassed, as determined by the

DIRECT_DIV bit and the LOCK_8K bit. When DivN divider is bypassed,

the corresponding IN_FREQ[3:0] bits should be set to match the input

frequency. DIVN must be bypassed on a reference clock input that is

also associated with another reference input used as SYNC.

For the fractional input divider, the FEC divider, each input clock has

a 16-bit (fec_divp_cnfg[15:0]) that represents the value of the numerator

and a 16-bit (fec_divq_cnfg[15:0]) that represents the value of the

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82P33714 Datasheet

FEC Division Factor = (fec_divp_cnfg[15:0]) ÷

(fec_divq_cnfg[15:0])

denominator of FEC divider. The FEC division factor is calculated as fol-

lows:

Pre-Divider

DIRECT_DIV bit

LOCK_8K bit

INn_DIV[1:0] bits

1 < n <4

Input Clock INn

HFDivider

00

1 < n < 6

1

0

(for IN1 ~ IN4)

DPLL

Clock

FEC Divider (P/Q)

DivNDivider

01

1< n < 19440

Figure 8. Pre-divider for an input clock

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82P33714 Datasheet

3.2.3.2

Input Clock Quality Monitoring

responding BUCKET_SEL[1:0] bits. Each leaky bucket configuration

consists of four elements: upper threshold, lower threshold, bucket size

and decay rate.

The qualities of all the input clocks are always monitored in the fol-

lowing aspects:

• Activity

The bucket size is the capability of the accumulator. If the number of

the accumulated events reach the bucket size, the accumulator will stop

increasing even if further events are detected. The upper threshold is a

point above which a no-activity alarm is raised. The lower threshold is a

point below which the no-activity alarm is cleared. The decay rate is a

certain period during which the accumulator decreases by 1 if no event

is detected.

• Frequency

Activity and frequency monitoring are conducted on all the input

clocks.

The qualified clocks are available for selection for the 2 DPLLs.

3.2.3.2.1 Activity Monitoring

The leaky bucket configuration is programmed by one of four groups

of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_

THRESHOLD_n_DATA[7:0] bits, the LOWER_THRESHOLD_n_

DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’

is 0 ~ 3.

Activity is monitored by using an internal leaky bucket accumulator,

as shown in Figure 9.

Each input clock is assigned an internal leaky bucket accumulator.

The input clock is monitored for each period of 128 ms, the internal leaky

bucket accumulator is increased by 1 when an event is detected; and it

is decreased by 1 when no event is detected within the period set by the

decay rate. The event is that an input clock drifts outside (>) ±500 ppm

with respect to the system clock within a 128 ms period.

The no-activity alarm status of the input clock is indicated by the

INn_NO_ACTIVITY_ALARM bit (6  n  1).

The input clock with a no-activity alarm is disqualified for clock selec-

tion for the DPLLs.

There are four configurations (0 - 3) for a leaky bucket accumulator.

The leaky bucket configuration for an input clock is selected by the cor-

clock signal with events

clock signal with no event

Input Clock

Decay

Rate

Bucket Size

Upper Threshold

Leaky Bucket Accumulator

No-activity Alarm Indication

Lower Threshold

0

Figure 9. Input Clock Activity Monitoring

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82P33714 Datasheet

3.2.3.2.2 Frequency Monitoring

When the input clock frequency rises to above the hard alarm reject-

ing threshold, the INn_FREQ_HARD_ALARM bit (6  n  1) will alarm

and indicate ‘1’. The alarm will remain until the frequency is down to

below the hard alarm accepting threshold, then the INn_FRE-

Q_HARD_ALARM bit will return to ‘0’. There is a hysteresis between fre-

quency monitoring, refer to Figure 10.

Frequency is monitored by comparing the input clock with a refer-

ence clock. The reference clock can be derived from the system clock or

the output of DPLL1, as determined by the FREQ_MON_CLK bit.

Each reference clock has a hard frequency monitor and a soft fre-

quency monitor. Both monitors have two thresholds, rejecting threshold

and accepting threshold, which are set in HARD_FREQ_MON_-

THRESHOLD[7:0] and SOFT_FREQ_MON_THRESHOLD[7:0]. So four

frequency alarm thresholds are set for frequency monitoring: Hard Alarm

Accepting Threshold, Hard Alarm Rejecting Threshold, Soft Alarm

Accepting Threshold and Soft Alarm Rejecting Threshold.

The soft alarm is indicated by the INn_FREQ_SOFT_ALARM bit

(6  n  1) in the same way as hard alarm.

The input clock with a frequency hard alarm is disqualified for clock

selection for the DPLLs, but the soft alarm doesn’t affect the clock selec-

tion for the DPLLs.

The frequency hard alarm accepting threshold can be calculated as

follows:

The frequency of each input clock with respect to the reference clock

can be read by doing the following step:

1. Read the value in the IN_FREQ_VALUE[7:0] bits and calculate

as follows:

Input Clock Frequency (ppm) = IN_FREQ_VALUE[7:0] * FRE-

Q_MON_FACTOR[3:0]

Frequency Hard Alarm Accepting Threshold (ppm) = (HARD_FRE-

Q_MON_THRESHOLD[7:4] + 1) X FREQ_MON_FACTOR[3:0] (b3~0,

FREQ_MON_FACTOR_CNFG)

The frequency hard alarm rejecting threshold can be calculated as

follows:

Note that the value set by the FREQ_MON_FACTOR[3:0] bits

depends on the application.

Frequency Hard Alarm Rejecting Threshold (ppm) = (HARD_FRE-

Q_MON_THRESHOLD[3:0] + 1) X FREQ_MON_FACTOR[3:0] (b3~0,

FREQ_MON_FACTOR_CNFG)

Rejecting threshold

Accepting threshold

accepted

rejected (alarmed)

accepted

Figure 10. Hysteresis Frequency Monitoring

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82P33714 Datasheet

3.2.3.3

Input Clock Selection

clocks quality monitoring do not affect the input clock selection if Forced

selection is used.

For DPLL1 and DPLL2, the DPLL1/2_INPUT_SEL[3:0] bits (register

DPLL1/2_input_sel_cnfg) determine the input clock selection, as shown

in Table 9:

3.2.3.3.2 Automatic Selection

In Automatic selection, the input clock selection is determined by

input clock being valid, priority and input clock configuration. The input

clock is declared valid depending on the results of input clock quality

monitoring (refer to Chapter 3.2.3.2). The input clock can be configured

to be valid and therefore be allowed to participate in the locking process

by setting to “0” the corresponding INn_VALID bit (6  n  1) in

DPLL_remote_input_valid_cnfg register, by default all the inputs are not

valid, and therefore the user must set the corresponding bit to “0” in

order to allow the DPLL to lock to a particular input clock. Within all the

qualified input clocks, the one with the highest priority is selected. The

priority is set by the corresponding INn_SEL_PRIORITY[3:0] bits in

DPLL_INn_sel_priority_cnfg (6 n  1). If more than one qualified input

clock INn is available, then it is important to set appropriate priorities to

the input clocks, two input clocks must not have the same priority. This

process is shown in Figure 11.

Table 9: Input Clock Selection for DPLL1 and DPLL2

DPLL1/2 _INPUT_SEL[3:0]

Input Clock Selection

0000

Automatic selection

Reserved

0001 ~ 0010

0011 ~ 0110

0111 ~ 1000

1001 ~ 1010

1011 ~ 1111

Forced selection (IN1 ~ IN4)

Reserved

Forced selection (IN5 ~ IN6)

Reserved

3.2.3.3.1 Forced Selection

In Forced selection, the selected input clock is set by the DPLL1_IN-

PUT_SEL[3:0] and DPLL2_INPUT_SEL[4:0] bits. The results of input

In p u t C lo ck V a lid a tio n

P rio rity

In p u t co n fig u ra tio n

N o

IN n _ S E L _ P R IO R IT Y [3 :0 ]

'0 0 0 0 '

In p u t C lo ck Q u a lity M o n ito rin g

(L O S , A ctiv ity, F re q u e n c y)

IN n = '1 '

IN n _ V A L ID = '0 '

Y e s

A ll q u a lifie d in p u t clo ck s a re a va ila b le fo r A u to m a tic s e le ctio n

Figure 11. Qualified Input Clocks for Automatic Selection

3.2.3.3.2.1 Input Clock Validation

For DPLL2, the following conditions must be satisfied for the input

clock to be valid; otherwise, it is invalid.

For all the input clocks, the input is declared valid depending on the

results of input clock quality monitoring (refer to Chapter 3.2.3.2). The

IN_NOISE_WINDOW bit should be set to ‘1’ if any of INn_FREQ[3:0] is

set for frequencies  8 kHz, by default it is set to ‘0’.

• No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);

• No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is

‘0’);

• LOS[3:0] are not set to disqualify the input clock

For DPLL1, the following conditions must be satisfied for the input

clock to be valid; otherwise, it is invalid.

The INn bit (6  n  1) indicates whether or not the clock is valid.

When the input clock changes from ‘valid’ to ‘invalid’, or from ‘invalid’ to

‘valid), the INn bit will be set. If the INn bit is ‘1’, an interrupt will be gen-

erated.

• No no-activity alarm (the INn_NO_ACTIVITY_ALARM bit is ‘0’);

• No frequency hard alarm (the INn_FREQ_HARD_ALARM bit is

‘0’);

• No phase lock alarm, i.e., the INn_PH_LOCK_ALARM bit is ‘0’;

• If the ULTR_FAST_SW bit is ‘1’, the DPLL selected input clock

misses less than (<) 2 consecutive clock cycles; if the ULTR_-

FAST_SW bit is ‘0’, this condition is ignored;

When the DPLL selected input clock has failed, i.e., the selected

input clock changes from ‘valid’ to ‘invalid’, the DPLL_MAIN_REF_-

FAILED bit will be set. If the DPLL_MAIN_REF_FAILED bit is ‘1’, an

interrupt will be generated.

• LOS[3:0] are not set to disqualify the input clock

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82P33714 Datasheet

3.2.3.3.2.2 Revertive and Non-Revertive Switching

3.2.3.3.3 Selected / Qualified Input Clocks Indication

For DPLL1, Revertive and Non-Revertive switchings are supported,

as selected by the REVERTIVE_MODE bit.

The selected input clock is indicated by the CURRENTLY_SELECT-

ED_INPUT[3:0] bits.

For DPLL2, only Revertive switching is supported.

When the device is configured in Automatic selection and Revertive

switching is enabled, the input clock indicated by the CURRENTLY_SE-

LECTED_INPUT[3:0] bits is the same as the one indicated by the HIGH-

EST_PRIORITY_VALIDATED[3:0] bits.

GR-1244 defines Revertive and Non-Revertive Reference switching.

In Non-Revertive switching, a switch to an alternate reference is main-

tained even after the original reference has recovered from the failure

that caused the switch. In Revertive switching, the clock switches back

to the original reference after that reference recovers from the failure,

independent of the condition of the alternate reference. In Non-Revertive

switching, input clock switch is minimized.

For proper operation COARSE_PH_LOS_LIMT_EN must be set to 0.

3.2.3.3.4 Input Clock Loss of Signal

There are 4 LOS input pins (LOS[3:0]) that can be used to disqualify

the input clock. If they are set high, then the associated input clock is

disqualified to be used as an input clock, and therefore the DPLLs will

not lock to that particular input clock.

In Revertive switching, the selected input clock is switched when

another qualified input clock with a higher priority than the current

selected input clock is available. Therefore, if REVERTIVE_MODE bit is

set to “1”, then the selected input clock is switched if any of the following

is satisfied:

The 4 LOS pins can be associated with any input clock by setting bits

LOS_EN in INn_LOS_SYNC_CNFG (1 < n < 6) register. By default, the

LOS pins are not associated with any input.

• the selected input clock is disqualified;

• another qualified input clock with a higher priority than the

selected input clock is available.

3.2.4

DPLL LOCKING PROCESS

The following events are always monitored for the DPLLs locking

process:

A qualified input clock with the highest priority is selected by revertive

switching. If more than one qualified input clock INn is available, then it

is important to set appropriate priorities to the input clocks, two input

clocks must not have the same priority.

• Fast Loss;

• Fine Phase Loss;

• Hard Limit Exceeding.

In Non-Revertive switching, the DPLL1 selected input clock is not

switched when another qualified input clock with a higher priority than

the current selected input clock becomes available. In this case, the

selected input clock is switched and a qualified input clock with the high-

est priority is selected only when the DPLL1 selected input clock is dis-

qualified. If more than one qualified input clock INn is available, then it is

important to set appropriate priorities to the input clocks, two input

clocks must not have the same priority.

For proper operation, COARSE_PH_LOS_LIMT_EN must be set to

0.

3.2.4.1

Fast Loss

A fast loss is triggered when the selected input clock misses 3 con-

secutive clock cycles. It is cleared once an active clock edge is detected.

For DPLL1 the occurrence of the fast loss will result in the DPLL to

unlock if the FAST_LOS_SW bit is ‘1’. For DPLL2, the occurrence of the

fast loss will result in the DPLL to unlock regardless of the

FAST_LOS_SW bit.

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82P33714 Datasheet

3.2.4.2

Fine Phase Loss

The phase lock alarm is indicated by the corresponding

INn_PH_LOCK_ALARM bit (6  n  1).

The DPLL compares the selected input clock with the feedback sig-

nal. If the phase-compared result exceeds the fine phase limit pro-

grammed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is

triggered. It is cleared once the phase-compared result is within the fine

phase limit.

The phase lock alarm can be cleared, as selected by the

PH_ALARM_TIMEOUT bit:

• It is cleared when a ‘1’ is written to the corresponding

INn_PH_LOCK_ALARM bit;

• It is cleared after the period (= TIME_OUT_VALUE[5:0] X MUL-

TI_FACTOR[1:0] in second) starting from the time the alarm is

raised.

For the greatest jitter and wander tolerance, set the

PH_LOS_FINE_LIMT[2:0] to the largest value.

The occurrence of the fine phase loss will result in DPLL to unlock if

the FINE_PH_LOS_LIMT_EN bit is ‘1’.

The selected input clock with a phase lock alarm is disqualified for

the DPLL1 to lock.

3.2.4.3

Hard Limit Exceeding

Note that phase lock alarm is not available for DPLL2.

Two limits are available for this monitoring. They are DPLL soft limit

and DPLL hard limit. When the frequency of the DPLL output with

respect to the system clock exceeds the DPLL soft / hard limit, a DPLL

soft / hard alarm will be raised; the alarm is cleared once the frequency

is within the corresponding limit. The occurrence of the DPLL soft alarm

does not affect the DPLL locking status. The DPLL soft alarm is indi-

cated by the corresponding DPLL_SOFT_FREQ_ALARM bit. The

occurrence of the DPLL hard alarm will result in the DPLL to unlock if the

FREQ_LIMT_PH_LOS bit is ‘1’.

3.2.5

APLL1 AND APLL2

APLL1 and APLL2 are provided for a better jitter and wander perfor-

mance of the device output clocks. The bandwidth for APLL1 and APLL2

is internally set to 22 kHz (typical).

The input of both APLLs can be derived from one of the DPLL1 out-

puts, as selected by the apll1_path_freq_cnfg[2:0] and apll2_path_fre-

q_cnfg[2:0] bits respectively as shown in Table 10. APLL2 is free-

running by default, after reset APLL2 should be set to be connected to

DPLL1 per Table 10.

The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits

and can be calculated as follows:

Table 10: APLL1/2 input selection

DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724

apll1/apll2_path_freq_cnfg[2:0]

APLL1/2 Input Selection

The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0]

bits and can be calculated as follows:

000

001

622.08 MHz from DPLL1

625 MHz from DPLL1

644.53125 MHz from DPLL1

Reserved

DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014

010

3.2.4.4

Locking Status

011~1111

The DPLL locking status depends on the locking monitoring results.

The DPLL is in locked state if none of the following events is triggered

during 2 seconds; otherwise, the DPLL is unlocked.

To following steps should be followed to set APLL1/APLL2 output to

Ethernet LAN PHY frequencies.

• Fast Loss (the FAST_LOS_SW bit is ‘1’);

To initialize the device, write into the following registers:

• Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);

• DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’).

1. Write 0x04F4F0 to bits apll1/apll2_divn_frac_cnfg[20:0] of

APLL1/APLL2 fractional feedback divider configuration register

to set the fractional part of feedback divider for APLL1/APLL2

If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the

FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is ‘0’, the

DPLL locking status will not be affected even if the corresponding event

is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2

seconds.

2. Write 0x0051 to bits apll1/apll2_divn_den_cnfg[15:0] of APLL1/

APLL2 divisor denominator configuration register to set the

denominator part of feedback divider for APLL1/APLL2

3. Write 0x0010 to bits apll1/apll2_divisor_num_cnfg[15:0] of

APLL1/APLL2 divisor numerator configuration register to set the

numerator part of feedback divider for APLL1/APLL2

The DPLL locking status is indicated by the corresponding

DPLL_LOCK bits and by the DPLL_LOCK pins.

3.2.4.5

Phase Lock Alarm

4. Write 0x21 to bits apll1/apll2_divisor_int_cnfg[5:0] of APLL1/

APLL2 divisor integer configuration register to set the integer part

of feedback divider for APLL1/APLL2

DPLL1 has a phase lock alarm that will be raised when the selected

input clock can not be locked in DPLL1 within a certain period. This

period can be calculated as follows:

5. Write 0x13356218 to bits apll1/apll2_fr_ratio_cnfg[28:0] of

APLL1/APLL2 feedback divider configuration register to set the

feedback divider for APLL1/APLL2

Period (sec.) = TIME_OUT_VALUE[5:0] X MULTI_FACTOR[1:0]

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August 21, 2018

82P33714 Datasheet

After the device has been initialized according to the steps above,

follow the following steps when setting APLL1/APLL2 path to 644.53125

MHz:

VC

• Write 1’b1 to dsm_cnfg_en bit to enable the preset programma-

ble feedback divider of APLL1/APLL2 configuration register

• Write the corresponding value in the apll1/apll2_path_fre-

q_cnfg[2:0] bits according to Table 10.

Rs

Cs

After the device has been initialized according to the steps 1 to 5

above, follow the following steps when setting APLL1/APLL2 path to

625MHz: or 622.08MHz

Cp

• Write 1’b0 to dsm_cnfg_en bit to disable the preset programma-

ble feedback divider of APLL1/APLL2 configuration register

• Write the corresponding value in the apll1/apll2_path_fre-

q_cnfg[2:0] bits according to Table 10.

Figure 12. APLL External Filter

3.2.5.1

EXTERNAL FILTER

It is recommended to use external filter component for better noise

suppression. The filter components are connected to VC1 for APLL1

and VC2 APLL2. Choosing the correct external components and having

a printed circuit board (PCB) layout is a key task for quality operation of

the APLLs external filter option. Figure 12 shows the APLL1 and APLL2

external filter components, and Table 11 shows the recommended val-

ues for Rs, Cs and Cp. The device has been characterized using these

parameters. The external loop filter components should be kept as close

as possible to the device. Loop filter traces should be kept short. Other

signal traces should be kept separated and not run underneath the

device, and loop filter components.

3.2.6

OUTPUT CLOCKS & FRAME SYNC SIGNALS

The device supports 10 output clocks and 2 frame sync output sig-

nals.

3.2.6.1

Output Clocks

OUT1 can be derived either from DPLL1 or APLL1 selected by out-

1_mux_cnfg[3:0].

OUT2 ~ OUT4 can be derived from APLL1.

OUT5 ~ OUT7 can be derived from APLL2.

Table 11: APLL1 and APLL2 filter components

OUT8 can be derived either from DPLL1 or APLL2 selected by out-

8_mux_cnfg[3:0].

VC Filter Pin

Rs ()

Cs (uF)

Cp (pF)

OUT1 to OUT8 have an output divider associated with each output.

The divider is composed by 2 cascaded dividers, the first divider can be

programmed by writing into OUTn_DIV1_CNFG[4:0], the second divider

can be programmed by writing into OUTn_DIV2_CNFG[26:0].

External component

220

1

470

Figure 13 shows the diagram for OUT1 and OUT8 output dividers

and relevant register bits.

OUT1_MUX_CNFG[3:0]

OUT8_MUX_CNFG[3:0]

APLL_PATH

Output Divider

DPLL1

DPLL2

OUT1

OUT8

Output Div1

Output Div2

APLL1/

APLL2

(OUT1_DIV1_CNFG[4:0]

(OUT8_DIV1_CNFG[4:0])

(OUT1_DIV2_CNFG[26:0]

(OUT8_DIV2_CNFG[26:0])

Figure 13. OUT1 and OUT8 output dividers

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82P33714 Datasheet

Figure 14 shows the diagram for OUT2 to OUT7 output dividers and

relevant register bits.

APLL_PATH

DPLL1

Output Dividers

2<n<4 (from APLL1)

5<n<7 (from APLL2)

Output Div1

Output Div2

(OUTn_DIV2_CNFG[26:0]

2<n<4 (from APLL1)

5<n<7 (from APLL2)

OUTn

APLL1

APLL2

(OUTn_DIV1_CNFG[4:0]

2<n<4 (from APLL1)

5<n<7 (from APLL2)

Phase 2

Phase 1

DPLL2

Figure 14. OUT2 to OUT7 output dividers

OUT9 and OUT10 are derived from DPLL2, there is an output divider

associated with it. A GUI (Time Commander) can be used to set the fol-

lowing bis in the respective register that are associated with the DPLL2

dividers.

DPLL2 is disabled by default, and if it is enabled, then the default fre-

quency for OUT9 and OUT10 is respectively 16.384 MHz and 2.048

MHz.

APLL1, APLL2, and the DPLLs can be configured from an external

EEPROM after reset. It can be used to set specific start up frequency

values as needed by the application.

• To set the feedback divider, program DPLL2_fb_div_cnfg[13:0]

bits of DPLL2 feedback divider register

• To set the fractional divider, program DPLL2_divn_-

frac_cnfg[23:0] of DPLL2 fractional divider register

• To set the denominator of the fractional divider, program

DPLL2_divn_den_cnfg[15:0] bits of DPLL2 fractional divider

denominator register

• To set the numerator of the fractional divider, program

DPLL2_divn_num_cnfg[15:0] bits of DPLL2 fractional divider

numerator register

3.2.6.2

Frame Sync Signals

Either an 8 kHz or a 2 kHz frame sync, or a 1PPS sync signal are

output on the FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS pins if

enabled by the 8K_1PPS_EN and 2K_1PPS EN bits respectively. They

are CMOS outputs.

The output sync frequencies are independent of the input sync fre-

quency. The output FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS fre-

quencies are selected through the DPLL1_fr_mfr_sync_cnfg registers.

• To set the integer divider, program DPLL2_int_cnfg[7:0]bits of

DPLL2 integer divider register

Any supported clock frequency at the clock input can be associated

with the sync signals.

OUT1 to OUT10 output clocks can be inverted by setting OUTn_IN-

VERT bit (0: output not inverted, 1: output inverted) in OUTn_MUX-

_CNFG register for (1 < n < 8), and in OUT9_CNFG and OUT10_CNFG

registers for OUT9 and OUT10 respectively.

The frame sync output signals are derived from the DPLL1 and

DPLL2 output and are aligned with the output clock. They are synchro-

nized to the frame sync input signal. In DCO control modes (section

3.2.2.1.6), the output FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS

must not be used, a 1PPS output sync signal can be generated in any of

the output clocks connected to the DCO being used.

The output clocks can be squelched by setting OUT-

n_SQUELCH[1:0] bits (0x: no squelch, 10: squelch to '0', 11: squelch to

'1') in OUTn_MUX_CNFG register for (1 < n < 8), and in OUT9_CNFG

and OUT10_CNFG registers for OUT1 to OUT8, and OUT9 and OUT10

respectively.

The frame sync output signals are derived from the DPLL1 output

and are aligned with the output clock. They are synchronized to the

frame sync input signal.

OUT1 to OUT8 output clocks can be individually powered down by

setting OUTn_PDN bit to '1' in OUTn_MUX_CNFG register for (1 < n <

8)

The frame/sync output signals align to the first edge of the associ-

ated reference clock that occurs after the edge of the frame/sync input

signal. The frequency of the associated reference clock must be lower or

equal to the frequencies of the output clocks that requires to be aligned

with the frame/sync pulse signal.

82P33714 provides a variety of output frequencies from 1Hz to

650MHz.

APLL1 is always enabled and the default frequency for OUT1, OUT2,

and OUT3 is respectively 25 MHz, 125 MHz, and 156.25MHz. OUT4 is

squelched by default.

If the frame sync input signal with respect to the DPLL1 selected

input clock is above a limit set by the SYNC_MON_LIMT[2:0] bits, an

external sync alarm will be raised and the frame/sync input signal is dis-

abled to synchronize the frame/sync output signals. The external sync

alarm is cleared once the frame/sync input signal with respect to the

By default, OUT5 to OUT8 are squelched. Set the proper registers to

set desired frequency values for OUT5 to OUT8.

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August 21, 2018

82P33714 Datasheet

DPLL selected input clock is within the limit. If it is within the limit,

whether frame/sync input signal is enabled to synchronize the frame

sync output signal is determined by the AUTO_EXT_SYNC_EN bit and

the EXT_SYNC_EN bit.

When they are pulsed, the pulse width derived from DPLL1 is defined by

the period of OUT1. They are pulsed on the position of the falling or ris-

ing edge of the standard 50:50 duty cycle, as selected by the

2K_8K_PUL_POSITION bit of Frame Sync and Multiframe Sync Output

Configuration Register.

When the frame/sync input signal is enabled to synchronize the

frame/sync output signal, it is adjusted to align itself with the DPLL

selected input clock.

3.2.7

INPUT AND OUTPUT PHASE CONTROL

The device has several features to allow a tight control of the phase

on the input and output clocks.

By default, the falling edge of the frame/sync input signal is aligned

with the rising edge of the DPLL1 selected input clock. The rising edge

of frame/sync input signal can be set to be aligned with the rising edge

of the DPLL1 selected input clock by setting sync_edge bit to “1” in

DPLL1_sync_edge_cnfg register.

3.2.7.1

DPLL1 Phase offset control

The phase offset of the DPLL1 selected input clock with respect to

the DPLL1 output can be adjusted. If the device is configured as the

active PLL in a redundancy system, then the PH_OFFSET_EN bit deter-

mines whether the input-to-output phase offset is enabled. If the device

is configured as the inactive PLL in a redundancy system, then the

input-to-output phase offset is always enabled. If enabled, the input-to-

output phase offset can be adjusted by setting the PH_OFF-

SET_CNFG[28:0] bits in DPLL1 phase offset configuration register. The

register value is a 2's complement phase offset with a resolution of

0.0745ps and a total range of [20us, - 20us].

The EX_SYNC_ALARM_MON bit indicates whether frame/sync

input signal is in external sync alarm status. The external sync alarm is

indicated by the EX_SYNC_ALARM bit. If the EX_SYNC_ALARM bit is

‘1’, the occurrence of the external sync alarm will trigger an interrupt.

The 8 kHz frame pulse, the 2 kHz frame pulse, and the 1PPS sync

signal can be inverted by setting the 8K_1PPS_INV and 2K_1PPS_INV

bits of Frame Sync and Multiframe Sync Output Configuration Register.

The 8 kHz and the 2 kHz frame sync outputs can be 50:50 duty cycle

or pulsed, as determined by the 8K_PUL and 2K_PUL bits respectively.

The input-to-output phase offset can be calculated as follows:

Phase Offset (ps) = PH_OFFSET[28:0] X 0.0745

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82P33714 Datasheet

3.2.7.2

Input Phase control

adjusted by a step size that is equal to the period of the input of clock of

the output Div1, the number set in the OUTn_PH1_CNFG register

should not be larger than the number set in OUTn_DIV1_CNFG register.

The OUTn_PH2_CNFG register is associated with output divider 2 as

shown in Figure 13 and Figure 14, the phase can be adjusted by a step

size that is equal to the period of the input of clock of the output Div2, the

number set in the OUTn_PH2_CNFG register should not be larger than

the number set in OUTn_DIV2_CNFG register.

All the inputs phase can be controlled individually. They can be pro-

grammed with a resolution of 0.61 ns and a range of [77.5 ns,-78.1ns] by

setting INn_PHASE_OFFSET_CNFG[7:0] bits (1 < n < 6) in the input

phase offset configuration register. The register value is a 2's comple-

ment phase offset, the default is zero. The programmed offset is auto-

matically applied to the DPLL1 when a particular input is selected. If the

manual DPLL1 phase offset control is used then the per-input phase off-

set is not applied.

There is a register that is associated with the fine phase adjustment,

the OUTn_FINE_CNFG (1 < n < 8). For the fine phase adjustment, the

output clocks must be output from the APLLs, The phase can be

adjusted by a step size that is equal to the 1/2 of the period of the VCO.

For Ethernet clocks the VCO frequency is 2.5GHz, for Ethernet LAN

PHY the VCO frequency is 2.578125 GHz, and for SONET/SDH clocks

the VCO frequency is 2.48832 GHz. OUT1 can be output from the

DPLLs, and in that case the fine phase adjustment is not available, it is

only available if the clocks are output from the APLLs.

3.2.7.3

Output Phase control

The output phase can be controlled individually for outputs OUT1 to

OUT8. There is the coarse phase control that allows the output phase to

be adjusted as low as 1.6ns. There is a fine phase adjustment that

allows the output phase to be adjusted as low as 187.27 ps. The total

o

range is +/-180 .

There are two registers associated with the coarse phase adjust-

ment, the OUTn_PH1_CNFG (1 < n < 8) and the OUTn_PH2_CNFG (1

< n < 8) registers. The OUTn_PH1_CNFG register is associated with

output divider 1 as shown in Figure 13 and Figure 14, the phase can be

The output phase adjustments are not available for OUT9 and

OUT10.

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82P33714 Datasheet

4

POWER SUPPLY FILTERING TECHNIQUES

To achieve optimum jitter performance, power supply filtering is

internal analog PLL, it also provides VDDD and VDDDO pins for the

core logic as well as I/O driver circuits.

required to minimize supply noise modulation of the output clocks. The

common sources of power supply noise are switch power supplies and

the high switching noise from the outputs to the internal PLL. The

82P33714 provides separate VDDA and VDDAO power pins for the

The suggested power decoupling scheme is shown in Figure 15.

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August 21, 2018

82P33714 Datasheet

VCC3V3

0.1uF

40, 42

VDDD

VSS

10uF

0.1uF

ePAD

One 0.1uF

per pin

VCC1V8

0.1uF

42, 53

VDDD_1P8

VSS

10uF

ePAD

One 0.1uF

per pin

VCC3V3

0.1uF

27, 29, 64, 66

VDDDO

VSS

10uF

0.1uF

ePAD

One 0.1uF

per pin

VCC3V3

0.1uF

2, 3, 4, 5, 1011, 12

VDDA

VSS

10uF

0.1uF

ePAD

One 0.1uF

per pin

20, 24, 69, 72

VCC3V3

0.1uF

VDDAO

VSSAO

10uF

0.1uF

19, 23, ePAD

One 0.1uF

per pin

Figure 15. 82P33714 Power Decoupling Scheme

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August 21, 2018

82P33714 Datasheet

5

MICROPROCESSOR INTERFACE

The microprocessor interface provides access to read and write the

5.1.1

I2C DEVICE ADDRESS

registers in the device. The microprocessor interface supports I2C.

The default value for the higher 4-bit address is 4’b1010, the 3-bit

address is set by pins I2C_AD2, I2C_AD1, and I2C_AD0.

5.1

I2C SLAVE MODE

5.1.2

I2C BUS TIMING

Figure 16 shows the definition of I2C bus timing.

SDA

t_f

t_{SU: DAT}

t_{HD: STA}

t_r

t_BUF

t_SP

t_LOW

t_r

SCL

t_{SU: STO}

t_{HD: STA}

t_{SU: STA}

t_{HD: DAT}

S

t_HIGH

P

S

Sr

Figure 16. Definition of I2C Bus Timing

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August 21, 2018

82P33714 Datasheet

(1)

Table 12: Timing Definition for Standard Mode and Fast Mode

Standard Mode

Fast Mode

Symbol

Parameter

Unit

Min

Max

Min

Max

SCL

Serial clock frequency

0

100

0

400

-

kHz

Hold time (repeated) START condition. After this period, the

first clock pulse is generated

t_{HD; STA}

4.0

-

0.5

s

t_LOW

t_HIGH

LOW period of the SCL clock

4.7

4.0

4.7

5.0

0⁽²⁾

250

-

1.3

0.6

-

0⁽²⁾

100⁽⁴⁾

-

s

HIGH period of the SCL clock

-

t_{SU; STA}

Set-up time for a repeated START condition

-

Data hold time: for CBUS compatible masters for I²C-bus

devices

-

3.45⁽³⁾

-

0.9⁽³⁾

-

t_{HD; DAT}

s

t_{SU; DAT}

Data set-up time

ns

s

pF

20 + 0.1Cb⁽⁵⁾

t_r

t_f

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

-

1000

300

-

300

-

t_{SU; STO}

t_BUF

C_b

4.0

4.7

-

0.6

1.3

-

Bus free time between a STOP and START condition

Capacitive load for each bus line

-

400

Noise margin at the LOW level for each connected device

(Including hysteresis)

V_nL

V_nH

t_sp

0.1VDD

0.2VDD

0

-

0.1VDD

0.2VDD

0

-

V

Noise margin at the HIGH level for each connected device

(Including hysteresis)

Pulse width of spikes which must be suppressed by the input

filter

50

ns

Note:

1. All values referred to V_IHminand V_ILmaxlevels (see Table 23)

2. A device must Internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_{IHmin o}f the SCL signal) to bridge the undefined region of the fall-

ing edge of SCL.

3. The maximum t_{HD; DAT h}as only to be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.

4. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement t_{SU; DAT}≥ 250 ns must then be met. This will automatically be

the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data

bit to the SDA line t_rmax+ t_{SU; DAT}= 1000 + 250 = 1250 ns (according to the Standard-mode I²C-bus specification) before the SCL line is released.

5. C_b= total capacitance of one bus line in pF. If mixed with Hs-mode device, faster fall-times according to Table 24 allowed.

n/a = not applicable

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August 21, 2018

82P33714 Datasheet

5.1.3

SUPPORTED TRANSACTIONS

The supported types of transactions are shown below.

Current Read

S

Dev Addr + R

A

Data 0

A

Data 1

A

Data n

Data 0

A

P

Sequential Read

S

Dev Addr + W

Offset Addr

A

S_r

Dev Addr + R

A

Data 1

A

Data n

A

P

Sequential Write

S

Dev Addr + W

Offset Addr

S = start

A

Data 0

A

Data 1

A

Data n

A

P

from master to slave

from slave to master

S_r= repeated start

A = acknowledge

A = not acknowledge

P = stop

Figure 17. I2C Slave Interface Supported Transactions

Table 13: Description of I2C Slave Interface Supported Transactions

Operation

Description

Reads a burst of data from an internal determined starting address, this starting address is equal to the last address accessed

during the last read or write operation, incremented by one. If the address exceeds the address space, it will start from 0 again.

Current Read

Sequential Read

Sequential Write

Reads a burst of data from a specified address space. The starting address of the space is specified as offset address.

Writes a burst of data to a specified address space, the starting address of the space is specified as offset address.

microprocessor by programming the registers in the device-address

space 101_0xxx. This mode uses the MPU_MODE1/I2CM_SCL and the

MPU_MODE0/I2CM_SDA pins as the serial clock and the serial data

respectively, it requires that both these pins be pulled high through resis-

tors (these resistor values are dependent on the bus capacitance and

I2C speed of the application). Access to the 82P33714 registers through

the microprocessor interface I2C serial port is not available until the

EEPROM reading process is completed.

The registers are divided up into pages of 128 bytes with each byte

having a separate address. Multi-byte registers need to be accessed in

multiple read/write cycles. Address 0x7F is reserved for the page index

pointer.

All register accesses are done as 8 bit I2C cycles. The 8-bit address

refers to the register offset within the active page. If access to a different

page is needed then a separate I2C write must be performed to the

page register (0x7F). This makes the new page active and then 8 bit

reads and writes can be performed anywhere within that page.

2

As an I C bus master, the 82P33714 will support the following:

•

8 kbit (1023 x 8) I2C EEPROM with device address 1010000 (for

the base block)

Sequential read (block read) of the entire memory-map for device,

from byte-address 0x000 to 0x39E

Note that accesses to multi-byte registers should not be interrupted

by accesses to other addresses, because that may cause the data to be

corrupted. The access of the multi-byte registers is different from that of

the single-byte registers. Take the DPLL1 priority table registers (00H

and 01H in page 2) as an example, the write operation for the multi-byte

registers follows a fixed sequence. The register (00H) is configured first

and the register (01H) is configured last. The two registers are config-

ured continuously and should not be interrupted by any operation. The

DPLL1 priority table configuration will take effect after all the two regis-

ters are configured. During read operation, the register (00H) is read first

and the register (01H) is read last. The priority table configuration regis-

ter reading should be continuous and not be interrupted by any opera-

tion.

•

7-bit device address mode

Validation of the EEPROM read data via CCITT-8 CRC check

against value stored in memory-map address 0x39E

Support for 100 kHz and 400 kHz operation with speed program-

mability. If bit 7 is set at memory-map address 0x001, the

82P33714 will shift from 100 kHz operation to 400 kHz operation.

2-byte word-addressing (1-byte word addressing is supported by

offsetting the memory-map upwards 1 address in the EEPROM)

Read will abort with an alarm (RD_EEPROM_ERR interrupt status

set) if any of the following conditions occur: Slave NACK, CRC fail-

ure, Slave Response time-out

•

5.2

I2C MASTER MODE

The 82P33714 has the capability to read from an external I2C

EEPROM upon exit from reset. This reduces the start-up load on the

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August 21, 2018

82P33714 Datasheet

As the 82P33714 I2C master bus is meant only to read from a single

EEPROM, it has the following restrictions:

After a successful EEPROM boot, the 82P33714 will stop toggling

the MPU_MODE1/ I2CM_SCL and MPU_MODE0/I2CM_SDA pins,

returning them to static high values, and the RD_EEPROM_DONE inter-

rupt status bit will be set. The I2C serial port will now respond to micro-

processor reads and writes to the appropriate I2C device address.

•

No support for Multi-master

No support for Slave clock stretching

No support for I2C Start Byte protocol

No support for EEPROM Chaining

No support for Writing to external I2C devices including the

EEPROM used for booting

5.2.2

EEPROM MEMORY MAP NOTES

The EEPROM memory-map is the same as the control and status

register (CSR) map with the following additions and constraints:

5.2.1

I2C BOOT-UP INITIALIZATION MODE

1. For EEPROMs supporting 2-byte word-address, the memory-map

addresses are the same as the EPPROM addresses; for EEPROMs

supporting 1-byte word-address, the memory-map addresses will by

mapped to the next address in the EEPROM, i.e. memory-map address

0x00 will be read from EEPROM address 0x01, and memory-map

address 0x39E will be read from EEPROM address 0x39F.

EEPROM mode is enabled via setting the MPU_MODE[1:0] pins

high (through two separate pull-up resistors). Once the RSTB input has

been asserted (low) and then de-asserted (high) and the device internal

calibration has been completed, the 82P33714 will perform a short block

read at 100 kHz to program the EEPROM read speed (100 kHz or 400

kHz). The 82P33714 will then perform a block read to program all the

device configuration registers, and check the CRC of the EEPROM

data. During the boot-up EEPROM-reading process, the 82P33714 will

not respond to microprocessor serial control port accesses. Once the

initialization process is completed, the contents of any of the device con-

figuration registers can be further altered by the microprocessor, if

desired.

2. Memory-map address 0x001, bit 7 is the EEPROM read speed (0

for 100 kps, 1 for 400 kbps)

3. Memory-map address 0x39E is the CRC-8 of the memory-map

from 0x000 to 0x39D (the standard CCITT CRC-8 with the data width

and result width being 8; the polynomial is (0, 1, 2, 8) or “0x07”). NB: all

memory-map addresses from 0x000 to 0x39d are included in the

sequential calculation of CRC, including those not used in the CSR - it is

recommend that data at unused addresses be set to 0x00.

The 82P33714 can work with EEPROMs supporting 2-byte word-

addresses or 1-byte word-addresses by using 2-byte word addressing

for both. This works in the usual manner for EEPROMs supporting 2-

byte word addresses, and gives an address-to-address match between

EEPROM and memory-map. For EEPROMs supporting only 1-byte

word addresses, the second address byte will cause an addition incre-

ment of the address counter, and the memory-map will be read at the

next highest EEPROM address,.i.e memory-map (CSR) address 0x00

will be read from EEPROM address 0x01, and memory map address

0x39E will be read from EEPROM address 0x39F.

4. Memory-map addresses 0x392 to 0x39D must be set to the default

values shown in the CSR documentation.

5. The device address at memory-map address 0x00f must match

the address set by the board.

6. Each memory-map address that is a multiple of 0x7F must contain

the pointer to the next page of the CSR i.e

0x07f 0x01

0x0ff 0x02

0x17f 0x03

0x1ff 0x04

0x27f 0x05

0x2ff 0x06

0x37f 0x07

If a NACK is received to any of the read cycles performed by the

82P33714 during the initialization process, or if the CRC does not match

the one stored in memory-map address 0x39E, the boot process will be

restarted. This restart can happen up to three times before an abort is

declared and the RD_EEPROM_ERR interrupt status bit is set. Also on

RD_EEPROM_ERR the MPU_MODE1/ I2CM_SCL and MPU_MODE0/

I2CM_SDA pins are both held low until the interrupt status bit is cleared

or the device is reset. The suggested method for dealing with RD_EE-

PROM_ERR is to externally set the MPU_MODE[1:0] pins to 00 and

then reset the 82P33714 so that it will boot into I2C serial port mode.

37

August 21, 2018

82P33714 Datasheet

ing edge of SCLK. When CLKE is asserted high, data on SDO will be

clocked out on the falling edge of SCLK.

5.3

SERIAL MODE

In a read operation, the active edge of SCLK is selected by CLKE.

When CLKE is asserted low, data on SDO will be clocked out on the ris-

In a write operation, data on SDI will be clocked in on the rising edge

of SCLK.

Figure 18. Serial Read Timing Diagram (CLKE Asserted Low)

Figure 19. Serial Read Timing Diagram (CLKE Asserted High)

38

August 21, 2018

82P33714 Datasheet

Table 14: Read Timing Characteristics in Serial Mode

Symbol

Parameter

One cycle time of the master clock

Delay of input pad

Min

Typ

12.86

5

Max

Unit

ns

T

t_in

t_out

t_su1

t_su2

t_d1

Delay of output pad

5

Valid SDI to valid SCLK setup time

Valid CS to valid SCLK setup time

Valid SCLK to valid data delay time

CS rising edge to SDO high impedance delay time

SCLK pulse width low

4

14

10

t_d2

t_pw1

t_pw2

t_h1

5T+10

SCLK pulse width high

5T+10

Valid SDI after valid SCLK hold time

Valid CS after valid SCLK hold time (CLKE = 0/1)

6

5

t_h2

Time between consecutive Read-Read or Read-Write accesses

(CS rising edge to CS falling edge)

t_TI

10

ns

Figure 20. Serial Write Timing Diagram

Table 15: Write Timing Characteristics in Serial Mode

Symbol

Parameter

Min

Typ

12.86

5

Max

Unit

ns

T

One cycle time of the master clock

Delay of input pad

t_in

t_out

t_su1

t_su2

t_pw1

t_pw2

t_h1

Delay of output pad

5

Valid SDI to valid SCLK setup time

Valid CS to valid SCLK setup time

SCLK pulse width low

4

14

5T+10

6

SCLK pulse width high

Valid SDI after valid SCLK hold time

Valid CS after valid SCLK hold time

t_h2

5

Time between consecutive Write-Write or Write-Read accesses

(CS rising edge to CS falling edge)

t_TI

10

ns

39

August 21, 2018

82P33714 Datasheet

5.4.1

PROTOCOL

5.4

UART MODE

Reads and writes are initiated by the micro-controller sending a com-

mand to the 82P33714. All commands start with a zero byte, followed by

a command byte, 2 address bytes, and a length byte, which specifies

the number of bytes to be written or read. Write commands then have a

number of data bytes as given by the length byte. Commands are

optionally acknowledged on completion.

When the 82P33714 comes out of reset with the MPU_MODE[1:0]

pins set to 'b10, or when the boot-up EEPROM sets the

mpu_sel_cnfg[1:0] bits to 'b10, the device will set its serial port mode to

support simple 2-pin UART (Universal Asynchronous Receiver / Trans-

mitter) communications. The UART_RX pin is used as the receive data,

(data into the device), and the UART_TX pin is used as the transmit

data, (data out of the device). The supported byte-protocol is 1 Start bit,

8 data bits, and 1 Stop bits, with no parity. Figure 21 shows the UART

data frame.

Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Zero byte

Command byte

High Address byte (always zero)

Low Address byte

Length byte

Byte 6 to 5+Length Write data bytes (if a write command)

Figure 21. UART Data Frame

The format of the command byte is given in Table 16.

The falling edge of the Start bit is used to synchronize the UART

receiver with the transmitter of the micro-controller; each bit is sampled

at the expected midpoint as determined by this falling edge and the pro-

grammed baud rate.

Table 16: UART Command byte Structure

Bit Number

Description

[7:6]

Not Used

The baud rate is programmed using the two control registers:

baud_rate_cnfg, and baud_limit_cnfg. These registers set up an M/N

divider from the 82P33714 system clock rate (77.76 MHz) down to the

desired sample-clock rate, which must be 16 times the desired baud

rate. The baud_freq_cnfg register is programmed with the M value, and

the baud_limit_cnfg register is programmed with the value (N - M).

These registers may be programmed by the boot-up EEPROM, or over

the serial UART link. The new values take effect as soon as the UART

goes idle, so it is recommended that all 4 bytes be written in one burst.

Command:

2'b00 = NOP (sends ACK if requested)

2'b01 = Read

[5:4]

2'b10 = Write

[3:2]

1

Not Used

Address Auto-Increment:

Set to 0 to enable address auto increment.

Set to 1 to disable address auto increment.

Send ACK Flag:

0

Set to 1 to send ACK byte at command completion.

Example Baud rates:

9600 baud (default)

•

Sample Clock Rate = 16 * 9600 = 153 600 Hz

Sample Clock Rate = 77.76 MHz * 4/2025 = 153 600 Hz

baud_freq_cnfg = 4 = x004

Note that bursts cannot exceed the boundary of one register page

(128 bytes), also the Address + Length should not reach the page regis-

ter at the top of the register page (address 127 / x3F).

baud_limit_cnfg = 2025 - 4 = 2021 = x07E5

When the micro-controller sends a read command, or requests an

acknowledge byte, the 82P33714 will transmit one of more bytes as fol-

lows:

115 200 baud

•

Sample Clock Rate = 16 * 115 200 = 1 843 200 Hz

Sample Clock Rate = 77.76 MHz * 16/675 = 1 843 200 Hz

baud_freq_cnfg = 16 = x010

Byte 1 to Length

Byte 'Length

Read Data bytes

baud_limit_cnfg = 675 - 16 = 659 = x293

'ACK byte (0x5A, if bit[0] of the Command byte

was set]

Reads and writes of the 82P33714 control and status registers are

performed through a multi-frame/byte binary protocol, which is more effi-

cient than a character-oriented (hyper-terminal) protocol. The UART will

auto-increment the internal address to support burst reads and writes for

even higher efficiency.

Although the UART command contains a two-byte address, the

82P33714 will only use the Low Address byte. The UART can be set to

expect a single byte address by clearing the uart_double_address bit in

the baud_freq_cnfg[11:8] register. The command protocol can then

leave out the High Address byte.

40

August 21, 2018

82P33714 Datasheet

6

JTAG

This device is compliant with the IEEE 1149.1 Boundary Scan stan-

dard except the following:

• The output boundary scan cells do not capture data from the

core and the device does not support EXTEST instruction;

The JTAG interface timing diagram is shown in Figure - 22.

t_TCK

TCK

t_S

t_H

TMS

TDI

t_D

TDO

Figure 22. JTAG Interface Timing Diagram

Table 17: JTAG Timing Characteristics

Symbol

Parameter

Min

100

25

Typ

Max

Unit

ns

t_TCK

t_S

TCK period

TMS / TDI to TCK setup time

TCK to TMS / TDI Hold Time

TCK to TDO delay time

ns

t_H

25

ns

t_D

50

ns

41

August 21, 2018

82P33714 Datasheet

7

THERMAL MANAGEMENT

The device operates over the industry temperature range -40°C ~

Table 18 has the thermal results based on JEDEC standard condi-

tions. It is industry practice and IDT practice to publish these results.

+85°C. To ensure the functionality and reliability of the device, the maxi-

mum junction temperature T should not exceed 125°C. In some

jmax

If the PCB design differs from the JEDEC standard conditions, then

the thermal results will be different.

applications, the device will consume more power and a thermal solution

should be provided to ensure the junction temperature T does not

j

7.2

THERMAL RELEASE PATH

exceed the T

.

jmax

In order to maximize both the removal of heat from the package,

electrical grounding from the package to the board can be done through

thermal vias to effectively conduct from the surface of the PCB to the

ground plane(s). The vias act as “heat pipes”. The number of vias (i.e.

“heat pipes”) are application specific and dependent upon the package

power dissipation as well as electrical conductivity requirements. Thus,

thermal and electrical analysis and/or testing are recommended to

determine the minimum number needed. It is recommended to use as

many vias connected to ground as possible. It is also recommended that

the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz cop-

per via barrel plating. These recommendations are to be used as a

guideline only.

7.1

JUNCTION TEMPERATURE

Junction temperature T is the temperature of package typically at the

j

geographical center of the chip where the device's electrical circuits are.

It can be calculated as follows:

Equation 1: T = T + P X 

JA

j

A

Where:



= Junction-to-Ambient Thermal Resistance of the Package

JA

T = Junction Temperature

j

T = Ambient Temperature

A

P = Device Power Consumption

In order to calculate junction temperature, an appropriate  must

JA

be used. The  is shown in Table 18:

JA

Table 18: Thermal Data

Typ Values (^oC/W)

Parameter

Symbol

CONDITIONS

PKG

Notes

_JC

_JB

Junction to Case

Junction to Base

11.2

0.42

_JA1

_JA2

_JA3

_JA4

Junction to Air, still air

20.75

17.05

15.66

14.96

Thermal Resistance

QFN/NLG72

JEDEC PCB (7x7 matrix)

Junction to Air, 1 m/s air flow

Junction to Air, 2 m/s air flow

Junction to Air, 3 m/s air flow

42

August 21, 2018

82P33714 Datasheet

8

ELECTRICAL SPECIFICATIONS

8.1

ABSOLUTE MAXIMUM RATING

Table 19: Absolute Maximum Rating

Symbol

Parameter

Min

Max

Unit

V

_DDA, V_DDAO,

Supply Voltage V_DDA, V_DDAO, V_DDDO,V_DDD

-0.5

3.6

V

V_DDDO,V_DDD

V_{DDD_1_8}

V_INCMOS

V_INDIFF

Supply Voltage V_{DDD_1_8}

Input Voltage (CMOS and Open drain pins)

Input Voltage (Differential pins)

Input Voltage (Analog pins)

-0.5

1.98

5.5

V

V_DDD+ 0.5

V

V_INAN

2.2

50

V

I_OUTCONT

I_OUTSURGE

T_A

Output Current (Continuous current)

Output Current (Surge current)

Ambient Operating Temperature Range

Storage Temperature

mA

°C

100

85

-40

-50

T_STOR

150

Note:

CDM Classification - Class III (JESD22 - C101)

HBM Classification - Class 2 (JS-001-2010)

8.2

RECOMMENDED OPERATION CONDITIONS

Table 20: Recommended Operation Conditions

Symbol

Parameter

Min

Typ

3.3

1.8

Max

Unit

Test Condition

V_DDA, V_DDAO

,

Power Supply (DC voltage)

3.135

3.465

V

V_DDDO,V_DDD

V_{DDD_1_8}

T_A

Power Supply (DC voltage) V_{DDD_1_8}

Ambient Temperature Range

Analog Supply Current

1.71

-40

1.89

85

V

°C

I_DDA

327.75

24.66

81.46

38.92

361.90

27.98

94.55

42.47

mA

I_DDD

Digital Supply Current (V_DDD)

I_{DDD_1_8}

I_DDDO

Digital Supply Current (V_{DDD_1_8}

Digital Output Supply Current

)

All outputs enabled

All outputs enabled,

unloaded

Analog Output Supply Current

152.13

205.33

1.94

170.93

229.45

2.28

mA

W

All outputs enabled,

4 LVPECL outputs

loaded with 150 ohms

to GND

I_DDAO

Analog Output Supply Current (loaded)

Total Power Dissipation

All outputs enabled,

excluding the loading

P_TOT

43

August 21, 2018

82P33714 Datasheet

8.3

I/O SPECIFICATIONS

8.3.1

CMOS INPUT / OUTPUT PORT

Table 21: CMOS Input Port Electrical Characteristics

Parameter

Description

Input Voltage High

Input Voltage Low

Input Current

Min

Typ

Max

Unit

V

Test Condition

V_IH

V_IL

I_IN

2

0.8

V

±10

A

Table 22: CMOS Input Port with Internal Pull-Up Resistor Electrical Characteristics

Parameter

Description

Input Voltage High

Input Voltage Low

Pull-Up Resistor

Input Current

Min

Typ

Max

0.8

Unit

V

Test Condition

V_IH

V_IL

P_U

I_IN

2

V

50

K

A

±150

Table 23: CMOS Input Port with Internal Pull-Down Resistor Electrical Characteristics

Parameter

Description

Input Voltage High

Input Voltage Low

Pull-Down Resistor

Input Current

Min

Typ

Max

0.8

Unit

Test Condition

V_IH

V_IL

P_D

I_IN

2

V

50

K

A

±150

Table 24: CMOS Output Port Electrical Characteristics

Application Pin

Parameter

Description

Output Voltage High

Output Voltage Low

Rise time

Min

Typ

Max

Unit

Test Condition

I_OH= -4 mA

I_OL= 4 mA

V_OH

V_OL

t_R

2.4

VDD

0.4

V

Output Clock

C

_LOAD= 15 pF

2.2

ns

V

t_F

C

Fall time

V_OH

V_OL

t_R

I_OH= -2 mA

I_OL= 2 mA

Output Voltage High

Output Voltage Low

Rise Time

2.4

0.4

20

V

Other Output

C_LOAD= 50 pF

7

ns

t_F

Fall Time

44

August 21, 2018

82P33714 Datasheet

8.3.2

LVPECL / LVDS INPUT / OUTPUT PORT

PECL Input Port

8.3.2.1

V_DD(+ 3.3 V)

130 Ω

50 Ω (transmission line)

IN_POS

82 Ω

1 PPS

GND

to

650 MHz

V_DD(+ 3.3 V)

130 Ω

50 Ω (transmission line)

IN_NEG

82 Ω

GND

Figure 23. Recommended PECL Input Port Line Termination

Table 25: LVPECL Input Port Electrical Characteristics

Parameter

V_IL

Description

Min

VDD - 2.5

VDD - 2.4

0.1

Typ

Max

VDD - 0.5

VDD - 0.4

1.4

Unit

V

Test Condition

Input Low Voltage, Differential Inputs

Input High Voltage, Differential Inputs

VDD - 1.5

VDD - 1.4

0.7

V_IH

V

V_ID

Input Differential Voltage

V

V_{IL_S}

V_{IH_S}

I_IH

Input Low Voltage, Single-ended Input

VSS

VDD - 1.95

VDD - 0.9

VDD - 1.5

VDD

V

Input High Voltage, Single-ended Input

Input High Current, Input Differential Voltage V_ID= 1.4 V

Input Low Current, Input Differential Voltage V_ID= 1.4 V

VDD - 1.3

V

10

A

I_IL

-10

Note:

1. Assuming a differential input voltage of at least 100 mV.

2. Unused differential input terminated to VDD-1.4 V.

45

August 21, 2018

82P33714 Datasheet

8.3.2.2

LVPECL Output Port

8.3.2.2.1 LVPECL Termination for 3.3 V

tionality. These outputs are designed to drive 50 transmission lines.

Matched impedance techniques should be used to maximize operating

frequency and minimize signal distortion. Figure 24 and Figure 25 show

two different layouts which are recommended only as guidelines. Other

suitable clock layouts may exist and it would be recommended that the

board designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

The clock layout topology shown below is a typical termination for

LVPECL outputs. The two different layouts mentioned are recom-

mended only as guidelines.

The differential outputs are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating resistors

(DC current path to ground) or current sources must be used for func-

3.3V

R3

125Ω

R4

125Ω

3.3V

Z_o= 50Ω

3.3V

+

_

Z_o= 50Ω

+

_

Input

LVPECL

Z_o= 50Ω

LVPECL

Input

R1

50Ω

R2

50Ω

Z_o= 50Ω

R1

84Ω

R2

84Ω

V_CC- 2V

1

RTT =

* Z_o

RTT

((V_OH+ V_OL) / (V_CC– 2)) – 2

Figure 24. 3.3V LVPECL Output Termination

Figure 25. 3.3V LVPECL Output Termination

46

August 21, 2018

82P33714 Datasheet

8.3.2.2.2 LVPECL Termination for 2.5 V

Figure 26 and Figure 27 show examples of termination for 2.5V

LVPECL driver. These terminations are equivalent to terminating 50 to

VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground

level. The R3 in Figure 27 can be eliminated and the termination is

shown in Figure 28.

Figure 27. 2.5V LVPECL Output Termination

Figure 26. 2.5V LVPECL Output Termination

Figure 28. 2.5V LVPECL Output Termination

Table 26: LVPECL Output Port Electrical Characteristics

Parameter

V_OH

Description

Min

_CCO– 1.3

_CCO– 2.0

0.6

Typ

Max

V_CCO– 0.7

V_CCO– 1.5

1.0

Unit

V

Test Condition

V

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

Peak-to-Peak Output Voltage Swing

Output Rise/Fall time

V_OL

V

V_SWING

V

t_RISE/t_FALL

80

400

ps

20% to 80%

NOTE 1: Outputs terminated with 50 to V_CCO– 2V

47

August 21, 2018

82P33714 Datasheet

8.3.3

LVDS INPUT / OUTPUT PORT

LVDS INPUT PORT

8.3.3.1

50 Ω (transmission line)

IN_POS

IN_NEG

1 PPS

to

100 Ω

650 MHz

50 Ω (transmission line)

Figure 29. Recommended LVDS Input Port Line Termination

Table 27: LVDS Input Port Electrical Characteristics

Parameter

V_CM

Description

Min

200

100

-100

Typ

1200

350

Max

2200

900

Unit

mV



Test Condition

Input Common-mode Voltage Range

Input Peak Differential Voltage

Input Differential Threshold

V_DIFF

V_IDTH

100

R_TERM

External Differential Termination Impedance

100

48

August 21, 2018

82P33714 Datasheet

8.3.3.2

LVDS Output Port

LVDS Driver Termination

source. The standard termination schematic as shown at the top part of

Figure 30 can be used with either type of output structure. The termina-

tion schematic shown at the bottom part of Figure 30, which can also be

used with both output types, is an optional termination with center tap

capacitance to help filter common mode noise. The capacitor value

should be approximately 50pF. If using a non-standard termination, it is

recommended to contact IDT and confirm if the output structure is cur-

rent source or voltage source type. In addition, since these outputs are

LVDS compatible, the input receiver’s amplitude and common-mode

input range should be verified for compatibility with the output.

For a general LVDS interface, the recommended value for the termi-

nation impedance (ZT) is between 90 and 132. The actual value

should be selected to match the differential impedance (Z0) of your

transmission line. A typical point-to-point LVDS design uses a 100 par-

allel resistor at the receiver and a 100 differential transmission-line

environment. In order to avoid any transmission-line reflection issues,

the components should be surface mounted and must be placed as

close to the receiver as possible. IDT offers a full line of LVDS compliant

devices with two types of output structures: current source and voltage

Figure 30. Recommended LVDS Output Port Line Termination

Table 28: LVDS Output Port Electrical Characteristics

Parameter

V_OD

Description

Min

Typ

Max

454

50

Unit

mV

V

Test Condition

Differential Output Voltage

V_ODMagnitude Change

247

V_OD

V_OS

Offset Voltage

1.125

90

1.375

50

V_OS

V_OSMagnitude Change

mV

ps

t_RISE/t_FALL

Output Rise/Fall time (see Figure 31)

400

20% to 80%

80%

t_R

V_OD

20%

t_F

Figure 31. Output Rise/Fall Time

49

August 21, 2018

82P33714 Datasheet

8.3.4

Table 29: Output Clock Duty Cycle

Clock Output Frequency Min

OUTPUT CLOCK DUTY CYCLE

Typ

Max

55

Unit

%

Test Condition

f

<570MHz

>570MHz

45

35

OUT

65

%

NOTE 1: Output Duty Cycle configured using APLL1 or APLL2.

First, R3 and R4 in parallel should equal the transmission line

impedance. For most 50 applications, R3 and R4 can be 100.

The values of the resistors can be increased to reduce the loading

for slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V_ILcannot be less

8.3.4.1 Single-Ended Input for Differential Input

Figure 32 shows how a differential input can be wired to accept

single ended levels. The reference voltage V_REF= V_CC/2 is gener-

ated by the bias resistors R1 and R2. The bypass capacitor (C1)

is used to help filter noise on the DC bias. This bias circuit should

be located as close to the input pin as possible. The ratio of R1

and R2 might need to be adjusted to position the V_REFin the

center of the input voltage swing. For example, if the input clock

swing is 2.5V and V_CC= 3.3V, R1 and R2 value should be

adjusted to set V_REFat 1.25V. The values below are for when both

the single ended swing and V_CCare at the same voltage. This

than -0.3V and V_IHcannot be more than V_CC+ 0.3V. Suggest

edge rate faster than 1V/ns. Though some of the recommended

components might not be used, the pads should be placed in the

layout. They can be utilized for debugging purposes. The data-

sheet specifications are characterized and guaranteed by using a

differential signal.

configuration requires that the sum of the output impedance of the

driver (Ro) and the series resistance (Rs) equals the transmission

line impedance. In addition, matched termination at the input will

attenuate the signal in half. This can be done in one of two ways.

Figure 32. Example of Single-Ended Signal to Drive Differential Input

Vth = VCC*[R2/(R1+R2)]

V

= 0.6 V ~ VCC

swing

For the example in Figure 32, R1 = R2, so Vth = VCC/2 =1.65 V

The suggested single-ended signal input:

DC offset (Swing Center) = Vth/2 +/- V

*10%

swing

V

= VCC

IHmax

ILmin

= 0 V

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August 21, 2018

82P33714 Datasheet

8.4

JITTER PERFORMANCE

Table 30: Gigabit Ethernet Output Clock Jitter Generation

(jitter measured on one differential output of APLL1/2 with one differential output enabled)

Output Frequency

RMS Jitter Typ (ps)

RMS Jitter Max (ps)

Test Filter

Notes

ITU-T G.8262

limit 0.5 UI p-p

(1 UI = 0.8 ns)

0.70

0.55

0.96

0.73

2.5 kHz - 5 MHz

12 kHz - 5 MHz

25 MHz

IEEE 802.3-2008

limit 0.24 UI p-p /

0.0174 UI RMS

(1 UI = 0.8 ns)

0.27

0.34

637 kHz - 5 MHz

ITU-T G.8262

limit 0.5 UI p-p

(1 UI = 0.8 ns)

0.71

0.56

1.00

0.75

2.5 kHz to 10 MHz

12 kHz - 20 MHz

125MHz

IEEE 802.3-2008

limit 0.24 UI p-p /

0.0174 UI RMS

(1 UI = 0.8 ns)

0.19

0.24

637 kHz - 10 MHz

0.55

0.52

0.23

0.74

1.18

0.31

12 kHz - 20 MHz

20 kHz - 40 MHz

1 MHz - 30 MHz

ITU-T G.8262

limit 0.5 UI p-p

(1 UI = 100.47 ps)

156.25MHz

IEEE 802.3-2008

limit 0.28 UI p-p /

0.0203 UI RMS

0.17

0.24

1.875 MHz - 20 MHz

(1 UI = 100.47 ps)

0.56

0.52

0.16

0.76

0.65

0.29

12 kHz - 20 MHz

20 kHz - 80 MHz

1 MHz - 30 MHz

ITU-T G.8262 limit 0.5 UI p-p

0.0203 UI RMS

(1 UI = 100.47 ps)

625MHz

IEEE 802.3-2008

limit 0.28 UI p-p /

0.0203 UI RMS

0.10

0.26

1.875 MHz - 20 MHz

(1 UI = 100.47 ps)

NOTE 1: DPLL locked to input clock

NOTE 2: For BER = 10–12, RMS jitter = p-p jitter/13.8 per IEEE 802.3-2008 and IEEE 802.3ae-2002 section 48B.3.1.3.1

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August 21, 2018

82P33714 Datasheet

Table 31: Gigabit Ethernet Output Clock Jitter Generation

(Jitter measured on one CMOS output of APLL1/2 with one CMOS output enabled)

Output Frequency

RMS Jitter Typ (ps)

RMS Jitter Max (ps)

Test Filter

Notes

ITU-T G.8262

limit 0.5 UI p-p

(1 UI = 0.8 ns)

0.71

0.54

0.95

0.70

2.5 kHz - 5 MHz

12 kHz - 5 MHz

25 MHz

IEEE 802.3-2008

limit 0.24 UI p-p /

0.0174 UI RMS

(1 UI = 0.8 ns)

0.23

0.29

637 kHz - 5 MHz

ITU-T G.8262

limit 0.5 UI p-p

(1 UI = 0.8 ns)

0.78

0.61

1.07

0.78

2.5 kHz to 10 MHz

12 kHz - 20 MHz

125MHz

IEEE 802.3-2008

limit 0.24 UI p-p /

0.0174 UI RMS

(1 UI = 0.8 ns)

0.20

0.25

637 kHz - 10 MHz

NOTE 1: DPLL locked to input clock

NOTE 2: For BER = 10–12, RMS jitter = p-p jitter/13.8 per IEEE 802.3-2008 and IEEE 802.3ae-2002 section 48B.3.1.3.1

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August 21, 2018

82P33714 Datasheet

Table 32: SONET/SDH Output Clock Jitter Generation

(jitter measured on one differential output of APLL1/2 with one differential output enabled

Output Frequency

RMS Jitter Typ (ps)

RMS Jitter Max (ps)

Test Filter

Notes

GR-253-CORE and ITU-T

G.813 Option 2

limit 0.1 UI p-p /

0.53

0.74

12 kHz to 1.3MHz

0.01 UI RMS

(STM-16: 1UI = 0.40 ns)

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-1: 1 UI = 6.43 ns)

0.62

0.92

0.90

0.32

0.41

0.85

1.26

1.27

0.43

0.53

12 kHz to 5MHz

500 Hz to 1.3 MHz

1 kHz to 5 MHz

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-4: 1 UI = 1.61 ns)

19.44 MHz

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-1: 1 UI = 6.43 ns)

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-4: 1 UI = 1.61 ns)

65 kHz to 1.3 MHz

250 kHz to 5 MHz

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-4: 1 UI = 1.61 ns)

GR-253-CORE and ITU-T

G.813 Option 2

0.57

1.02

12 kHz to 20 MHz

limit 0.1 UI p-p /

0.01 UI RMS

(STM-16: 1UI = 0.40 ns)

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-1: 1 UI = 6.43 ns)

0.94

0.87

0.27

0.22

1.31

1.24

0.36

0.29

500 Hz to 1.3 MHz

1 kHz to 5 MHz

77.76 MHz

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-4: 1 UI = 1.61 ns)

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-1: 1 UI = 6.43 ns)

65 kHz to 1.3 MHz

250 kHz to 5 MHz

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-4: 1 UI = 1.61 ns)

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August 21, 2018

82P33714 Datasheet

Table 32: SONET/SDH Output Clock Jitter Generation

(jitter measured on one differential output of APLL1/2 with one differential output enabled

Output Frequency

RMS Jitter Typ (ps)

RMS Jitter Max (ps)

Test Filter

Notes

GR-253-CORE and ITU-T

G.813 Option 2

limit 0.1 UI p-p /

0.56

0.77

12 kHz to 20 MHz

0.01 UI RMS

(STM-16: 1UI = 0.40 ns)

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-1: 1 UI = 6.43 ns)

0.96

0.88

0.68

0.28

0.21

0.20

1.33

1.26

0.97

0.37

0.28

0.27

500 Hz to 1.3 MHz

1 kHz to 5 MHz

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-4: 1 UI = 1.61 ns)

155.52 MHz

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-16: 1UI = 0.40 ns)

5 kHz to 20 MHz

65 kHz to 1.3 MHz

250 kHz to 5 MHz

1 MHz to 20 MHz

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-1: 1 UI = 6.43 ns)

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-4: 1 UI = 1.61 ns)

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-16: 1UI = 0.40 ns)

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August 21, 2018

82P33714 Datasheet

Table 32: SONET/SDH Output Clock Jitter Generation

(jitter measured on one differential output of APLL1/2 with one differential output enabled

Output Frequency

RMS Jitter Typ (ps)

RMS Jitter Max (ps)

Test Filter

Notes

GR-253-CORE and ITU-T

G.813 Option 2

limit 0.1 UI p-p /

0.58

0.83

12 kHz to 20 MHz

0.01 UI RMS

(STM-16: 1UI = 0.40 ns)

GR-253-CORE and ITU-T

G.813 Option 2

limit 0.3 UI p-p

(STM-64: 1 UI = 0.10 ns)

0.51

0.66

20 kHz to 80 MHz

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-64: 1 UI = 0.10 ns)

GR-253-CORE and ITU-T

G.813 Option 2

limit 0.1 UI p-p

(STM-64: 1 UI = 0.10 ns)

0.16

0.26

4 MHz to 80 MHz

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-64: 1 UI = 0.10 ns)

622.08 MHz

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-1: 1 UI = 6.43 ns)

1.05

0.97

0.73

0.29

0.20

0.14

1.52

1.44

1.06

0.39

0.28

0.27

500 Hz to 1.3 MHz

1 kHz to 5 MHz

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-4: 1 UI = 1.61 ns)

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-16: 1UI = 0.40 ns)

5 kHz to 20 MHz

65 kHz to 1.3 MHz

250 kHz to 5 MHz

1 MHz to 20 MHz

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-1: 1 UI = 6.43 ns)

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-4: 1 UI = 1.61 ns)

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-16: 1UI = 0.40 ns)

NOTE 1: DPLL locked to input clock

55

August 21, 2018

82P33714 Datasheet

Table 33: SONET/SDH Output Clock Jitter Generation

(jitter measured on one CMOS output of APLL1/2 with one CMOS output enabled)

Output Frequency

RMS Jitter Typ (ps)

RMS Jitter Max (ps)

Test Filter

Notes

GR-253-CORE and ITU-T

G.813 Option 2

limit 0.1 UI p-p /

0.50

0.71

12 kHz to 1.3MHz

0.01 UI RMS

(STM-16: 1UI = 0.40 ns)

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-1: 1 UI = 6.43 ns)

0.54

0.89

0.84

0.28

0.27

0.74

1.23

1.17

0.36

12 kHz to 5MHz

500 Hz to 1.3 MHz

1 kHz to 5 MHz

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-4: 1 UI = 1.61 ns)

19.44 MHz

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-1: 1 UI = 6.43 ns)

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-4: 1 UI = 1.61 ns)

65 kHz to 1.3 MHz

250 kHz to 5 MHz

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-4: 1 UI = 1.61 ns)

GR-253-CORE and ITU-T

G.813 Option 2

0.57

2.63

12 kHz to 20 MHz

limit 0.1 UI p-p

(STM-4: 1 UI = 1.61 ns)

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-1: 1 UI = 6.43 ns)

0.93

0.86

0.28

0.22

1.30

1.22

0.37

0.29

500 Hz to 1.3 MHz

1 kHz to 5 MHz

ITU-T G.813 Option 1

limit 0.5 UI p-p

(STM-4: 1 UI = 1.61 ns)

77.76 MHz

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-1: 1 UI = 6.43 ns)

65 kHz to 1.3 MHz

250 kHz to 5 MHz

ITU-T G.813 Option 1

limit 0.1 UI p-p

(STM-4: 1 UI = 1.61 ns)

NOTE 1: DPLL locked to input clock

56

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82P33714 Datasheet

Table 34: DPLL1/DPLL2 Output Clock Jitter Generation

(Jitter measured on one CMOS output of DPLL1/DPLL2 with all other outputs disabled)

Output Frequency

RMS Jitter Typ (ps)

RMS Jitter Max (ps)

Test Filter

Notes

10 MHz

100.11

100.63

619.64

543.45

100 Hz - 100 kHz

100 Hz - 40 kHz

N x 1.544 MHz

(Note 2)

ANSI T1.403

limit 0.07 UI p-p

(DS1: 1 UI = 647 ns)

16.06

99.42

10.66

101.67

25.62

39.94

449.83

26.44

8 kHz - 40 kHz

100 Hz - 100 kHz

18 kHz - 100 kHz

100 Hz - 800 kHz

10 kHz - 800 kHz

N x 2.048 MHz

(Note 3)

ITU-T G.823

limit 0.2 UI p-p

(E1: 1 UI = 488 ns)

202.75

39.06

ITU-T G.751

limit 0.05 UI p-p

34.368 MHz

(E3: 1 UI = 29.10 ns)

105.16

20.77

198.15

27.44

100 Hz - 400 kHz

30 kHz - 400 kHz

44.736 MHz

NOTE 1:DPLL1/2 locked to input clock

NOTE 2: Measured on 12.352 MHz output clock

NOTE 3: Measured on 16.384 MHz output clock

Table 35: DPLL3 Output Clock Jitter Generation

(Jitter measured on one CMOS output of DPLL3 with all other outputs disabled)

Output Frequency

RMS Jitter Typ (ps)

RMS Jitter Max (ps)

Test Filter

Notes

147.325

347.530

100 Hz - 100 kHz

N x 2.048 MHz

Note 2

ITU-T G.823

limit 0.2 UI p-p

(E1: 1 UI = 488 ns)

8.02

133.88

0.80

17.24

303.43

1.47

18 kHz - 100 kHz

100 Hz - 40 kHz

8 kHz - 40 kHz

N x 1.544 MHz

Note 3

ANSI T1.403

limit 0.07 UI p-p

(DS1: 1 UI = 647 ns)

NOTE 1:DPLL3 locked to input clock

NOTE 2: Measured on 12.288 MHz output clock

NOTE 3: Measured on 12.352 MHz output clock

57

August 21, 2018

82P33714 Datasheet

8.5

INPUT / OUTPUT CLOCK TIMING

The inputs and outputs are aligned ideally. But due to the circuit delays, there is delay between the inputs and outputs.

1PPS Input Clock

t₁

1PPS Output Clock

Figure 33. Input / output clock timing

Table 36: Input-to-Output Delay via APLL1/2

t₁Min (ns)

t₁Max (ns)

t₁Range (ns_pp)

Output

Any LVCMOS Input to any of OUT01, OUT02, OUT07

or OUT08

6

13

19

(±3 around mean)

Any LVPECL/LVDS Input to any of OUT03, OUT04,

OUT05 or OUT06

5

11.5

10

0

16.5

19

8

(±2.5 around mean)

9

Any Input to any APLL1/2 Output

Any Input to [M]FRSYNC Output

(±4.5 around mean)

8

(typical value is 2.5ns)

NOTE 1. The measurements in the above table takes into account any delays in the clock path from any input to any output; through DPLL2 and either APLL1 or

APLL2.

NOTE 2. The measurements in the above table are over operational temperature, varying power supply and repeated power on/off cycle.

NOTE 3. Measurements are taken using an ideal REF input and an ideal System clock to account for only internal delays in the device.

8.6

OUTPUT / OUTPUT CLOCK TIMING

1PPS Output Clock

t₁

Figure 34. Output / output clock timing

Table 37: APLL1/2 Output-to-Output Delay

t₁Min (ps)

t₁Max (ps)

Output

Output-to-Output, LVCMOS

(OUT01 to OUT02 or OUT07 to OUT08)

-110

110

Output-to-Output, LVPECL/LVDS

Input to a LVPECL/LVDS Output

(OUT03 to OUT04 or OUT05 to OUT06)

-85

85

58

August 21, 2018

82P33714 Datasheet

PACKAGE OUTLINE DRAWINGS

The package outline drawings are appended at the end of this document and are accessible from the link below. The package information is the most

current data available.

www.idt.com/document/psc/nlnlg72-package-outline-100-x-100-mm-body-epad-75-mm-sq-050-mm-pitch-qfn-sawn

ORDERING INFORMATION

Table 38: Ordering Information

Part/Order Number

Package

Temperature

-40^oto +85^oC

82P33714ANLG

72-Pin QFN

“G” after the two-letter package code denotes Pb-Free configuration, RoHS compliant.

59

August 21, 2018

82P33714 Datasheet

REVISION HISTORY

Revision Date

Description of Change

August 21, 2018

Added Figure 31

• Updated the Package Outline Drawings to append to the datasheet upon download from IDT.com; no mechanical changes.

• Revision history note: The April 20, 2015 release of the 82P33714 Datasheet contained a change to Input Clock Loss of

Signal that was not included in the document’s revision history. This was a documentation change only – there was no

change to the form, fit, or function of the 82P33714. The text was changed as follows:

From:

June 15, 2018

There are 4 LOS input pins (LOS[3:0]) that can be used to disqualify the input clock. If they are set to zero, then the associ-

ated input clock is disqualified to be used as an input clock, and therefore the DPLLs will not lock to that particular input

clock.

To:

There are 4 LOS input pins (LOS[3:0]) that can be used to disqualify the input clock. If they are set high, then the associated

input clock is disqualified to be used as an input clock, and therefore the DPLLs will not lock to that particular input clock.

Added MS/SL PIN USAGE

Updated Table 8

August 25, 2017

July 19, 2017

Updated the description of MS/SL in Table 1

Updated the Package Outline Drawings; however, no mechanical changes.

January 23, 2017

January 9, 2017

March 28, 2016

June 10, 2015

Pages 3-4, 60

Pages, 1, 4, 22, 23, 28-29, 60

Page 31, 52

Pages 9, 12, 13, 39, 40, 41

Page 51

May 13, 2015

April 20, 2015

Pages 58, 60, 62-67

Pages 37, 58 (Table 38), 61 (Table 40), 62 (Table 41)

Page 14

February 5, 2015

January 28, 2015

December 12, 2014

Page 51, Table 31

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.IDT.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,

without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same

way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability

of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not

convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-

sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property

60

August 21, 2018


型号：	82P33714
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Synchronous Equipment Timing Source
文件：	总63页 (文件大小：1183K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

82P33714 [IDT]

相关型号：

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