82V2081PPG8_技术文档

SINGLE CHANNEL T1/E1/J1 LONG HAUL/

SHORT HAUL LINE INTERFACE UNIT

IDT82V2081

FEATURES:

•

Single channel T1/E1/J1 long haul/short haul line interfaces

Supports HPS (Hitless Protection Switching) for 1+1 protection

without external relays

- Active edge of transmit clock (TCLK) and receive clock (RCLK)

- Active level of transmit data (TDATA) and receive data (RDATA)

- Receiver or transmitter power down

•

Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024

KHz

Programmable T1/E1/J1 switchability allowing one bill of ma-

terial for any line condition

Single 3.3 V power supply with 5 V tolerance on digital interfaces

Meets or exceeds specifications in

- ANSI T1.102, T1.403 and T1.408

- ITU I.431, G.703,G.736, G.775 and G.823

- ETSI 300-166, 300-233 and TBR12/13

- AT&T Pub 62411

Software programmable or hardware selectable on:

- Wave-shapingtemplatesforshorthaulandlonghaulLBO(LineBuild

Out)

- Line terminating impedance (T1:100 Ω, J1:110 Ω, E1:75 Ω/120 Ω)

- Adjustment of arbitrary pulse shape

- High impedance setting for line drivers

- PRBS (Pseudo Random Bit Sequence) generation and detection

15

with 2 -1 PRBS polynomials for E1

- QRSS(QuasiRandomSequenceSignals)generationanddetection

•

20

with 2 -1 QRSS polynomials for T1/J1

- 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS or QRSS

error counter

- Analog loopback, Digital loopback, Remote loopback and Inband

loopback

Cable attenuation indication

Adaptive receive sensitivity

Shortcircuitprotectionandinternalprotectiondiodeforlinedriv-

ers

LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection

Supports serial control interface, Motorola and Intel Multiplexed

interfaces and hardware control mode

Package:

•

- JA (Jitter Attenuator) position (receive path or transmit path)

- Single rail/dual rail system interfaces

- B8ZS/HDB3/AMI line encoding/decoding

•

IDT82V2081: 44-pin TQFP

DESCRIPTION:

maintenance, a PRBS/QRSS generation/detection circuit is integrated in

the chip, and different types of loopbacks can be set according to the appli-

cations. Four different kinds of line terminating impedance, 75 Ω, 100 Ω,

110Ω and120Ω areselectable. Thechipalsoprovidesdrivershort-circuit

protectionandinternalprotectiondiode.Thechipcanbecontrolledbyeither

software or hardware.

TheIDT82V2081canbeconfiguredasasinglechannelT1,E1orJ1Line

Interface Unit. In receive path, an Adaptive Equalizer is integrated to

removethedistortionintroducedbythecableattenuation.TheIDT82V2081

also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and

detects and reports the LOS conditions. In transmit path, there is an AMI/

B8ZS/HDB3 encoder, Waveform Shaper and LBOs. There is one Jitter

Attenuator, which can be placed in either the receive path or the transmit

path.TheJitterAttenuatorcanalsobedisabled.TheIDT82V2081supports

both Single Rail and Dual Rail system interfaces. To facilitate the network

The IDT82V2081 can be used in LAN, WAN, Routers, Wireless Base

Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,

CSU/DSU equipment, etc.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

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FUNCTIONAL BLOCK DIAGRAM

LOS/AIS

Detector

LOS

Receiver

Internal

Termination

RCLK

RD/RDP

CV/RDN

Data and

Clock

Recovery

Adaptive

Equalizer

RTIP

B8ZS/

HDB3/AMI

Decoder

Data

Slicer

Jitter

Attenuator

RRING

PRBS Detector

IBLC Detector

Analog

Loopback

Remote

Loopback

Digital

Loopback

TCLK

TD/TDP

TDN

TTIP

B8ZS/

HDB3/AMI

Decoder

Transmitter

Internal

Termination

Jitter

Attenuator

Line

Driver

Waveform

Shaper/LBO

TRING

PRBS Generator

IBLC Generator

TAOS

Clock

Generator

Register

Files

Software Control Interface

Pin Control

VDDIO

VDDD

VDDA

VDDT

Figure-1 Block Diagram

2

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TABLE OF CONTENTS

1

2

3

IDT82V2081 PIN CONFIGURATIONS .......................................................................................... 8

PIN DESCRIPTION ....................................................................................................................... 9

FUNCTIONAL DESCRIPTION .................................................................................................... 15

3.1

3.2

3.3

CONTROL MODE SELECTION ....................................................................................... 15

T1/E1/J1 MODE SELECTION .......................................................................................... 15

TRANSMIT PATH ............................................................................................................. 15

3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 15

3.3.2 ENCODER............................................................................................................. 15

3.3.3 PULSE SHAPER .................................................................................................... 15

3.3.3.1 Preset Pulse Templates .......................................................................... 15

3.3.3.2 LBO (Line Build Out) ............................................................................... 16

3.3.3.3 User-Programmable Arbitrary Waveform ................................................ 16

3.3.4 TRANSMIT PATH LINE INTERFACE..................................................................... 20

3.3.5 TRANSMIT PATH POWER DOWN........................................................................ 20

3.4

RECEIVE PATH ............................................................................................................... 21

3.4.1 RECEIVE INTERNAL TERMINATION.................................................................... 21

3.4.2 LINE MONITOR...................................................................................................... 22

3.4.3 ADAPTIVE EQUALIZER......................................................................................... 22

3.4.4 RECEIVE SENSITIVITY ......................................................................................... 22

3.4.5 DATA SLICER ........................................................................................................ 22

3.4.6 CDR (Clock & Data Recovery)................................................................................ 22

3.4.7 DECODER.............................................................................................................. 22

3.4.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 23

3.4.9 RECEIVE PATH POWER DOWN........................................................................... 23

JITTER ATTENUATOR .................................................................................................... 23

3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 23

3.5.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 23

LOS AND AIS DETECTION ............................................................................................. 24

3.6.1 LOS DETECTION................................................................................................... 24

3.6.2 AIS DETECTION .................................................................................................... 25

TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 26

3.7.1 TRANSMIT ALL ONES........................................................................................... 26

3.7.2 TRANSMIT ALL ZEROS......................................................................................... 26

3.7.3 PRBS/QRSS GENERATION AND DETECTION.................................................... 26

3.5

3.6

3.7

3.8

LOOPBACK ...................................................................................................................... 26

3.8.1 ANALOG LOOPBACK ............................................................................................ 26

3.8.2 DIGITAL LOOPBACK ............................................................................................. 26

3.8.3 REMOTE LOOPBACK............................................................................................ 26

3.8.4 INBAND LOOPBACK.............................................................................................. 28

3.8.4.1 Transmit Activate/Deactivate Loopback Code......................................... 28

3.8.4.2 Receive Activate/Deactivate Loopback Code.......................................... 28

3.8.4.3 Automatic Remote Loopback .................................................................. 28

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3.9

ERROR DETECTION/COUNTING AND INSERTION ...................................................... 29

3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 29

3.9.2 ERROR DETECTION AND COUNTING ................................................................ 29

3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 30

3.10 LINE DRIVER FAILURE MONITORING ........................................................................... 30

3.11 MCLK AND TCLK ............................................................................................................. 31

3.11.1 MASTER CLOCK (MCLK) ...................................................................................... 31

3.11.2 TRANSMIT CLOCK (TCLK).................................................................................... 31

3.12 MICROCONTROLLER INTERFACES ............................................................................. 32

3.12.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 32

3.12.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 32

3.13 INTERRUPT HANDLING .................................................................................................. 33

3.14 5V TOLERANT I/O PINS .................................................................................................. 33

3.15 RESET OPERATION ........................................................................................................ 33

3.16 POWER SUPPLY ............................................................................................................. 33

4

PROGRAMMING INFORMATION .............................................................................................. 34

4.1

4.2

REGISTER LIST AND MAP ............................................................................................. 34

REGISTER DESCRIPTION .............................................................................................. 35

4.2.1 CONTROL REGISTERS......................................................................................... 35

4.2.2 TRANSMIT PATH CONTROL REGISTERS........................................................... 36

4.2.3 RECEIVE PATH CONTROL REGISTERS ............................................................. 38

4.2.4 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 40

4.2.5 INTERRUPT CONTROL REGISTERS................................................................... 43

4.2.6 LINE STATUS REGISTERS................................................................................... 46

4.2.7 INTERRUPT STATUS REGISTERS ...................................................................... 48

4.2.8 COUNTER REGISTERS ........................................................................................ 49

5

6

7

HARDWARE CONTROL PIN SUMMARY .................................................................................. 50

TEST SPECIFICATIONS ............................................................................................................ 52

MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 63

7.1

7.2

SERIAL INTERFACE TIMING .......................................................................................... 63

PARALLEL INTERFACE TIMING ..................................................................................... 64

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LIST OF TABLES

Table-1

Table-2

Table-3

Table-4

Table-5

Table-6

Table-7

Table-8

Pin Description................................................................................................................ 9

Transmit Waveform Value For E1 75 Ω........................................................................ 17

Transmit Waveform Value For E1 120 Ω...................................................................... 17

Transmit Waveform Value For T1 0~133 ft................................................................... 17

Transmit Waveform Value For T1 133~266 ft............................................................... 18

Transmit Waveform Value For T1 266~399 ft............................................................... 18

Transmit Waveform Value For T1 399~533 ft............................................................... 18

Transmit Waveform Value For T1 533~655 ft............................................................... 18

Transmit Waveform Value For J1 0~655 ft ................................................................... 19

Transmit Waveform Value For DS1 0 dB LBO.............................................................. 19

Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 19

Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 19

Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 20

Impedance Matching for Transmitter ............................................................................ 20

Impedance Matching for Receiver ................................................................................ 21

Criteria of Starting Speed Adjustment........................................................................... 23

LOS Declare and Clear Criteria for Short Haul Mode ................................................... 24

LOS Declare and Clear Criteria for Long Haul Mode.................................................... 25

AIS Condition ................................................................................................................ 25

Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 26

EXZ Definition ............................................................................................................... 29

Interrupt Event............................................................................................................... 33

Register List and Map ................................................................................................... 34

ID: Device Revision Register ........................................................................................ 35

RST: Reset Register ..................................................................................................... 35

GCF: Global Configuration Register ............................................................................. 35

TERM: Transmit and Receive Termination Configuration Register .............................. 35

JACF: Jitter Attenuation Configuration Register ........................................................... 36

TCF0: Transmitter Configuration Register 0 ................................................................. 36

TCF1: Transmitter Configuration Register 1 ................................................................. 37

TCF2: Transmitter Configuration Register 2 ................................................................. 37

TCF3: Transmitter Configuration Register 3 ................................................................. 38

TCF4: Transmitter Configuration Register 4 ................................................................. 38

RCF0: Receiver Configuration Register 0..................................................................... 38

RCF1: Receiver Configuration Register 1..................................................................... 39

RCF2: Receiver Configuration Register 2..................................................................... 40

MAINT0: Maintenance Function Control Register 0...................................................... 40

MAINT1: Maintenance Function Control Register 1...................................................... 41

MAINT2: Maintenance Function Control Register 2...................................................... 41

MAINT3: Maintenance Function Control Register 3...................................................... 41

MAINT4: Maintenance Function Control Register 4...................................................... 42

MAINT5: Maintenance Function Control Register 5...................................................... 42

MAINT6: Maintenance Function Control Register 6...................................................... 42

INTM0: Interrupt Mask Register 0................................................................................. 43

INTM1: Interrupt Masked Register 1............................................................................. 44

INTES: Interrupt Trigger Edge Select Register............................................................. 45

Table-9

Table-10

Table-11

Table-12

Table-13

Table-14

Table-15

Table-16

Table-17

Table-18

Table-19

Table-20

Table-21

Table-22

Table-23

Table-24

Table-25

Table-26

Table-27

Table-28

Table-29

Table-30

Table-31

Table-32

Table-33

Table-34

Table-35

Table-36

Table-37

Table-38

Table-39

Table-40

Table-41

Table-42

Table-43

Table-44

Table-45

Table-46

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Table-47

Table-48

Table-49

Table-50

Table-51

Table-52

Table-53

Table-54

Table-55

Table-56

Table-57

Table-58

Table-59

Table-60

Table-61

Table-62

Table-63

Table-64

Table-65

Table-66

Table-67

Table-68

Table-69

STAT0: Line Status Register 0 (real time status monitor)............................................. 46

STAT1: Line Status Register 1 (real time status monitor)............................................. 47

INTS0: Interrupt Status Register 0................................................................................ 48

INTS1: Interrupt Status Register 1................................................................................ 49

CNT0: Error Counter L-byte Register 0......................................................................... 49

CNT1: Error Counter H-byte Register 1........................................................................ 49

Hardware Control Pin Summary ................................................................................... 50

Absolute Maximum Rating ............................................................................................ 52

Recommended Operation Conditions........................................................................... 52

Power Consumption...................................................................................................... 53

DC Characteristics ........................................................................................................ 53

E1 Receiver Electrical Characteristics .......................................................................... 54

T1/J1 Receiver Electrical Characteristics...................................................................... 55

E1 Transmitter Electrical Characteristics ...................................................................... 56

T1/J1 Transmitter Electrical Characteristics.................................................................. 57

Transmitter and Receiver Timing Characteristics ......................................................... 58

Jitter Tolerance ............................................................................................................. 59

Jitter Attenuator Characteristics.................................................................................... 61

Serial Interface Timing Characteristics ......................................................................... 63

Multiplexed Motorola Read Timing Characteristics....................................................... 64

Multiplexed Motorola Write Timing Characteristics....................................................... 65

Multiplexed Intel Read Timing Characteristics.............................................................. 66

Multiplexed Intel Write Timing Characteristics .............................................................. 67

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LIST OF FIGURES

Figure-1

Figure-2

Figure-3

Figure-4

Figure-5

Figure-6

Figure-7

Figure-8

Block Diagram ................................................................................................................. 2

IDT82V2081 TQFP44 Package Pin Assignment ............................................................ 8

E1 Waveform Template Diagram .................................................................................. 15

E1 Pulse Template Test Circuit ..................................................................................... 16

DSX-1 Waveform Template .......................................................................................... 16

T1 Pulse Template Test Circuit ..................................................................................... 16

Receive Path Function Block Diagram .......................................................................... 21

Transmit/Receive Line Circuit ....................................................................................... 21

Monitoring Receive Line in Another Chip ...................................................................... 22

Monitor Transmit Line in Another Chip .......................................................................... 22

Jitter Attenuator ............................................................................................................. 23

LOS Declare and Clear ................................................................................................. 24

Analog Loopback .......................................................................................................... 27

Digital Loopback ............................................................................................................ 27

Remote Loopback ......................................................................................................... 27

Auto Report Mode ......................................................................................................... 29

Manual Report Mode ..................................................................................................... 30

TCLK Operation Flowchart ............................................................................................ 31

Serial Microcontroller Interface Function Timing ........................................................... 32

Transmit System Interface Timing ................................................................................ 59

Receive System Interface Timing ................................................................................. 59

E1 Jitter Tolerance Performance .................................................................................. 60

T1/J1 Jitter Tolerance Performance .............................................................................. 60

E1 Jitter Transfer Performance ..................................................................................... 62

T1/J1 Jitter Transfer Performance ................................................................................ 62

Serial Interface Write Timing ......................................................................................... 63

Serial Interface Read Timing with SCLKE=1 ................................................................ 63

Serial Interface Read Timing with SCLKE=0 ................................................................ 63

Multiplexed Motorola Read Timing ................................................................................ 64

Multiplexed Motorola Write Timing ................................................................................ 65

Multiplexed Intel Read Timing ....................................................................................... 66

Multiplexed Intel Write Timing ....................................................................................... 67

Figure-9

Figure-10

Figure-11

Figure-12

Figure-13

Figure-14

Figure-15

Figure-16

Figure-17

Figure-18

Figure-19

Figure-20

Figure-21

Figure-22

Figure-23

Figure-24

Figure-25

Figure-26

Figure-27

Figure-28

Figure-29

Figure-30

Figure-31

Figure-32

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1

IDT82V2081 PIN CONFIGURATIONS

22

21

20

19

18

17

16

15

14

13

12

RD / DS / SCLKE / MONT

IC

VDDT

TRING

TTIP

34

35

36

37

38

39

40

41

42

43

44

CS / RXTXM1

INT / RXTXM0

VDDIO

GNDIO

MODE1

MODE0

JA1

GNDT

GNDA

RRING

RTIP

IDT82V2081

JA0

VDDA

REF

THZ

IC

RST

Figure-2 IDT82V2081 TQFP44 Package Pin Assignment

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2

PIN DESCRIPTION

Table-1 Pin Description

Name

Type

Pin No.

Description

TTIP

TRING

Analog

output

37

36

TTIP/TRING: Transmit Bipolar Tip/Ring

These pins are the differential line driver outputs. They will be in high impedance state under the following conditions:

•

THZ pin is high;

THZ bit is set to 1;

Loss of MCLK;

Loss of TCLK (exceptions: Remote Loopback; transmit internal pattern by MCLK);

Transmit path power down;

After software reset; pin reset and power on.

RTIP

RRING

Analog

input

41

40

RTIP/RRING: Receive Bipolar Tip/Ring

These signals are the differential receiver inputs.

TD/TDP

TDN

I

2

3

TD: Transmit Data

When the device is in single rail mode, the NRZ data to be transmitted is input on this pin. Data on TD pin is sampled into the

device on the active edge of TCLK and is encoded by AMI, HDB3 or B8ZS line code rules before being transmitted. In this

mode, TDN should be connected to ground.

TDP/TDN: Positive/Negative Transmit Data

When the device is in dual rail mode, the NRZ data to be transmitted for positive/negative pulse is input on these pins. Data

on TDP/TDN pin is sampled into the device on the active edge of TCLK. The line code in dual rail mode is as follows:

TDP

TDN

Output Pulse

Space

0

1

0

1

0

1

Positive Pulse

Negative Pulse

Space

TCLK

I

1

TCLK: Transmit Clock input

This pin inputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data at TD/TDP or TDN is

sampled into the device on the active edge of TCLK. If TCLK is missing¹and the TCLK missing interrupt is not masked, an inter-

rupt will be generated.

RD/RDP

CV/RDN

O

5

6

RD: Receive Data output

In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI, HDB3 or B8ZS line code rules.

CV: Code Violation indication

In single rail mode, the BPV/CV code violation will be reported by driving the CV pin to high level for a full clock cycle. B8ZS/

HDB3 line code violation can be indicated if the B8ZS/HDB3 decoder is enabled. When AMI decoder is selected, bipolar vio-

lation will be indicated.

In hardware control mode, the EXZ, BPV/CV errors in received data stream are always monitored by the CV pin if single rail

mode is chosen.

RDP/RDN: Positive/Negative Receive Data output

In dual rail mode, this pin outputs the re-timed NRZ data when CDR is enabled, or directly outputs the raw RZ slicer data if CDR

is bypassed.

Active edge and level select:

Data on RDP/RDN or RD is clocked with either the rising or the falling edge of RCLK. The active polarity is also selectable.

RCLK

O

4

RCLK: Receive Clock output

This pin outputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS condition with AIS enabled

(bit AISE=1), RCLK is derived from MCLK. In clock recovery mode, this signal provides the clock recovered from the RTIP/

RRING signal. The receive data (RD in single rail mode or RDP and RDN in dual rail mode) is clocked out of the device on the

active edge of RCLK. If clock recovery is bypassed, RCLK is the exclusive OR (XOR) output of the dual rail slicer data RDP

and RDN. This signal can be used in applications with external clock recovery circuitry.

Notes:

1. TCLK missing: the state of TCLK continues to be high level or low level over 70 MCLK cycles.

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Table-1 Pin Description (Continued)

Name

MCLK

Type

I

Pin No.

9

Description

MCLK: Master Clock input

A built-in clock system that accepts selectable 2.048MHz reference for E1 operating mode and 1.544MHz reference for T1/J1

operating mode. This reference clock is used to generate several internal reference signals:

•

Timing reference for the integrated clock recovery unit.

Timing reference for the integrated digital jitter attenuator.

Timing reference for microcontroller interface.

Generation of RCLK signal during a loss of signal condition.

Reference clock to transmit All Ones, all zeros, PRBS/QRSS pattern as well as activate or deactivate Inband Loopback

code if MCLK is selected as the reference clock. Note that for ATAO and AIS, MCLK is always used as the reference

clock.

•

Reference clock during the Transmit All Ones (TAO) condition or sending PRBS/QRSS in hardware control mode.

The loss of MCLK will turn TTIP/TRING into high impedance status.

LOS

REF

O

7

LOS: Loss of Signal Output

This is an active high signal used to indicate the loss of received signal. When LOS pin becomes high, it indicates the loss of

received signal. The LOS pin will become low automatically when valid received signal is detected again. The criteria of loss

of signal are described in 3.6 LOS AND AIS DETECTION.

I

43

REF: reference resister

An external resistor (3KΩ, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit.

MODE1

MODE0

17

16

MODE[1:0]: operation mode of Control interface select

The level on this pin determines which control mode is used to control the device as follows:

MODE[1:0]

Control Interface mode

Hardware interface

00

01

10

11

Serial Microcontroller Interface

Parallel –Multiplexed -Motorola Interface

Parallel –Multiplexed -Intel Interface

•

The serial microcontroller Interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the

selection of the active edge of SCLK.

The parallel multiplexed microcontroller interface consists of CS, AD[7:0], DS/RD, R/W/WR, ALE/AS, ACK/RDY and

INT pins. (refer to 3.12 MICROCONTROLLER INTERFACES for details)

Hardware interface consists of PULS[3:0], THZ, RCLKE, LP[1:0], PATT[1:0], JA[1:0], MONT, TERM, EQ, RPD,

MODE[1:0] and RXTXM[1:0]

RCLKE

I

11

21

RCLKE: the active edge of RCLK select

In hardware control mode, this pin selects the active edge of RCLK

•

L= select the rising edge as the active edge of RCLK

H= select the falling edge as the active edge of RCLK

In software control mode, this pin should be connected to GNDIO.

CS

CS: Chip Select

In serial or parallel microcontroller interface mode, this is the active low enable signal. A low level on this pin enables serial or

parallel microcontroller interface.

RXTXM1

RXTXM[1:0]: Receive and transmit path operation mode select

In hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as AMI or HDB3/

B8ZS line coding:

•

00= single rail with HDB3/B8ZS coding

01= single rail with AMI coding

10= dual rail interface with CDR enabled

11= slicer mode (dual rail interface with CDR disabled)

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Table-1 Pin Description (Continued)

Name

Type

O

Pin No.

20

Description

INT

INT: Interrupt Request

In software control mode, this pin outputs the general interrupt request for all interrupt sources. These interrupt sources can be

masked individually via registers (INTM0, 14H) and (INTM1, 15H). The interrupt status is reported via the registers (INTS0,

19H) and (INTS1, 1AH).

Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by setting

INT_PIN[1:0] (GCF, 02H).

RXTXM0

SCLK

I

RXTXM0

See RXTXM1 above.

25

SCLK: Shift Clock

In serial microcontroller interface mode, this signal is the shift clock for the serial interface. Configuration data on SDI pin is sam-

pled on the rising edge of SCLK. Configuration and status data on SDO pin is clocked out of the device on the falling edge of

SCLK if SCLKE pin is high, or on the rising edge of SCLK if SCLKE pin is low.

ALE

AS

ALE: Address Latch Enable

In parallel microcontroller interface mode with multiplexed Intel interface, the address on AD[7:0] is sampled into the device on

the falling edge of ALE.

AS: Address Strobe

In parallel microcontroller interface mode with multiplexed Motorola interface, the address on AD[7:0] is latched into the device

on the falling edge of AS.

LP1

LP[1:0]: Loopback mode select

When the chip is configured by hardware, this pin is used to select loopback operation modes (Inband Loopback is not provided

in hardware control mode)

•

00= no loopback

01= analog loopback

10= digital loopback

11= remote loopback

SDI

I

24

SDI: Serial Data Input

In serial microcontroller interface mode, this signal is the input data to the serial interface. Configuration data at SDI pin is sam-

pled by the device on the rising edge of SCLK.

WR

WR: Write Strobe

In Intel parallel multiplexed interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. The data on

AD[7:0] is sampled into the device in a write operation.

R/W

R/W: Read/Write Select

In Motorola parallel multiplexed interface mode, this pin is low for write operation and high for read operation.

LP0

See LP1 above.

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SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-1 Pin Description (Continued)

Name

SDO

Type

O

Pin No.

23

Description

SDO: Serial Data Output

In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration or Status data at SDO

pin is clocked out of the device on the falling edge of SCLK if SCLKE pin is high, or on the rising edge of SCLK if SCLKE pin

is low.

ACK

ACK: Acknowledge Output

In Motorola parallel mode interface, the low level on this pin means:

•

The valid information is on the data bus during a read operation.

The write data has been accepted during a write cycle.

RDY

RDY: Ready signal output

In Intel parallel mode interface, the low level on this pin means a read or write operation is in progress; a high acknowledges

a read or write operation has been completed.

TERM

I

TERM: Internal or external termination select in hardware mode

This pin selects internal or external impedance matching for both receiver and transmitter.

•

0 = ternary interface with external impedance matching network

1 = ternary interface with internal impedance matching network

SCLKE

22

SCLKE: Serial Clock Edge Select

In serial microcontroller interface mode, this signal selects the active edge of SCLK for outputting SDO. The output data is valid

after some delay from the active clock edge. It can be sampled on the opposite edge of the clock. The active clock edge which

clocks the data out of the device is selected as shown below:

SCLKE

Low

SCLK

Rising edge is the active edge.

Falling edge is the active edge.

High

RD: Read Strobe

RD

DS

In Intel parallel multiplexed interface mode, the data is driven to AD[7:0] by the device during low level of RD in a read operation.

DS: Data Strobe

In Motorola parallel multiplexed interface mode, this signal is the data strobe of the parallel interface. In a write operation (R/

W = 0), the data on AD[7:0] is sampled into the device. In a read operation (R/W = 1), the data is driven to AD[7:0] by the device.

MONT: Receive Monitor gain select

In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:

0= 0dB

1= 26dB

MONT

AD7

I/O

33

AD7: Address/Data Bus bit7

In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller

interface.

In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.

PULS3

I

PULS[3:0]: these pins are used to select the following functions in hardware control mode:

•

T1/J1/E1 mode

Transmit pulse template

Internal termination impedance (75Ω/120Ω/100Ω/110Ω)

Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.

AD6

I/O

32

AD6: Address/Data Bus bit6

In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller

interface.

In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.

PULS2

I

See above.

12

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SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-1 Pin Description (Continued)

Name

AD5

Type

I/O

Pin No.

31

Description

AD5: Address/Data Bus bit5

In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller

interface.

In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.

PULS1

AD4

I

See above.

I/O

30

29

AD4: Address/Data Bus bit4

In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller

interface.

In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.

PULS0

AD3

I

See above.

I/O

AD3: Address/Data Bus bit3

In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller

interface.

In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.

EQ

I

EQ: Receive Equalizer on/off control in hardware control mode

•

0= short haul (10 dB)

1= long haul (36 dB for T1/J1, 43 dB for E1)

AD2

I/O

28

27

AD2: Address/Data Bus bit2

In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller

interface.

In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.

RPD

AD1

I

RPD: Receiver power down control in hardware control mode

•

0= normal operation

1= receiver power down

I/O

AD1: Address/Data Bus bit1

In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller

interface.

In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.

PATT1

AD0

I

PATT[1:0]: Transmit pattern select

In hardware control mode, this pin selects the transmit pattern

•

00 = normal

01= All Ones

10= PRBS

11= transmitter power down

I/O

26

15

AD0: Address/Data Bus bit0

In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller

interface.

In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.

PATT0

JA1

I

See above.

JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select (only used for hardware control mode)

•

00 = JA is disabled

01 = JA in receiver, broad bandwidth, FIFO=64 bits

10 = JA in receiver, narrow bandwidth, FIFO=128 bits

11 = JA in transmitter, narrow bandwidth, FIFO=128 bits

In software control mode, this pin should be connected to ground.

JA0

I

14

12

See above.

RST

RST: Hardware reset

The chip is forced to reset state if a low signal is input on this pin for more than 100ns.

13

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SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-1 Pin Description (Continued)

Name

THZ

Type

I

Pin No.

13

Description

THZ: Transmitter Driver High Impedance Enable

This signal enables or disables transmitter driver. A low level on this pin enables the driver while a high level on this pin places

driver in high impedance state. Note that the functionality of the internal circuits is not affected by this signal.

Power Supplies and Grounds

3.3 V I/O power supply

VDDIO

GNDIO

VDDT

GNDT

VDDA

GNDA

VDDD

GNDD

-

19

18

35

38

42

39

8

I/O ground

3.3 V power supply for transmitter driver

Analog ground for transmitter driver

3.3 V analog core power supply

Analog core ground

Digital core power supply

Digital core ground

10

Others

IC

-

34

44

IC: Internal connection

Internal Use. This pin should be left open when in normal operation.

IC: Internal connection

Internal Use. This pin should be connected to ground when in normal operation.

14

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SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

3.3.2 ENCODER

3

FUNCTIONAL DESCRIPTION

In Single Rail mode, when T1/J1 mode is selected, the Encoder can be

selected to be a B8ZS encoder or an AMI encoder by setting T_MD[0] bit

(TCF0, 05H).

3.1 CONTROL MODE SELECTION

The IDT82V2081 can be configured by software or by hardware. The

software control mode supports Serial Control Interface, Motorola Multi-

plexed Control Interface and Intel Multiplexed Control Interface. The Con-

trol mode is selected by MODE1 and MODE0 pins as follows:

InSingleRailmode,whenE1modeisselected,theEncodercanbecon-

figured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit

(TCF0, 05H).

In both T1/J1 mode and E1 mode, when Dual Rail mode is selected (bit

T_MD[1] is ‘1’), the Encoder is by-passed. In Dual Rail mode, a logic ‘1’ on

the TDP pin and a logic ‘0’ on the TDN pin results in a negative pulse on the

TTIP/TRING; a logic ‘0’ on TDP pin and a logic ‘1’ on TDN pin results in a

positive pulse on the TTIP/TRING. If both TDP and TDN are high or low,

the TTIP/TRING outputs a space (Refer to TD/TDP, TDN Pin Description).

Control Interface mode

00

01

10

11

Hardware interface

Serial Microcontroller Interface.

Parallel –Multiplexed -Motorola Interface

Parallel –Multiplexed -Intel Interface

In hardware control mode, the operation mode of receive and transmit

path can be selected by setting RXTXM1 and RXTXM0 pins. Refer to 5

HARDWARE CONTROL PIN SUMMARY for details.

•

The serial microcontroller Interface consists of CS, SCLK, SCLKE,

SDI, SDO and INT pins. SCLKE is used for the selection of active

edge of SCLK.

•

The parallel Multiplexed microcontroller Interface consists of CS,

AD[7:0], DS/RD, R/W/WR, ALE/AS, ACK/RDY and INT pins.

Hardware interface consists of PULS[3:0], THZ, RCLKE, LP[1:0],

PATT[1:0], JA[1:0], MONT, TERM, EQ, RPD, MODE[1:0] and

RXTXM[1:0]. Refer to 5 HARDWARE CONTROL PIN SUMMARY

for details about hardware control.

3.3.3 PULSE SHAPER

The IDT82V2081 provides three ways of manipulating the pulse shape

before sending it. The first is to use preset pulse templates for short haul

application, the second is to use LBO (Line Build Out) for long haul appli-

cation and the other way is to use user-programmable arbitrary waveform

template.

3.2 T1/E1/J1 MODE SELECTION

In software control mode, the pulse shape can be selected by setting

the related registers.

When the chip is configured by software, T1/E1/J1 mode is selected by

theT1E1bit(GCF, 02H). InE1application, theT1E1bit(GCF, 02H)should

be set to ‘0’. In T1/J1 application, the T1E1 bit should be set to ‘1’.

In hardware control mode, the pulse shape can be selected by setting

PULS[3:0] pins. Refer to 5 HARDWARE CONTROL PIN SUMMARY for

details.

When the chip is configured by hardware, T1/E1/J1 mode is selected

by PULS[3:0] pins. These pins also determine transmit pulse template and

internal termination impedance. Refer to 5 HARDWARE CONTROL PIN

SUMMARY for details.

3.3.3.1 Preset Pulse Templates

For E1 applications, the pulse shape is shown in Figure-3 according to

the G.703 and the measuring diagram is shown in Figure-4. In internal

impedance matching mode, if the cable impedance is 75 Ω, the PULS[3:0]

bits (TCF1, 06H) should be set to ‘0000’; if the cable impedance is 120 Ω,

the PULS[3:0] bits (TCF1, 06H) should be set to ‘0001’. In external imped-

ance matching mode, for both E1/75 Ω and E1/120 Ω cable impedance,

PULS[3:0] should be set to ‘0001’.

3.3 TRANSMIT PATH

The transmit path of IDT82V2081 consists of an Encoder, an optional

Jitter Attenuator, a Waveform Shaper, a set of LBOs, a Line Driver and a

Programmable Transmit Termination.

3.3.1 TRANSMIT PATH SYSTEM INTERFACE

The transmit path system interface consists of TCLK pin, TD/TDP pin

andTDNpin.InE1mode,TCLKisa2.048MHzclock.InT1/J1mode,TCLK

is a 1.544 MHz clock. If TCLK is missing for more than 70 MCLK cycles, an

interrupt will be generated if it is not masked.

1.20

1.00

0.80

0.60

Transmit data is sampled on the TD/TDP and TDN pins by the active

edgeofTCLK. Theactive edge ofTCLKcanbeselectedby theTCLK_SEL

bit (TCF0, 05H). And the active level of the data on TD/TDP and TDN can

be selected by the TD_INV bit (TCF0, 05H). In hardware control mode, the

falling edge of TCLK and the active high of transmit data are always used.

0.40

0.20

0.00

The transmit data from the system side can be provided in two different

ways: Single Rail and Dual Rail. In Single Rail mode, only TD pin is used

for transmitting data and the T_MD[1] bit (TCF0, 05H) should be set to ‘0’.

InDualRailMode,bothTDPpinandTDNpinareusedfortransmittingdata,

the T_MD[1] bit (TCF0, 05H) should be set to ‘1’.

-0.20

0.6

-0.6

-0.4

-0.2

0

0.2

0.4

T im e in U nit Intervals

Figure-3 E1 Waveform Template Diagram

15

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TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

3.3.3.3 User-Programmable Arbitrary Waveform

WhenthePULS[3:0]bitsaresetto‘11xx’, user-programmablearbitrary

waveform generator mode can be used. This allows the transmitter perfor-

mance to be tuned for a wide variety of line condition or special application.

TTIP

IDT82V2081

RLOAD

VOUT

Each pulse shape can extend up to 4 UIs (Unit Interval), addressed by

UI[1:0] bits (TCF3, 08H) and each UI is divided into 16 sub-phases,

addressedbytheSAMP[3:0]bits(TCF3,08H).Thepulseamplitudeofeach

phase is represented by a binary byte, within the range from +63 to -63,

stored in WDAT[6:0] bits (TCF4, 09H) in signed magnitude form. The most

positivenumber+63(D)representsthe positivemaximumamplitudeofthe

transmitpulsewhilethemostnegativenumber-63(D)representsthemax-

imum negative amplitude of the transmit pulse. Therefore, up to 64 bytes

are used.

TRING

Note: 1. For RLOAD = 75 Ω (nom), Vout (Peak)=2.37V (nom)

2. For R^LOAD=120 Ω (nom), Vout (Peak)=3.00V (nom)

Figure-4 E1 Pulse Template Test Circuit

For T1 applications, the pulse shape is shown in Figure-5 according to

the T1.102 and the measuring diagram is shown in Figure-6. This also

meets the requirement of G.703, 2001. The cable length is divided into five

grades,andtherearefivepulsetemplatesusedforeachofthecablelength.

The pulse template is selected by PULS[3:0] bits (TCF1, 06H).

Therearetwelvestandardtemplateswhicharestoredinanon-chipROM.

User can select one of them as reference and make some changes to get

the desired waveform.

User can change the wave shape and the amplitude to get the desired

pulse shape. In order to do this, firstly, users can choose a set of waveform

value from the following twelve tables, which is the most similar to the

desired pulse shape. Table-2, Table-3, Table-4, Table-5, Table-6, Table-7,

Table-8, Table-9, Table-10, Table-11, Table-12andTable-13listthesample

data and scaling data ofeach of thetwelvetemplates. Thenmodifythe cor-

responding sample data to get the desired transmit pulse shape.

1.2

1

0.8

0.6

0.4

0.2

0

Secondly, through the value of SCAL[5:0] bits increased or decreased

by 1, the pulse amplitude can be scaled up or down at the percentage ratio

againstthestandardpulseamplitudeifneeded. Fordifferentpulseshapes,

the value of SCAL[5:0] bits and the scaling percentage ratio are different.

The following twelve tables list these values.

-0.2

-0.4

-0.6

Do the followings step by step, the desired waveform can be pro-

grammed, based on the selected waveform template:

(1).Select the UI by UI[1:0] bits (TCF3, 08H)

0

250

500

750

1000

1250

Time (ns)

Figure-5 DSX-1 Waveform Template

(2).Specify the sample address in the selected UI by SAMP [3:0] bits

(TCF3, 08H)

(3).Write sample data to WDAT[6:0] bits (TCF4, 09H). It contains the

data to be stored in the RAM, addressed by the selected UI and the

corresponding sample address.

(4).Set the RW bit (TCF3, 08H) to ‘0’ to implement writing data to RAM,

or to ‘1’ to implement read data from RAM

TTIP

Cable

IDT82V2081

R^LOAD

VOUT

TRING

(5).Implement the Read from RAM/Write to RAM by setting the DONE

bit (TCF3, 08H)

Note: RLOAD = 100 Ω ± 5%

Repeat the above steps until all the sample data are written to or read

from the internal RAM.

Figure-6 T1 Pulse Template Test Circuit

(6).Write the scaling data to SCAL[5:0] bits (TCF2, 07H) to scale the

amplitude of the waveform based on the selected standard pulse

amplitude

For J1 applications, the PULS[3:0] (TCF1, 06H) should be set to ‘0111’.

Table-14 lists these values.

WhenmorethanoneUIisusedtocomposethepulsetemplate,theover-

lap of two consecutive pulses could make the pulse amplitude overflow

(exceed the maximum limitation) if the pulse amplitude is not set properly.

This overflow is captured by DAC_OV_ISbit (INTS1, 1AH), and, if enabled

by the DAC_OV_IM bit (INTM1, 15H), an interrupt will be generated.

3.3.3.2 LBO (Line Build Out)

Topreventthecross-talkatthefarend, theoutputofTTIP/TRINGcould

beattenuatedbeforetransmissionforlonghaulapplications.TheFCCPart

68 Regulations specifies four grades of attenuation with a step of 7.5 dB.

Three LBOs are used to implement the pulse attenuation. The PULS[3:0]

bits (TCF1, 06H) are used to select the attenuation grade. Both Table-14

and Table-15 list these values.

The following tables give all the sample data based on the preset pulse

templates and LBOs in detail forreference. For preset pulsetemplatesand

LBOs, scaling up/down against the pulse amplitude is not supported.

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INDUSTRIAL

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SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

1.Table-2 Transmit Waveform Value For E1 75 Ω

2.Table-3 Transmit Waveform Value For E1 120 Ω

Table-3 Transmit Waveform Value For E1 120 Ω

3. Table-4 Transmit Waveform Value For T1 0~133 ft

4.Table-5 Transmit Waveform Value For T1 133~266 ft

5.Table-6 Transmit Waveform Value For T1 266~399 ft

6.Table-7 Transmit Waveform Value For T1 399~533 ft

7.Table-8 Transmit Waveform Value For T1 533~655 ft

8.Table-9 Transmit Waveform Value For J1 0~655 ft

9.Table-10 Transmit Waveform Value For DS1 0 dB LBO

10.Table-11 Transmit Waveform Value For DS1 -7.5 dB LBO

11.Table-12 Transmit Waveform Value For DS1 -15.0 dB LBO

12.Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO

Sample

UI 1

UI 2

UI 3

UI 4

1

2

0000000

0001111

0111100

0000000

3

4

5

6

7

8

9

Table-2 Transmit Waveform Value For E1 75 Ω

10

11

12

13

14

15

16

Sample

UI 1

UI 2

UI 3

UI 4

1

2

0000000

0001100

0110000

0000000

3

4

5

6

SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0]

results in 3% scaling up/down against the pulse amplitude.

7

8

9

Table-4 Transmit Waveform Value For T1 0~133 ft

10

11

12

13

14

15

16

Sample

UI 1

UI 2

UI 3

UI 4

1

2

0010111

0100111

0100110

0100101

0100100

0100011

1001010

1001001

1000111

1000101

1000100

1000011

1000010

1000001

0000000

3

4

5

6

SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0]

results in 3% scaling up/down against the pulse amplitude.

7

8

9

10

11

12

13

14

15

16

SCAL[5:0] = 110110¹(default), One step change of this value of SCAL[5:0]

results in 2% scaling up/down against the pulse amplitude.

1. In T1 mode, when arbitrary pulse for short haul application is configured,

users should write ‘110110’ to SCAL[5:0] bits if no scaling is required.

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SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-5 Transmit Waveform Value For T1 133~266 ft

Table-7 Transmit Waveform Value For T1 399~533 ft

Sample

UI 1

UI 2

UI 3

UI 4

Sample

UI 1

UI 2

UI 3

UI 4

1

2

0011011

0101110

0101100

0101010

0101001

0101000

0100111

0100110

0100101

1010000

1001111

1001101

1001010

1001000

1000110

1000100

1000011

1000010

1000001

0000000

See Table-4

0000000

1

2

0100000

0111011

0110101

0101111

0101110

0101101

0101100

0101010

0101000

1011000

1010011

1001100

1001000

1000110

1000100

1000011

1000010

1000001

0000000

See Table-4

0000000

3

4

5

6

7

8

9

10

11

12

13

14

15

16

10

11

12

13

14

15

16

Table-6 Transmit Waveform Value For T1 266~399 ft

Table-8 Transmit Waveform Value For T1 533~655 ft

Sample

UI 1

UI 2

UI 3

UI 4

Sample

UI 1

UI 2

UI 3

UI 4

1

2

0011111

0110100

0101111

0101100

0101011

0101010

0101001

0101000

0100101

1010111

1010011

1010000

1001011

1001000

1000110

1000100

1000011

1000010

1000001

0000000

See Table-4

0000000

1

2

0100000

0111111

0111000

0110011

0101111

0101110

0101101

0101100

0101001

1011111

1011110

1010111

1001111

1001001

1000111

1000100

1000011

1000010

1000001

0000000

See Table-4

0000000

3

4

5

6

7

8

9

10

11

12

13

14

15

16

10

11

12

13

14

15

16

18

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TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-9 Transmit Waveform Value For J1 0~655 ft

Table-11 Transmit Waveform Value For DS1 -7.5 dB LBO

Sample

UI 1

UI 2

UI 3

UI 4

Sample

UI 1

UI 2

UI 3

UI 4

1

2

0010111

0100111

0100110

0100101

0100100

0100011

1001010

1001001

1000111

1000101

1000100

1000011

1000010

1000001

0000000

1

2

0000000

0000010

0001001

0010011

0011101

0100101

0101011

0110001

0110110

0111010

0111001

0110000

0101000

0100000

0011010

0010111

0010100

0010010

0010000

0001110

0001100

0001011

0001010

0001001

0001000

0000111

0000110

0000101

0000100

0000011

0000010

0000001

0000000

3

4

5

6

7

8

9

10

11

12

13

14

15

16

10

11

12

13

14

15

16

SCAL[5:0] = 110110 (default), One step change of this value of SCAL[5:0]

results in 2% scaling up/down against the pulse amplitude.

SCAL[5:0] = 010001 (default), One step change of this value of SCAL[5:0]

results in 6.25% scaling up/down against the pulse amplitude.

Table-10 Transmit Waveform Value For DS1 0 dB LBO

Table-12 Transmit Waveform Value For DS1 -15.0 dB LBO

Sample

UI 1

UI 2

UI 3

UI 4

Sample

UI 1

UI 2

UI 3

UI 4

1

2

0010111

0100111

0100110

0100101

0100100

0100011

1001010

1001001

1000111

1000101

1000100

1000011

1000010

1000001

0000000

1

2

0000000

0000001

0000100

0001000

0001110

0010100

0011011

0100010

0101010

0110000

0110101

0110111

0111000

0110111

0110101

0110011

0110000

0101101

0101010

0100111

0100100

0100001

0011110

0011100

0011010

0010111

0010101

0010100

0010010

0010000

0001111

0001101

0001100

0001011

0001010

0001001

0001000

0000111

0000110

0000101

0000100

0000011

0000010

0000001

0000000

3

4

5

6

7

8

9

10

11

12

13

14

15

16

10

11

12

13

14

15

16

SCAL[5:0] = 110110 (default), One step change of this Value results in 2%

scaling up/down against the pulse amplitude.

SCAL[5:0] = 001000 (default), One step change of the value of SCAL[5:0]

results in 12.5% scaling up/down against the pulse amplitude.

19

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TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

‘0’, the internal impedance matching circuit will be selected. In this case,

the T_TERM[1:0] bits (TERM, 03H) can be set to choose 75 Ω, 100Ω, 110

Ω or 120 Ω internal impedance of TTIP/TRING. If T_TERM[2] is set to ‘1’,

the internal impedance matching circuit will be disabled. In this case, the

external impedance matching circuit will be used to realize the impedance

matching. For T1/J1 mode, the external impedance matching circuit for the

transmitter isnot supported. Figure-8 shows the appropriate external com-

ponents to connect with the cable. Table-14 is the list of the recommended

impedance matching for transmitter.

Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO

Sample

UI 1

UI 2

UI 3

UI 4

1

2

0000000

0000001

0000011

0000111

0001011

0001111

0010101

0011001

0011100

0100000

0100011

0100111

0101010

0101100

0101110

0110000

0110001

0110010

0110001

0110000

0101110

0101100

0101001

0100111

0100100

0100010

0100000

0011110

0011100

0011010

0011000

0010111

0010101

0010100

0010011

0010001

0010000

0001111

0001110

0001101

0001100

0001010

0001001

0001000

0000111

0000110

0000101

0000100

0000011

0000010

0000001

3

4

5

6

In hardware control mode, TERM pin can be used to select impedance

matching for both receiver and transmitter. If TERM pin is low, external

impedance network will be used for impedance matching. If TERM pin is

high, internal impedance will be used for impedance matching and

PULS[3:0] pins will be set to select the specific internal impedance. Refer

to 5 HARDWARE CONTROL PIN SUMMARY for details.

7

8

9

10

11

12

13

14

15

16

TheTTIP/TRINGpinscanalsobeturnedintohighimpedancebysetting

the THZ bit (TCF1, 06H) to ‘1’. In this state, the internal transmit circuits are

still active.

In hardware control mode, TTIP/TRING can be turned into high imped-

ance by pulling THZ pin to high. Refer to 5 HARDWARE CONTROL PIN

SUMMARY for details.

SCAL[5:0] = 000100 (default), One step change of this value of SCAL[5:0]

results in 25% scaling up/down against the pulse amplitude.

Besides,inthefollowingcases,bothTTIP/TRINGpinswillalsobecome

high impedance:

•

Loss of MCLK;

3.3.4 TRANSMIT PATH LINE INTERFACE

Loss of TCLK (exceptions: Remote Loopback; Transmit internal

pattern by MCLK);

Transmit path power down;

The transmit line interface consists of TTIP pin and TRING pin. The

impedance matching can be realized by the internal impedance matching

circuit or the external impedance matching circuit. If T_TERM[2] is set to

•

After software reset; pin reset and power on.

Table-14 Impedance Matching for Transmitter

Cable Configuration

Internal Termination

External Termination

T_TERM[2:0]

PULS[3:0]

R_T

T_TERM[2:0]

PULS[3:0]

R_T

E1/75 Ω

000

001

010

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

0 Ω

1XX

0001

-

9.4 Ω

E1/120 Ω

T1/0~133 ft

T1/133~266 ft

T1/266~399 ft

T1/399~533 ft

T1/533~655 ft

J1/0~655 ft

-

011

010

0 dB LBO

-7.5 dB LBO

-15.0 dB LBO

-22.5 dB LBO

Note: The precision of the resistors should be better than ± 1%

3.3.5 TRANSMIT PATH POWER DOWN

In hardware control mode, the transmit path can be powered down by

pulling both PATT1 and PATT0 pins to high. Refer to 5 HARDWARE CON-

TROL PIN SUMMARY for details.

ThetransmitpathcanbepowereddownbysettingtheT_OFFbit(TCF0,

05H) to ‘1’. In this case, the TTIP/TRING pins are turned into high imped-

ance.

20

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

is set to ‘0’, the internal impedance matching circuit will be selected. In this

case, the R_TERM[1:0] bits (TERM, 03H) can be set to choose 75 Ω, 100

Ω, 110 Ω or 120 Ω internal impedance of RTIP/RRING. If R_TERM[2] is

set to ‘1’, the internal impedance matching circuit will be disabled. In this

case, the external impedance matching circuit will be used to realize the

impedance matching. Figure-8 shows the appropriate external compo-

nents to connect with the cable. Table-15 is the list of the recommended

impedance matching for receiver.

3.4 RECEIVE PATH

The receive path consists of Receive Internal Termination, Monitor

Gain,Amplitude/WaveShapeDetector,DigitalTuningController,Adaptive

Equalizer, Data Slicer, CDR (Clock & Data Recovery), Optional Jitter

Attenuator, Decoder and LOS/AIS Detector. Refer to Figure-7.

3.4.1 RECEIVE INTERNAL TERMINATION

The impedance matching can be realized by the internal impedance

matching circuit or the external impedance matching circuit. If R_TERM[2]

LOS/AIS

LOS

Detector

RCLK

Receive

Internal

termination

RTIP

Clock

Jitter

Adaptive

Equalizer

Data Slicer

Monitor Gain

Decoder

RDP

RDN

and Data

Recovery

Attenuator

RRING

Figure-7 Receive Path Function Block Diagram

Table-15 Impedance Matching for Receiver

Cable Configuration

Internal Termination

R_TERM[2:0]

External Termination

R_R

R_TERM[2:0]

R_R

E1/75 Ω

E1/120 Ω

T1

000

001

010

011

120 Ω

1XX

75 Ω

120 Ω

100 Ω

110 Ω

J1

VDDA

D8

1:1

·

•

RTIP

3.3 V

68µF¹

A

•

D7

VDDA

GNDA

VDDA

RX Line

R^R

0.1µF

D6

D5

•

·

•

B

RRING

TTIP

VDDT

D4

2:1

R^T

•

·

3.3 V

68µF¹

D3

VDDT

GNDT

TX Line

Cp

VDDT

D2

•·

TRING

RT

D1

Note: 1. Common decoupling capacitor

2. Cp 0-560 (pF)

3. D1 - D8, Motorola - MBR0540T1;

International Rectifier - 11DQ04 or 10BQ060

Figure-8 Transmit/Receive Line Circuit

21

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Inhardwarecontrolmode, TERM, PULS[3:0]pinscanbeusedtoselect

impedance matching for both receiver and transmitter. If TERM pin is low,

externalimpedancenetworkwillbeusedforimpedancematching.IfTERM

pin is high, internal impedance will be used for impedance matching and

PULS[3:0] pins can be set to select the specific internal impedance. Refer

to 5 HARDWARE CONTROL PIN SUMMARY for details.

3.4.3 ADAPTIVE EQUALIZER

The adaptive equalizer can remove most of the signal distortion due to

intersymbol interference caused by cable attenuation. It can be enabled or

disabled by setting EQ_ON bit to ‘1’ or ‘0’ (RCF1, 0BH).

Whentheadaptiveequalizerisoutofrange,EQ_Sbit(STAT0,17H)will

be set to ‘1’ to indicate the status of equalizer. If EQ_IES bit (INTES, 16H)

is set to ‘1’, any changes of EQ_S bit will generate an interrupt and EQ_IS

bit (INTS0, 19H) will be set to ‘1’ if it is not masked. If EQ_IES is set to ‘0’,

only the ‘0’ to ‘1’ transition of the EQ_S bit will generate an interrupt and

EQ_ISbitwillbesetto‘1’ifitisnot masked. TheEQ_ISbitwillberesetafter

being read.

3.4.2 LINE MONITOR

In both T1/J1 and E1 short haul applications, the non-intrusive monitor-

ingonchannelslocatedinotherchipscanbeperformedbytappingthemon-

itored channel through a high impedance bridging circuit. Refer to Figure-

9 and Figure-11.

The Amplitude/wave shape detector keeps on measuring the ampli-

tude/waveshapeoftheincomingsignalsduringanobservationperiod.This

observation period can be 32, 64, 128 or 256 symbol periods, as selected

by UPDW[1:0] bits (RCF2, 0CH). A shorter observation period allows

quicker responses to pulse amplitude variation while a longer observation

period can minimize the possible overshoots. The default observation

period is 128 symbol periods.

After a high resistance bridging circuit, the signal arriving at the RTIP/

RRING is dramatically attenuated. To compensate this attenuation, the

Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,

selected by MG[1:0] bits (RCF2, 0CH). For normal operation, the Monitor

Gain should be set to 0 dB.

In hardware control mode, MONT pin can be used to set the Monitor

Gain. When MONT pin is low, the Monitor Gain is 0 dB. When MONT pin

is high, the Monitor Gain is 26 dB. Refer to 5 HARDWARE CONTROL PIN

SUMMARY for details.

Based on the observed peak value for a period, the equalizer will be

adjusted to achievea normalized signal. LATT[4:0] bits(STAT1, 18H) indi-

cate the signal attenuation introduced by the cable in approximately 2 dB

per step.

DSX cross connect

point

3.4.4 RECEIVE SENSITIVITY

RTIP

For short haul application, the Receive Sensitivity for both E1 and T1/

J1 is -10 dB. For long haul application, the receive sensitivity is -43 dB for

E1 and -36 dB for T1/J1.

monitor

gain=0dB

RRING

R

normal receive mode

When the chip is configured by hardware, the short haul or long haul

operating mode can be selected by setting EQ pin. For short haul mode,

theReceiveSensitivityforbothE1andT1/J1is-10dB.Forlonghaulmode,

thereceivesensitivityis-43dBforE1and-36dBforT1/J1.Referto5HARD-

WARE CONTROL PIN SUMMARY for details.

RTIP

monitor gain

=22/26/32dB

RRING

3.4.5 DATA SLICER

monitor mode

The Data Slicer is used to generate a standard amplitude mark or a

space according to the amplitude of the input signals. The threshold can

be40%,50%,60%or70%,asselectedbytheSLICE[1:0]bits(RCF2,0CH).

TheoutputoftheDataSlicerisforwardedtotheCDR(Clock&DataRecov-

ery) unit or to the RDP/RDN pins directly if the CDR is disabled.

Figure-9 Monitoring Receive Line in Another Chip

DSX cross connect

point

TTIP

3.4.6 CDR (Clock & Data Recovery)

TheCDRisusedtorecovertheclockanddatafromthereceivedsignal.

The recovered clock tracks the jitter in the data output from the Data Slicer

and keeps the phase relationship between data and clock during the

absenceoftheincomingpulse.TheCDRcanalsobeby-passedintheDual

Railmode. WhenCDRisby-passed, the data fromtheDataSlicer isoutput

to the RDP/RDN pins directly.

TRING

R

normal transmit mode

RTIP

monitor gain

=22/26/32dB

3.4.7 DECODER

RRING

monitor mode

In T1/J1 applications, the R_MD[1:0] bits (RCF0, 0AH) is used to select

the AMI decoder or B8ZS decoder. In E1 applications, the R_MD[1:0] bits

(RCF0, 0AH) are used to select the AMI decoder or HDB3 decoder.

Figure-10 Monitor Transmit Line in Another Chip

Whenthechipisconfiguredbyhardware,theoperationmodeofreceive

and transmit path can be selected by setting RXTXM1 and RXTXM0 pins.

Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.

22

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

3.4.8 RECEIVE PATH SYSTEM INTERFACE

The receive path system interface consists of RCLK pin, RD/RDP pin

andRDNpin. InE1 mode, the RCLKoutputsarecovered2.048MHzclock.

In T1/J1 mode, the RCLK outputs a recovered 1.544 MHz clock. The

RD/RDP

De-jittered Data

RDN

FIFO

32/64/128

Jittered Data

received data is updated on the RD/RDP and RDN pins on the active edge

of RCLK. The active edge of RCLK can be selected by the RCLK_SEL bit

(RCF0, 0AH). And the active level of the data on RD/RDP and RDN can be

selected by the RD_INV bit (RCF0, 0AH).

W

R

Jittered Clock

De-jittered Clock

RCLK

In hardware control mode, only the active edge of RCLK can be

DPLL

selected.IfRCLKEissettohigh,thefallingedgewillbechosenastheactive

edge of RCLK. If RCLKE is set to low, the rising edge will be chosen as the

active edge of RCLK. The active level of the data on RD/RDP and RDN is

the same as that in software control mode.

MCLK

Thereceiveddatacanbeoutputtothesystemsideintwodifferentways:

SingleRailorDualRail,asselectedbyR_MDbit[1](RCF0,0AH). InSingle

Rail mode, only RD pin is used to output data and the RDN/CV pin is used

to report the received errors. In Dual Rail Mode, both RDP pin and RDN pin

are used for outputting data.

Figure-11 Jitter Attenuator

In E1 applications, the Corner Frequency of the DPLL can be 0.9 Hz or

6.8 Hz, as selected by the JABW bit (JACF, 04H). In T1/J1 applications,

the Corner Frequency of the DPLL can be 1.25 Hz or 5.00 Hz, as selected

bytheJABWbit(JACF,04H).ThelowertheCornerFrequencyis,thelonger

time is needed to achieve synchronization.

InthereceiveDualRailmode,theCDRunitcanbeby-passedbysetting

R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data

Slicer will be output to the RDP/RDN pins directly, and the RCLK outputs

the exclusive OR (XOR) of the RDP and RDN. This is called receiver slicer

mode. In this case, the transmit path is still operating in Dual Rail mode.

When the incoming data moves faster than the outgoing data, the FIFO

will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 1AH).

If the incoming data moves slower than the outgoing data, the FIFO will

underflow.ThisunderflowiscapturedbytheJAUD_IS bit(INTS1,1AH).For

some applications that are sensitive to data corruption, the JA limit mode

can be enabled by setting JA_LIMIT bit (JACF, 04H) to ‘1’. In the JA limit

mode, the speed of the outgoing data will be adjusted automatically when

theFIFOisclosetoitsfulloremptiness.Thecriteriaofstartingspeedadjust-

ment are shown in Table-16. The JA limit mode can reduce the possibility

of FIFO overflow and underflow, but the quality of jitter attenuation is dete-

riorated.

3.4.9 RECEIVE PATH POWER DOWN

The receive path can be powered down by setting R_OFF bit (RCF0,

0AH)to‘1’.Inthiscase,theRCLK,RD/RDP,RDNandLOSwillbelogiclow.

Inhardwarecontrolmode,receiverpowerdowncanbeselectedbypull-

ing RPD pin to high. Refer to 5 HARDWARE CONTROL PIN SUMMARY

for more details.

3.5 JITTER ATTENUATOR

There is one Jitter Attenuator in the IDT82V2081. The Jitter Attenuator

can be deployed in the transmit path or the receive path, and can also be

disabled. This is selected by the JACF[1:0] bits (JACF, 04H).

Table-16 Criteria of Starting Speed Adjustment

FIFO Depth

32 Bits

Criteria for Adjusting Data Outgoing Speed

2 bits close to its full or emptiness

3 bits close to its full or emptiness

4 bits close to its full or emptiness

In hardware control mode, Jitter Attenuator position, bandwidth and the

depth of FIFO can be selected by JA[1:0] pins. Refer to 5 HARDWARE

CONTROL PIN SUMMARY for details.

64 Bits

128 Bits

3.5.1 JITTER ATTENUATION FUNCTION DESCRIPTION

3.5.2 JITTER ATTENUATOR PERFORMANCE

The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in

Figure-11. The FIFO is used as a pool to buffer the jittered input data, then

the data is clocked out of the FIFO by a de-jittered clock. The depth of the

FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits

(JACF, 04H). In hardware control mode, the depth of FIFO can be selected

by JA[1:0] pins. Refer to 5 HARDWARE CONTROL PIN SUMMARY for

details. Consequently, the constant delay of the Jitter Attenuator will be 16

bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but at the cost

of increasing data latency time.

The performance of the Jitter Attenuator in the IDT82V2081 meets the

ITU-TI.431,G.703,G.736-739,G.823,G.824, ETSI300011,ETSITBR12/

13, AT&T TR62411 specifications. Details of the Jitter Attenuator perfor-

manceisshowninTable-63JitterToleranceandTable-64JitterAttenuator

Characteristics.

23

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

•

LOS detect level threshold

3.6 LOS AND AIS DETECTION

In short haul mode, the amplitude threshold Q is fixed on 800 mVpp,

while P=Q+200 mVpp (200 mVpp is the LOS level detect hysteresis).

3.6.1 LOS DETECTION

TheLossofSignalDetectormonitors theamplitudeoftheincomingsig-

nal level and pulse density of the received signal on RTIP and RRING.

Inlonghaulmode,thevalueofQcanbeselectedbyLOS[4:0]bit(RCF1,

0BH), while P=Q+4 dB (4 dB is the LOS level detect hysteresis). The

LOS[4:0] default value is 10101 (-46 dB).

•

LOS declare (LOS=1)

A LOS is detected when the incoming signal has “no transitions”, i.e.,

when the signal level is less than Q dB below nominal for N consecutive

pulse intervals. Here N is defined by LAC bit (MAINT0, 0DH). LOS will be

declared by pulling LOS pin to high (LOS=1) and LOS interrupt will be gen-

erated if it is not masked.

When the chip is configured by hardware, the LOS detect level is fixed

if the IDT82V2081 operates in long haul mode. It is -46dB (E1) and -38dB

(T1/J1).

•

Criteria for declare and clear of a LOS detect

The detection supports the ANSI T1.231 and I.431 for T1/J1 mode and

G.775 and ETSI 300233/I.431 for E1 mode. The criteria can be selected

by LAC bit (MAINT0, 0DH) and T1E1 bit (GCF, 02H).

•

LOS clear (LOS=0)

The LOS is cleared when the incoming signal has “transitions”, i.e.,

when the signal level is greater than P dB below nominal and has an aver-

age pulse density of at least 12.5% forM consecutive pulse intervals, start-

ingwiththereceiptofapulse. HereMisdefinedbyLACbit(MAINT0,0DH).

LOS status is cleared by pulling LOS pin to low.

Table-17 and Table-18 summarize LOS declare and clear criteria for

both short haul and long haul application.

•

All Ones output during LOS

Onthesystemside, theRDP/RDNwillreflecttheinputpulse“transition”

at the RTIP/RRING side and output recovered clock (but the quality of the

output clock can not be guaranteed when the input level is lower than the

maximum receive sensitivity) when AISE bit (MAINT0, 0DH) is 0; or output

All Ones as AIS when AISE bit (MAINT0, 0DH) is 1. In this case, RCLK out-

put is replaced by MCLK.

LOS=1

Onthelineside,theTTIP/TRINGwilloutputAllOnesasAISwhenATAO

bit (MAINT0, 0DH) is 1. The All Ones pattern uses MCLK as the reference

clock.

signal level>P

density=OK

signal level<Q

(observing windows= M)

(observing windows= N)

LOS indicator is always active for all kinds of loopback modes.

LOS=0

Figure-12 LOS Declare and Clear

Table-17 LOS Declare and Clear Criteria for Short Haul Mode

Control bit

LOS declare threshold

LOS clear threshold

T1E1

LAC

Level < 800 mVpp

N=175 bits

Level > 1 Vpp

M=128 bits

12.5% mark density

<100 consecutive zeroes

0=T1.231

1=I.431

1=T1/J1

Level < 800 mVpp

N=1544 bits

Level > 1 Vpp

M=128 bits

12.5% mark density

<100 consecutive zeroes

Level < 800 mVpp

N=32 bits

Level > 1 Vpp

M=32 bits

0=G.775

12.5% mark density

<16 consecutive zeroes

0=E1

Level < 800 mVpp

N=2048 bits

Level > 1 Vpp

M=32 bits

1=I.431/ETSI

12.5% mark density

<16 consecutive zeroes

24

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-18 LOS Declare and Clear Criteria for Long Haul Mode

Control bit

LAC

LOS declare threshold

LOS clear threshold

Note

T1E1

LOS[4:0]

00000

Q (dB)

-4

-6

…

Level < Q

N=175 bits

Level > Q+ 4dB

M=128 bits

12.5% mark density

<100 consecutive zeros

00001

…

T1.231 10001

0

-38

…

10101

10110-11111

-46

-48

00000

…

-4

Level < Q

N=1544 bits

Level > Q+ 4dB

M=128 bits

I.431 Level detect range is -18 to -30 dB

-

00110

-16

12.5% mark density

<100 consecutive zeros

1=T1/J1

I.431 00111

…

-18

…

01101

-30

1

01110

…

-32

…

-

10001

…

-38

…

10101

10110-11111

-46

-48

00000

…

00010

-4

…

-8

Level < Q

N=32 bits

Level > Q+ 4dB

M=32 bits

12.5% mark density

<16 consecutive zeros

G.775 Level detect range is -9 to -35 dB

-

G.775

-

00011

…

10000

-10

…

-36

0

10001

…

-38

…

10101(default)

10110-11111

-46

-48

0=E1

00000

-4

Level < Q

N=2048 bits

Level > Q+ 4dB

M=32 bits

I.431 Level detect range is -6 to -20 dB

-

12.5% mark density

<16 consecutive zeros

00001

…

-6

…

I.431/

1

ETSI 01000

-20

01001

…

-22

…

-

10101(default)

10110-11111

-46

-48

3.6.2 AIS DETECTION

T1.231. In E1 applications, the criteria for declaring/clearing AIS detection

comply with the ITU G.775 or the ETSI 300233, as selected by the LAC bit

(MAINT0, 0DH). Table-19 summarizes different criteria for AIS detection

Declaring/Clearing.

The Alarm Indication Signal can be detected by the IDT82V2081 when

the Clock & Data Recovery unit is enabled. The status of AIS detection is

reflected in the AIS_S bit (STAT0, 17H). In T1/J1 applications, the criteria

for declaring/clearing AIS detection are in compliance with the ANSI

Table-19 AIS Condition

ITU G.775 for E1

(LAC bit is set to ‘0’ by default)

ETSI 300233 for E1

(LAC bit is set to ‘1’)

ANSI T1.231 for T1/J1

Less than 3 zeros contained in each of two consecutive Less than 3 zeros contained in a 512-bit Less than 9 zeros contained in an 8192-bit stream

512-bit streams are received stream are received (a ones density of 99.9% over a period of 5.3 ms)

AIS

detected

3 or more zeros contained in each of two consecutive 3 or more zeros contained in a 512-bit 9 or more zeros contained in an 8192-bit stream

AIS

cleared

512-bit streams are received

stream are received

are received

25

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

PRBSdatacanbeinvertedthroughsettingthePRBS_INVbit(MAINT0,

0DH).

3.7 TRANSMIT AND DETECT INTERNAL PATTERNS

The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and

Activate/Deactivate Loopback Code) will be generated and detected by

IDT82V2081. TCLK is used as the reference clock by default. MCLK can

alsobe usedasthereferenceclockbysettingthePATT_CLK bit(MAINT0,

0DH) to ‘1’.

Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0,

19H). The PRBS_IES bit (INTES, 16H) can be used to determine whether

the ‘0’ to ‘1’ change of PRBS_S bit will be captured by the PRBS_IS bit or

any changes of PRBS_S bit will be captured by the PRBS_IS bit. When the

PRBS_ISbitis‘1’,aninterruptwillbegeneratedifthePRBS_IMbit(INTM0,

14H) is set to ‘1’.

If the PATT_CLK bit (MAINT0, 0DH) is set to ‘0’ and the PATT[1:0] bits

(MAINT0,0DH)aresetto‘00’,thetransmitpathwilloperateinnormalmode.

The received PRBS/QRSS logic errors can be counted in a 16-bit

counter if the ERR_SEL [1:0] bits (MAINT6, 13H) are set to ‘00’. Refer to

3.9 ERROR DETECTION/COUNTING AND INSERTIONfor the operation

of the error counter.

When the chip is configured by hardware, the transmit path will operate

in normal mode by setting PATT[1:0] pins to ‘00’. Refer to 5 HARDWARE

CONTROL PIN SUMMARY for details.

3.7.1 TRANSMIT ALL ONES

3.8 LOOPBACK

In transmit direction, the All Ones data can be inserted into the data

streamwhenthePATT[1:0]bits(MAINT0,0DH)aresetto‘01’.Thetransmit

datastream is output from TTIP/TRING. In this case, either TCLK orMCLK

can be used as the transmit clock, as selected by the PATT_CLK bit

(MAINT0, 0DH).

To facilitate testing and diagnosis, the IDT82V2081 provides four dif-

ferent loopback configurations: Analog Loopback, Digital Loopback,

Remote Loopback and Inband Loopback.

3.8.1 ANALOG LOOPBACK

Inhardwarecontrolmode,theAllOnesdatacanbeinsertedintothedata

stream in transmit direction by setting PATT[1:0] pins to ‘01’. Refer to 5

HARDWARE CONTROL PIN SUMMARY for details.

When the ALP bit (MAINT1, 0EH) is set to ‘1’, the chip is configured in

Analog Loopback mode. In thismode, thetransmit signals are looped back

to the Receiver Internal Termination in the receive path then output from

RCLK,RD,RDP/RDN.Atthesametime,thetransmitsignalsarestilloutput

to TTIP/TRING in transmit direction. Figure-13 shows the process.

3.7.2 TRANSMIT ALL ZEROS

If the PATT_CLK bit (MAINT0, 0DH) is set to ‘1’, the All Zeros will be

inserted into the transmit data stream when the PATT[1:0] bits (MAINT0,

0DH) are set to ‘00’.

In hardware control mode, Analog Loopback can be selected by setting

LP[1:0] pins to ‘01’.

3.8.2 DIGITAL LOOPBACK

3.7.3 PRBS/QRSS GENERATION AND DETECTION

When the DLP bit (MAINT1, 0EH) is set to ‘1’, the chip is configured in

Digital Loopback mode. In this mode, the transmit signals are looped back

to the jitter attenuator (if enabled) and decoder in receive path, then output

from RCLK, RD, RDP/RDN. At the same time, the transmit signals are still

output to TTIP/TRING in transmit direction. Figure-14 shows the process.

A PRBS/QRSS will be generated in the transmit direction and detected

20

in thereceive direction by IDT82V2081. TheQRSS is 2 -1for T1/J1 appli-

15

cations and the PRBS is 2 -1 for E1 applications, with maximum zero

restrictions according to the AT&T TR62411 and ITU-T O.151.

When the PATT[1:0] bits (MAINT0, 0DH) are set to ‘10’, the PRBS/

QRSS pattern will be inserted into the transmit data stream with the MSB

first. The PRBS/QRSS pattern will be transmitted directly or invertedly.

Both Analog Loopback mode and Digital Loopback mode allow the

sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will

overwrite the transmit signals. In this case, either TCLK or MCLK can be

used as the reference clock for internal patterns transmission.

Inhardwarecontrolmode,thePRBSdatawillbegeneratedinthetrans-

mitdirectionandinsertedintothetransmitdatastreambysettingPATT[1:0]

pinsto‘10’. Referto5HARDWARECONTROLPINSUMMARYfordetails.

In hardware control mode, Digital Loopback can be selected by setting

LP[1:0] pins to ‘10’.

The PRBS/QRSS in the received data stream will be monitored. If the

PRBS/QRSS has reached synchronization status, the PRBS_S bit

(STAT0, 17H)willbesetto‘1’, eveninthepresenceofalogicerrorrateless

3.8.3 REMOTE LOOPBACK

When the RLP bit (MAINT1, 0EH) is set to ‘1’, the chip is configured in

RemoteLoopbackmode.Inthismode,therecoveredclockanddataoutput

from Clock and Data Recovery on the receive path is looped back to the

jitterattenuator(ifenabled)andWaveformShaperintransmitpath. Figure-

15 shows the process.

-1

than or equal to 10 . The criteria for setting/clearing the PRBS_S bit are

shown in Table-20.

Table-20 Criteria for Setting/Clearing the PRBS_S Bit

Inhardwarecontrolmode,RemoteLoopbackcanbeselectedbysetting

LP[1:0] pins to ‘11’.

6 or less than 6 bit errors detected in a 64 bits hopping window.

PRBS/QRSS

Detection

More than 6 bit errors detected in a 64 bits hopping window.

PRBS/QRSS

Missing

26

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SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

LOS/AIS

LOS

Detection

Receiver

Internal

Termination

B8ZS/

HDB3/AMI

Decoder

Clock and

Data

Recovery

RCLK

RD/RDP

CV/RDN

RTIP

Jitter

Attenuator

Data

Slicer

Adaptive

Equalizer

RRING

Analog

Loopback

B8ZS/

HDB3/AMI

Encoder

Transmitter

Internal

Termination

TTIP

TCLK

TD/TDP

TDN

Line

Driver

Jitter

Attenuator

Waveform

Shaper/LBO

TRING

Figure-13 Analog Loopback

LOS/AIS

Detection

LOS

Receiver

Internal

Termination

B8ZS/

HDB3/AMI

Decoder

Clock and

Data

RCLK

RD/RDP

CV/RDN

RTIP

Jitter

Attenuator

Adaptive

Equalizer

Data

Slicer

RRING

Recovery

Digital

Loopback

B8ZS/

HDB3/AMI

Encoder

TTIP

Transmitter

Internal

Termination

TCLK

TD/TDP

TDN

Jitter

Attenuator

Waveform

Shaper/LBO

Line

Driver

TRING

Figure-14 Digital Loopback

LOS/AIS

Detection

LOS

Receiver

Internal

Termination

B8ZS/

HDB3/AMI

Decoder

Clock and

Data

RCLK

RD/RDP

CV/RDN

RTIP

Jitter

Attenuator

Adaptive

Equalizer

Data

Slicer

RRING

Recovery

Remote

Loopback

B8ZS/

HDB3/AMI

Encoder

TTIP

Transmitter

Internal

Termination

TCLK

TD/TDP

TDN

Waveform

Shaper/LBO

Jitter

Attenuator

Line

Driver

TRING

Figure-15 Remote Loopback

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3.8.4 INBAND LOOPBACK

bit-long or 8-bit-long respectively by repeating itself if it is 3-bit-long or 4-

bit-long.

When PATT[1:0] bits (MAINT0, 0DH) are set to ‘11’, the IDT82V2081

isconfiguredinInbandLoopbackmode.Inthismode,anunframedactivate/

Deactivate Loopback Code is generated repeatedly in transmit direction

per ANSI T1. 403 which overwrite the transmit signals. In receive direction,

theframedorunframedcodeisdetectedperANSIT1.403,eveninthepres-

AftertheActivateLoopbackCodehasbeendetectedinthereceivedata

for more than 30 ms (in E1 mode) / 40 ms (in T1/J1 mode), the IBLBA_S

bit (STAT0, 17H) will be set to ‘1’ to declare the reception of the Activate

Loopback Code.

-2

ence of 10 bit error rate.

After the Deactivate Loopback Code has been detected in the receive

dataformorethan30ms(InE1mode)/40ms(InT1/J1mode),theIBLBD_S

bit (STAT0, 17H) will be set to ‘1’ to declare the reception of the Deactivate

Loopback Code.

If the Automatic Remote Loopback is enabled by setting ARLP bit

(MAINT1, 0EH) to ‘1’, the chip will establish/demolish the Remote Loop-

back based on the reception of the Activate Loopback Code/Deactivate

Loopback Code for 5.1 s. If the ARLP bit (MAINT1, 0EH) is set to ‘0’, the

Remote Loopback can also be demolished forcedly.

WhentheIBLBA_IESbit(INTES, 16H)issetto‘0’, onlythe‘0’to‘1’tran-

sition of the IBLBA_S bit will generate an interrupt and set the IBLBA_IS bit

(INTS0, 19H) to ‘1’. When the IBLBA_IES bit is set to ‘1’, any changes of

the IBLBA_S bit will generate an interruptand set theIBLBA_IS bit (INTS0,

19H) to ‘1’. The IBLBA_IS bit will be reset to ‘0’ after being read.

3.8.4.1 Transmit Activate/Deactivate Loopback Code

The pattern of the transmit Activate/Deactivate Loopback Code is

defined by the TIBLB[7:0] bits (MAINT3, 10H). Whether the code repre-

sentsanActivateLoopbackCodeoraDeactivateLoopbackCodeisjudged

bythefarendreceiver. Thelengthofthepatternrangesfrom5bitsto8bits,

as selected by the TIBLB_L[1:0] bits (MAINT2, 0FH). The pattern can be

programmed to 6-bit-long or 8-bit-long by repeating itself respectively if it

is 3-bit-long or 4-bit-long. When the PATT[1:0] bits (MAINT0, 0DH) are set

to ‘11’, the transmission of the Activate/Deactivate Loopback Code is initi-

ated. If the PATT_CLK bit (MAINT0, 0DH) is set to ‘0’ and the PATT[1:0]

bits (MAINT0, 0DH) are set to ‘00’, the transmission of the Activate/Deac-

tivate Loopback Code will stop.

WhentheIBLBD_IESbit(INTES, 16H)issetto‘0’, onlythe‘0’to‘1’tran-

sition of the IBLBD_S bit will generate an interrupt and set the IBLBD_IS

bit (INTS0, 19H) to ‘1’. When the IBLBD_IES bit is set to ‘1’, any changes

of the IBLBD_S bit will generate an interrupt and set the IBLBD_IS bit

(INTS0, 19H) to ‘1’. The IBLBD_IS bit will be reset to ‘0’ after being read.

3.8.4.3 Automatic Remote Loopback

When ARLP bit (MAINT1, 0EH) is set to ‘1’, the IDT82V2081 is config-

ured into the Automatic Remote Loopback mode. In this mode, if the Acti-

vate Loopback Code has been detected in the receive data for more than

5.1s, theRemoteLoopback(shownasFigure-15)willbeestablishedauto-

matically, and the RLP_S bit (STAT1, 18H) will be set to ‘1’ to indicate the

establishment of the Remote Loopback. The IBLBA_S bit (STAT0, 17H) is

set to ‘1’ to generate an interrupt. In this case, the Remote Loopback mode

will still be kept even if the receiver stop receiving the Activate Loopback

Code.

The local transmit activate/deactivate code setting should be the same

as the receive code setting in the remote end. It is the same thing for the

other way round.

3.8.4.2 Receive Activate/Deactivate Loopback Code

The pattern of the receive Activate Loopback Code is defined by the

RIBLBA[7:0] bits (MAINT4, 11H). The length of this pattern ranges from 5

bits to 8 bits, as selected by the RIBLBA_L [1:0] bits (MAINT2, 0FH). The

pattern can be programmed to 6-bit-long or 8-bit-long respectively by

repeating itself if it is 3-bit-long or 4-bit-long.

If the Deactivate Loopback Code has been detected in the receive data

formorethan5.1s,theRemoteLoopbackwillbedemolishedautomatically,

and theRLP_S bit (STAT1, 18H) will set to ‘0’ to indicate the demolishment

oftheRemoteLoopback.TheIBLBD_Sbit(STAT0,17H)issetto‘1’togen-

erate an interrupt.

The pattern of the receive Deactivate Loopback Code is defined by the

RIBLBD[7:0] bits (MAINT5, 12H). The length of the receive Deactivate

Loopback Code ranges from 5 bits to 8 bits, as selected by the

RIBLBD_L[1:0] bits (MAINT2, 0FH). The pattern can be programmed to 6-

The Remote Loopback can also be demolished forcedly by setting

ARLP bit (MAINT1, 0EH) to ‘0’.

28

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•

HDB3/B8ZS Code Violation (CV) Error: In HDB3/B8ZS coding, a

CV error is declared when two consecutive BPV errors are

detected, and the pulses that have the same polarity as the previ-

ous pulse are not the HDB3/B8ZS zero substitution pulses.

Excess Zero (EXZ) Error: There are two standards defining the

EXZ errors: ANSI and FCC. The EXZ_DEF bit (MAINT6, 13H)

chooses which standard will be adopted by the chip to judge the

EXZ error. Table-21 shows definition of EXZ. In hardware control

mode, only ANSI standard is adopted.

3.9 ERROR DETECTION/COUNTING AND INSERTION

3.9.1 DEFINITION OF LINE CODING ERROR

The following line encoding errors can be detected and counted by the

IDT82V2081:

•

Received Bipolar Violation (BPV) Error: In AMI coding, when two

consecutive pulses of the same polarity are received, a BPV error

is declared.

Table-21 EXZ Definition

EXZ Definition

ANSI

FCC

AMI

More than 15 consecutive 0s are detected

More than 3 consecutive 0s are detected

More than 7 consecutive 0s are detected

More than 80 consecutive 0s are detected

More than 3 consecutive 0s are detected

More than 7 consecutive 0s are detected

HDB3

B8ZS

3.9.2 ERROR DETECTION AND COUNTING

Auto Report Mode

(CNT_MD=1)

Which type of the receiving errors (Received CV/BPV errors, excess

zero errors and PRBS logic errors) will be counted is determined by

ERR_SEL[1:0]bits(MAINT6, 13H). Onlyonetypeofreceivingerrorcanbe

counted at a time except that when the ERR_SEL[1:0] bits are set to ‘11’,

both CV/BPV and EXZ errors will be detected and counted.

counting

next second

repeats the

same process

N

Theselectedtypeofreceivingerrorsiscountedinaninternal16-bitError

Counter. Once an error is detected, an error interrupt which is indicated by

corresponding bitin (INTS1, 1AH)willbegenerated ifit isnotmasked. This

Error Counter can be operated in two modes: Auto Report Mode and Man-

ualReportMode, asselectedbytheCNT_MDbit(MAINT6, 13H). InSingle

Rail mode, once BPV or CV errors are detected, the CV pin will be driven

to high for one RCLK period.

One-Second Timer expired?

Y

CNT0, CNT1

counter

data in counter

0

Bit TMOV_IS is set to '1'

• Auto Report Mode

In Auto Report Mode, the internal counter starts to count the received

errorswhentheCNT_MDbit(MAINT6,13H)issetto‘1’.Aone-secondtimer

is used to set the counting period. The received errors are counted within

one second. If the one-second timer expires, the value in the internal

counterwillbetransferredto(CNT0,1BH)and(CNT1,1CH),thentheinter-

nal counter will be reset and start to count received errors for the next sec-

ond.Theerrorsoccurredduringthetransferwillbeaccumulatedtothenext

round. Theexpirationoftheone-secondtimerwillsetTMOV_ISbit(INTS1,

1AH) to‘1’, andwill generateaninterruptiftheTIMER_IMbit(INTM1, 15H)

issetto‘0’.TheTMOV_ISbit(INTS1,1AH)willbeclearedaftertheinterrupt

register is read. The content in the (CNT0, 1BH) and (CNT1, 1CH) should

beread withinthe next second. If thecounter overflows, a counteroverflow

interrupt which is indicated by CNT_OV_IS bit (INTS1, 1AH) will be gener-

ated if it is not masked by CNT_IM bit (INTM1, 15H).

read the data in CNT0, CNT1 within

the next second

Bit TMOV_IS is cleared after

the interrupt register is read

Figure-16 Auto Report Mode

29

INDUSTRIAL

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• Manual Report Mode

3.9.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION

In Manual Report Mode, the internal Error Counter starts to count the

received errors when the CNT_MD bit (MAINT6, 13H) is set to ‘0’. When

there is a ‘0’ to ‘1’ transition on the CNT_TRF bit (MAINT6, 13H), the data

in the counter will be transferred to (CNT0, 1BH) and (CNT1, 1CH), then

the counter will be reset. The errors occurred during the transfer will be

accumulated to thenext round. If thecounter overflows, a counteroverflow

interrupt indicated by CNT_OV_IS bit (INTS1, 1AH) will be generated if it

is not masked by CNT_IM bit (INTM1, 15H).

Only when three consecutive ‘1’s are detected in the transmit data

stream,willa‘0’to‘1’transitionontheBPV_INSbit(MAINT6,13H)generate

a bipolar violation pulse, and the polarity of the second ‘1’ in the series will

be inverted.

A ‘0’ to ‘1’ transition on the EER_INS bit (MAINT6, 13H) will generate a

logic error during the PRBS/QRSS transmission.

3.10 LINE DRIVER FAILURE MONITORING

Thetransmitdriverfailuremonitorcanbeenabledordisabledbysetting

DFM_OFF bit (TCF1, 06H). If the transmit driver failure monitor is enabled,

the transmit driver failure will be captured by DF_S bit (STAT0, 17H). The

transition of the DF_S bit is reflected by DF_IS bit (INTS0, 19H), and, if

enabled by DF_IMbit(INTM0, 14H), will generate aninterrupt. When there

is a short circuit on the TTIP/TRING port, the output current will be limited

to 100 mA (typical), and an interrupt will be generated.

Manual Report mode

(CNT_MD=0)

counting

N

A '0' to '1' transition

on CNT_TRF?

In hardware control mode, the transmit driver failure monitor is always

enabled.

next round

Y

repeat the

same process

CNT0, CNT1

counter

data in

counter

0

Read the data in CNT0,

CNT1 within next round¹

Reset CNT_TRF for the

next '0' to '1' transition

Figure-17 Manual Report Mode

Note: It is recommended that users should do the followings within next round of

error counting: Read the data in CNT0 and CNT1; Reset CNT_TRF bit for

the next ‘0’ to ‘1’ transition on this bit.

30

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3.11.2 TRANSMIT CLOCK (TCLK)

3.11 MCLK AND TCLK

TCLK is used to sample the transmit data on TD/TDP and TDN. The

active edge of TCLK can be selected by the TCLK_SEL bit (TCF0, 05H).

During Transmit All Ones, PRBS/QRSS patterns or Inband Loopback

Code, either TCLK or MCLK can be used as the reference clock. This is

selected by the PATT_CLK bit (MAINT0, 0DH).

3.11.1 MASTER CLOCK (MCLK)

MCLK is an independent, free-running reference clock. MCLK is 1.544

MHzforT1/J1applicationsand2.048MHzinE1mode.Thisreferenceclock

is used to generate several internal reference signals:

•

Timing reference for the integrated clock recovery unit.

Timing reference for the integrated digital jitter attenuator.

Timing reference for microcontroller interface.

Generation of RCLK signal during a loss of signal condition if AIS is

enabled.

But for Automatic Transmit All Ones and AIS, only MCLK is used as the

reference clock and the PATT_CLK bit is ignored. In Automatic Transmit

All Ones condition, the ATAO bit (MAINT0, 0DH) is set to ‘1’. In AIS condi-

tion, the AISE bit (MAINT0, 0DH) is set to ‘1’.

•

Reference clock during Transmit All Ones, All Zeros, PRBS/QRSS

pattern and Inband Loopback code if it is selected as the reference

clock. For ATAO and AIS, MCLK is always used as the reference

clock.

Reference clock during Transmit All Ones (TAO) condition or send-

ing PRBS/QRSS in hardware control mode.

If TCLK has been missing for more than 70 MCLK cycles, TCLK_LOS

bit (STAT0, 17H) will be set, and the TTIP/TRING will become high imped-

anceifthechipisnotusedforremoteloopbackorisnotusingMCLKtotrans-

mit internal patterns (TAOS, All Zeros, PRBS and in-band loopback code).

WhenTCLKisdetectedagain,TCLK_LOSbit(STAT0,17H)willbecleared.

The reference frequency to detect a TCLK loss is derived from MCLK.

•

Figure-18 shows the chip operation status in different conditions of

MCLK and TCLK. The missing of MCLK will set the TTIP/TRING to high

impedance state.

Clocked

MCLK=H/L?

yes

clocked

L/H

TCLK status?

generate transmit clock loss

interrupt if not masked in

software control mode;

normal operation

transmitter high impedance

Figure-18 TCLK Operation Flowchart

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3.12.1 PARALLEL MICROCONTROLLER INTERFACE

3.12 MICROCONTROLLER INTERFACES

TheinterfaceiscompatiblewithMotorolaorIntelmicrocontroller.When

MODE[1:0] pins are set to ‘10’, Parallel-Multiplexed-Motorola interface is

selected. When MODE[1:0] pins are set to ‘11’, Parallel-Multiplexed-Intel

Interface is selected.

Themicrocontrollerinterfaceprovidesaccesstoreadandwritethereg-

isters in the device. The chip supports serial microcontroller interface and

two kinds of parallel microcontroller interface: Motorola multiplexed mode

and Intel multiplexed mode. Different microcontroller interfaces can be

selected by setting MODE[1:0] pins to different values. Refer to MODE1

and MODE0 in pin description and 7 MICROCONTROLLER INTERFACE

TIMING CHARACTERISTICS for details.

3.12.2 SERIAL MICROCONTROLLER INTERFACE

When MODE[1:0] pins are set to‘01’, Serial Interface is selected. In this

mode, the registers are programmed through a 16-bit word which contains

an 8-bit address/command byte (5 address bits A0~A4 and bit R/W) and

an 8-bit data byte (D0~D7). When bit R/W is ‘1’, data is read out from pin

SDO. When bit R/W is ‘0’, data is written into SDI pin. Refer to Figure-19.

CS

SCLK

A0 A1 A2 A3 A4

-

R/W

D3

D7

D0

D1

D2

D4 D5 D6

SDI

address/command byte

input data byte (R/W=0)

D2

D4

D1

D3

D5 D6

SDO

output data byte (R/W=1)

remains high impedance

Figure-19 Serial Microcontroller Interface Function Timing

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There are totally fourteen kinds of events that could be the interrupt

source:

3.13 INTERRUPT HANDLING

All kinds of interrupt of the IDT82V2081 are indicated by the INT pin.

When the INT_PIN[0] bit (GCF, 02H) is ‘0’, the INT pin is open drain active

low, with a 10 KΩ external pull-up resistor. When the INT_PIN[1:0] bits

(GCF, 02H) are ‘01’, the INT pin is push-pull active low; when the

INT_PIN[1:0] bits are ‘10’, the INT pin is push-pull active high.

(1).LOS Detected

(2).AIS Detected

(3).Driver Failure Detected

(4).TCLK Loss

(5).Synchronization Status of PRBS

(6).PRBS Error Detected

AnactivelevelontheINTpinrepresentsaninterruptoftheIDT82V2081.

(7).Code Violation Received

(8).Excessive Zeros Received

(9).JA FIFO Overflow/Underflow

(10).Inband Loopback Code Status

(11).Equalizer Out of Range

(12).One-Second Timer Expired

(13).Error Counter Overflow

(14).Arbitrary Waveform Generator Overflow

The interrupt event is captured by the corresponding bit in the Interrupt

Status Register (INTS0, 19H) or (INTS1, 1AH). Every kind of interrupt can

be enabled/disabled individually by the corresponding bit in the register

(INTM0, 14H) or(INTM1, 15H). Someeventisreflectedbythecorrespond-

ing bit in the Status Register (STAT0, 17H) or (STAT1, 18H), and the Inter-

rupt Trigger Edge Selection Register can be used to determine how the

Status Register sets the Interrupt Status Register.

AftertheInterruptStatusRegister(INTS0,19H)or(INTS1,1AH)isread,

the INT pin become inactive.

Table-22isasummaryofallkindsofinterruptandtheassociatedStatus

bit, Interrupt Status bit, Interrupt Trigger Edge Selection bit and Interrupt

Mask bit.

Table-22 Interrupt Event

Interrupt Event

Status bit

(STAT0, STAT1)

Interrupt Status bit

(INTS0, INTS1)

Interrupt Edge Selection bit

(INTES)

Interrupt Mask bit

(INTM0, INTM1)

LOS Detected

AIS Detected

LOS_S

AIS_S

LOS_IS

AIS_IS

LOS_IES

AIS_IES

LOS_IM

AIS_IM

Driver Failure Detected

DF_S

DF_IS

DF_IES

DF_IM

TCLK Loss

TCLK_LOS

PRBS_S

TCLK_LOS_IS

PRBS_IS

ERR_IS

TCLK_IES

PRBS_IES

TCLK_IM

PRBS_IM

ERR_IM

CV_IM

Synchronization Status of PRBS/QRSS

PRBS/QRSS Error

Code Violation Received

Excessive Zeros Received

JA FIFO Overflow

CV_IS

EXZ_IS

EXZ_IM

JAOV_IS

JAUD_IS

EQ_IS

JAOV_IM

JAUD_IM

EQ_IM

JA FIFO Underflow

Equalizer Out of Range

EQ_S

EQ_IES

Inband Loopback Activate Code Status

Inband Loopback Deactivate Code Status

One-Second Timer Expired

Error Counter Overflow

IBLBA_S

IBLBD_S

IBLBA_IS

IBLBD_IS

TMOV_IS

CNT_OV_IS

DAC_OV_IS

IBLBA_IES

IBLBD_IES

IBLBA_IM

IBLBD_IM

TIMER_IM

CNT_IM

DAC_OV_IM

Arbitrary Waveform Generator Overflow

•

Hardware Reset: Asserting the RST pin low for a minimum of 100

3.14 5V TOLERANT I/O PINS

ns will reset the chip.

All digital input pins willtolerate5.0 ± 10% voltsand are compatible with

TTL logic.

Afterreset, alldriversoutputareinhighimpedancestate, alltheinternal

flip-flops are reset, and all the registers are initialized to default values.

3.15 RESET OPERATION

3.16 POWER SUPPLY

The chip can be reset in two ways:

This chip uses a single 3.3 V power supply.

•

Software Reset: Writing to the RST register (01H) will reset the chip

in 1 us.

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4

PROGRAMMING INFORMATION

4.1 REGISTER LIST AND MAP

The registers banks include control registers, status registers and

counter registers.

Table-23 Register List and Map

Address (hex)

Register

R/W

Map

b7

b6

b5

b4

b3

b2

b1

b0

Control Registers

00

01

02

03

04

ID

R

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

RST

W

GCF

TERM

JACF

R/W

-

T1E1

R_TERM2

JADP1

INT_PIN1

R_TERM1

JADP0

INT_PIN0

R_TERM0

JABW

T_TERM2

JA_LIMIT

T_TERM1

JACF1

T_TERM0

JACF0

Transmit Path Control Registers

05

06

07

08

09

TCF0

TCF1

TCF2

TCF3

TCF4

R/W

-

T_OFF

THZ

TD_INV

PULS3

SCAL3

SAMP3

WDAT3

TCLK_SEL

PULS2

T_MD1

PULS1

SCAL1

SAMP1

WDAT1

T_MD0

PULS0

SCAL0

SAMP0

WDAT0

-

DFM_OFF

SCAL5

UI1

-

DONE

-

SCAL4

UI0

SCAL2

RW

SAMP2

WDAT2

WDAT6

WDAT5

WDAT4

Receive Path Control Registers

0A

0B

0C

RCF0

RCF1

RCF2

R/W

-

R_OFF

LOS4

RD_INV

LOS3

RCLK_SEL

LOS2

R_MD1

LOS1

MG1

R_MD0

LOS0

MG0

EQ_ON

-

SLICE1

SLICE0

UPDW1

UPDW0

Network Diagnostics Control Registers

0D

0E

0F

10

11

MAINT0

MAINT1

MAINT2

MAINT3

MAINT4

MAINT5

MAINT6

R/W

-

PATT1

-

PATT0

-

PATT_CLK

-

PRBS_INV

ARLP

LAC

RLP

AISE

ALP

ATAO

DLP

-

TIBLB_L1

TIBLB5

RIBLBA5

RIBLBD5

ERR_INS

TIBLB_L0

TIBLB4

RIBLBA_L1 RIBLBA_L0 RIBLBD_L1 RIBLBD_L0

TIBLB7

RIBLBA7

RIBLBD7

-

TIBLB6

RIBLBA6

RIBLBD6

BPV_INS

TIBLB3

RIBLBA3

RIBLBD3

ERR_SEL1

TIBLB2

RIBLBA2

RIBLBD2

ERR_SEL0

TIBLB1

RIBLBA1

RIBLBD1

CNT_MD

TIBLB0

RIBLBA0

RIBLBD0

CNT_TRF

RIBLBA4

RIBLBD4

EXZ_DEF

12

13

Interrupt Control Registers

14

INTM0

R/W

EQ_IM

IBLBA_IM

IBLBD_IM

JAUD_IM

PRBS_IM

ERR_IM

TCLK_IM

EXZ_IM

DF_IM

CV_IM

DF_IES

AIS_IM

TIMER_IM

AIS_IES

LOS_IM

CNT_IM

LOS_IES

15

INTM1

INTES

R/W DAC_OV_IM JAOV_IM

16

R/W

EQ_IES

IBLBA_IES IBLBD_IES PRBS_IES

TCLK_IES

Line Status Register

17

18

STAT0

STAT1

R

EQ_S

-

IBLBA_S

-

IBLBD_S

RLP_S

PRBS_S

LATT4

TCLK_LOS

LATT3

DF_S

AIS_S

LATT1

LOS_S

LATT0

LATT2

Interrupt Status Register

19

INTS0

R

EQ_IS

IBLBA_IS

IBLBD_IS

JAUD_IS

PRBS_IS TCLK_LOS_IS

DF_IS

CV_IS

AIS_IS

LOS_IS

1A

INTS1

DAC_OV_IS JAOV_IS

ERR_IS

EXZ_IS

TMOV_IS CNT_OV_IS

Counter Registers

1B

1C

CNT0

CNT1

R

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit9

Bit0

Bit8

Bit15

Bit14

Bit13

Bit12

Bit11

Bit10

34

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

4.2 REGISTER DESCRIPTION

4.2.1 CONTROL REGISTERS

Table-24 ID: Device Revision Register

(R, Address = 00H)

Symbol

Bit

Default

Description

ID[7:0]

7-0

00H

00H is for the first version.

Table-25 RST: Reset Register

(W, Address = 01H)

Symbol

Bit

Default

RST[7:0]

7-0

00H

Software reset. A write operation on this register will reset all internal registers to their default values, and the status

of all ports are set to the default status. The content in this register can not be changed.

Table-26 GCF: Global Configuration Register

(R/W, Address = 02H)

Symbol

-

Bit

7-3

2

Default

00000

0

Description

Reserved.

T1E1

This bit selects the E1 or T1/J1 operation mode globally.

= 0: E1 mode is selected.

= 1: T1/J1 mode is selected.

INT_PIN[1:0]

1-0

00

Interrupt pin control

= X0: Open drain, active low (with an external pull-up resistor)

= 01: Push-pull, active low

= 11: Push-pull, active high

Table-27 TERM: Transmit and Receive Termination Configuration Register

(R/W, Address = 03H)

Symbol

Bit

7-6

5-3

Default

00

Description

-

Reserved.

T_TERM[2:0]

000

These bits select the internal termination for transmit line impedance matching.

= 000: Internal 75 Ω impedance matching

= 001: Internal 120 Ω impedance matching

= 010: Internal 100 Ω impedance matching

= 011: Internal 110 Ω impedance matching

= 1xx: Selects external impedance matching resistors for E1 mode only. T1/J1 does not require external impedance

resistors (see Table-14).

R_TERM[2:0]

2-0

000

These bits select the internal termination for receive line impedance matching.

= 000: Internal 75 Ω impedance matching

= 001: Internal 120 Ω impedance matching

= 010: Internal 100 Ω impedance matching

= 011: Internal 110 Ω impedance matching

= 1xx: Selects external impedance matching resistors (see Table-15).

35

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-28 JACF: Jitter Attenuation Configuration Register

(R/W, Address = 04H)

Symbol

-

Bit

7-6

5

Default

Description

00

1

Reserved.

JA_LIMIT

= 0: Normal mode

= 1: JA limit mode

JACF[1:0]

JADP[1:0]

JABW

4-3

2-1

0

00

0

Jitter attenuation configuration

= 00/10: JA not used

= 01: JA in transmit path

= 11: JA in receive path

Jitter attenuation depth select

= 00: 128 bits

= 01: 64 bits

= 1x: 32 bits

Jitter transfer function bandwidth select

= 0: 6.8 Hz (E1)

5 Hz (T1/J1)

= 1: 0.9 Hz (E1)

1.25 Hz (T1/J1)

4.2.2 TRANSMIT PATH CONTROL REGISTERS

Table-29 TCF0: Transmitter Configuration Register 0

(R/W, Address = 05H)

Symbol

-

Bit

7-5

4

Default

000

Description

Reserved.

T_OFF

0

Transmitter power down enable

= 0: Transmitter power up

= 1: Transmitter power down (line driver high impedance)

TD_INV

TCLK_SEL

T_MD[1:0]

3

2

0

Transmit data invert

= 0: Data on TD or TDP/TDN is active high

= 1: Data on TD or TDP/TDN is active low

Transmit clock edge select

= 0: Data on TDP/TDN is sampled on the falling edge of TCLK

= 1: Data on TDP/TDN is sampled on the rising edge of TCLK

0-1

00

Transmitter operation mode control

T_MD[1:0] select different stages of the transmit data path

= 00: Enable HDB3/B8ZS encoder and waveform shaper blocks. Input on pin TD is single rail NRZ data

= 01: Enable AMI encoder and waveform shaper blocks. Input on pin TD is single rail NRZ data

= 1x: Encoder is bypassed, dual rail NRZ transmit data input on pin TDP/TDN

36

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-30 TCF1: Transmitter Configuration Register 1

(R/W, Address = 06H)

Symbol

-

Bit

7-6

5

Default

Description

00

0

Reserved. This bit should be ‘0’ for normal operation.

DFM_OFF

Transmit driver failure monitor disable

= 0: DFM is enabled

= 1: DFM is disabled

THZ

4

1

Transmit line driver high impedance enable

= 0: Normal state

= 1: Transmit line driver high impedance enable (other transmit path still work normally)

PULS[3:0]

3-0

0000 These bits select the transmit template/LBO for short-haul/long-haul applications.

T1/E1/J1

E1

TCLK

Cable impedance Cable range or

Allowable Cable

loss

LBO

0000¹

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

11XX

2.048 MHz

75 Ω

-

0-43 dB

E1

2.048 MHz

1.544 MHz

120 Ω

100 Ω

110 Ω

100 Ω

-

0-43 dB

0-0.6 dB

0.6-1.2 dB

1.2-1.8 dB

1.8-2.4 dB

2.4-3.0 dB

0-3.0 dB

0-36 dB

DSX1

J1

0-133 ft

133-266 ft

266-399 ft

399-533 ft

533-655 ft

0-655 ft

DS1

0 dB LBO

-7.5 dB LBO

-15.0 dB LBO

-22.5 dB LBO

DS1

0-28.5 dB

0-21 dB

DS1

0-13.5 dB

User programmable waveform setting

1. In internal impedance matching mode, for E1/75 Ω cable impedance, the PULS[3:0] bits (TCF1, 06H) should be set to ‘0000’. In external impedance matching mode, for E1/75 Ω cable

impedance, the PULS[3:0] bits should be set to ‘0001’.

Table-31 TCF2: Transmitter Configuration Register 2

(R/W, Address = 07H)

Symbol

-

Bit

7-6

5-0

Default

00

Description

Reserved.

SCAL[5:0]

100001

SCAL specifies a scaling factor to be applied to the amplitude of the user-programmable arbitrary pulses which is

to be transmitted if needed. The default value of SCAL[5:0] is ‘100001’. Refer to 3.3.3.3 User-Programmable Arbi-

trary Waveform.

= 110110: Default value for T1 0~133 ft, T1 133~266 ft, T1 266~399 ft, T1 399~533 ft, T1 533~655 ft, J1 0~655 ft,

DS1 0dB LBO. One step change of this value results in 2% scaling up/down against the pulse amplitude.

= 010001: Default value for DS1 -7.5 dB LBO. One step change of this value results in 6.25% scaling up/down

against the pulse amplitude.

= 001000: Default value for DS1 -15.0 dB LBO. One step change of this value results in 12.5% scaling up/down

against the pulse amplitude.

= 000100: Default value for DS1 -22.5 dB LBO. One step change of this value results in 25% scaling up/down

against the pulse amplitude.

= 100001: Default value for E1 75 Ω and 120 Ω. One step change of this value results in 3% scaling up/down

against the pulse amplitude.

37

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-32 TCF3: Transmitter Configuration Register 3

(R/W, Address = 08H)

Symbol

DONE

RW

Bit

7

Default

Description

0

After ‘1’ is written to this bit, a read or write operation is implemented.

6

This bit selects read or write operation

= 0: Write to RAM

= 1: Read from RAM

UI[1:0]

5-4

3-0

00

These bits specify the unit interval address. There are totally 4 unit intervals.

= 00: UI address is 0 (The most left UI)

= 01: UI address is 1

= 10: UI address is 2

= 11: UI address is 3

SAMP[3:0]

0000

These bits specify the sample address. Each UI has totally 16 samples.

= 0000: Sample address is 0 (The most left sample)

= 0001: Sample address is 1

= 0010: Sample address is 2

……

= 1110: Sample address is 14

= 1111: Sample address is 15

Table-33 TCF4: Transmitter Configuration Register 4

(R/W, Address = 09H)

Symbol

-

Bit

7

Default

Description

0

Reserved

WDAT[6:0]

6-0

0000000 In Indirect Write operation, the WDAT[6:0] will be loaded to the pulse template RAM, specifying the amplitude of

the Sample.

After an Indirect Read operation, the amplitude data of the Sample in the pulse template RAM will be output to the

WDAT[6:0].

4.2.3 RECEIVE PATH CONTROL REGISTERS

Table-34 RCF0: Receiver Configuration Register 0

(R/W, Address = 0AH)

Symbol

-

Bit

7-5

4

Default

000

Description

Reserved

R_OFF

0

Receiver power down enable

= 0: Receiver power up

= 1: Receiver power down

RD_INV

RCLK_SEL

R_MD[1:0]

3

2

0

Receive data invert

= 0: Data on RD or RDP/RDN is active high

= 1: Data on RD or RDP/RDN is active low

Receive clock edge select (this bit is ignored in slicer mode)

= 0: Data on RD or RDP/RDN is updated on the rising edge of RCLK

= 1: Data on RD or RDP/RDN is updated on the falling edge of RCLK

1-0

00

Receive path decoding selection

= 00: Receive data is HDB3 (E1)/B8ZS (T1/J1) decoded and output on RD pin with single rail NRZ format

= 01: Receive data is AMI decoded and output on RD pin with single rail NRZ format

= 10: Decoder is bypassed, re-timed dual rail data with NRZ format output on RDP/RDN (dual rail mode with clock

recovery)

= 11: CDR and decoder are bypassed, slicer data with RZ format output on RDP/RDN (slicer mode)

38

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-35 RCF1: Receiver Configuration Register 1

(R/W, Address= 0BH)

Symbol

-

Bit

7

Default

Description

0

Reserved

EQ_ON

6

= 0: Receive equalizer off (short haul receiver)

= 1: Receive equalizer on (long haul receiver)

-

5

0

Reserved.

LOS[4:0]

4:0

10101

LOS Clear Level (dB)

LOS Declare Level (dB)

00000

00001

00010

00011

00100

00101

00110

00111

0

<-4

>-2

<-6

>-4

<-8

>-6

<-10

<-12

<-14

<-16

<-18

<-20

<-22

<-24

<-26

<-28

<-30

<-32

<-34

<-36

<-38

<-40

<-42

<-44

<-46

<-48

>-8

>-10

>-12

>-14

>-16

>-18

>-20

>-22

>-24

>-26

>-28

>-30

>-32

>-34

>-36

>-38

>-40

>-42

>-44

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110 -11111

39

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-36 RCF2: Receiver Configuration Register 2

(R/W, Address = 0CH)

Symbol

-

Bit

7-6

5-4

Default

00

Description

Reserved.

SLICE[1:0]

01

Receive slicer threshold

= 00: The receive slicer generates a mark if the voltage on RTIP/RRING exceeds 40% of the peak amplitude.

= 01: The receive slicer generates a mark if the voltage on RTIP/RRING exceeds 50% of the peak amplitude.

= 10: The receive slicer generates a mark if the voltage on RTIP/RRING exceeds 60% of the peak amplitude.

= 11: The receive slicer generates a mark if the voltage on RTIP/RRING exceeds 70% of the peak amplitude.

UPDW[1:0]

MG[1:0]

3-2

1-0

10

00

Equalizer observation window

= 00: 32 bits

= 01: 64 bits

= 10: 128 bits

= 11: 256 bits

Monitor gain setting: these bits select the internal linear gain boost

= 00: 0 dB

= 01: 22 dB

= 10: 26 dB

= 11: 32 dB

4.2.4 NETWORK DIAGNOSTICS CONTROL REGISTERS

Table-37 MAINT0: Maintenance Function Control Register 0

(R/W, Address = 0DH)

Symbol

-

Bit

7

Default

00

Description

Reserved.

PATT[1:0]

6-5

00

These bits select the internal pattern and insert it into transmit data stream.

= 00: Normal operation (PATT_CLK = 0) / insert all zeros (PATT_CLK = 1)

= 01: Insert All Ones

= 10: Insert PRBS (E1: 2¹⁵-1) or QRSS (T1/J1: 2²⁰-1)

= 11: Insert programmable Inband loopback activate or deactivate code (default value 00001)

PATT_CLK

PRBS_INV

LAC

4

3

2

1

0

Selects reference clock for transmitting internal pattern

= 0: Uses TCLK as the reference clock

= 1: Uses MCLK as the reference clock

Inverts PRBS

= 0: The PRBS data is not inverted

= 1: The PRBS data is inverted before transmission and detection

LOS/AIS criterion is selected as below:

= 0: G.775 (E1) / T1.231 (T1/J1)

= 1: ETSI 300233& I.431 (E1) / I.431 (T1/J1)

AISE

AIS enable during LOS

= 0: AIS insertion on RDP/RDN/RCLK is disabled during LOS

= 1: AIS insertion on RDP/RDN/RCLK is enabled during LOS

ATAO

Automatically Transmit All Ones (enabled only when PATT[1:0] = 01)

= 0: Disabled

= 1: Automatically Transmit All Ones pattern at TTIP/TRING during LOS

40

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-38 MAINT1: Maintenance Function Control Register 1

(R/W, Address= 0EH)

Symbol

-

Bit

7-4

3

Default

0000

0

Description

Reserved

ARLP

Automatic remote loopback enable

= 0: Disables automatic remote loopback (normal transmit and receive operation)

= 1: Enables automatic remote loopback

RLP

ALP

DLP

2

1

0

Remote loopback enable

= 0: Disables remote loopback (normal transmit and receive operation)

= 1: Enables remote loopback

Analog loopback enable

= 0: Disables analog loopback (normal transmit and receive operation)

= 1: Enables analog loopback

Digital loopback enable

= 0: Disables digital loopback (normal transmit and receive operation)

= 1: Enables digital loopback

Table-39 MAINT2: Maintenance Function Control Register 2

(R/W, Address = 0F0H)

Symbol

Bit

7-6

5-4

Default

00

Description

-

Reserved

TIBLB_L[1:0]

00

Defines the length of the user-programmable transmit loopback activate/deactivate code contained in TIBLB reg-

ister. The default selection is 5 bits length.

= 00: 5-bit long activate code in TIBLB [4:0]

= 01: 6-bit long activate code in TIBLB [5:0]

= 10: 7-bit long activate code in TIBLB [6:0]

= 11: 8-bit long activate code in TIBLB [7:0]

RIBLBA_L[1:0]

RIBLBD_L[1:0]

3-2

1-0

00

01

Defines the length of the user-programmable receive activate loopback code contained in RIBLBA register. The

default selection is 5 bits length.

= 00: 5-bit long activate code in RIBLBA [4:0]

= 01: 6-bit long activate code in RIBLBA [5:0]

= 10: 7-bit long activate code in RIBLBA [6:0]

= 11: 8-bit long activate code in RIBLBA [7:0]

Defines the length of the user-programmable receive deactivate loopback code contained in RIBLBD register. The

default selection is 6 bits length.

= 00: 5-bit long deactivate code in RIBLBD [4:0]

= 01: 6-bit long deactivate code in RIBLBD [5:0]

= 10: 7-bit long deactivate code in RIBLBD [6:0]

= 11: 8-bit long deactivate code in RIBLBD [7:0]

Table-40 MAINT3: Maintenance Function Control Register 3

(R/W, Address = 10H)

Symbol

Bit

Default

Description

TIBLB[7:0]

7-0

(000)00001 Defines the user-programmable transmit Inband loopback activate or deactivate code. The default selection is

00001.

TIBLB [7:0] form the 8-bit repeating code

TIBLB [6:0] form the 7-bit repeating code

TIBLB [5:0] form the 6-bit repeating code

TIBLB [4:0] form the 5-bit repeating code

41

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-41 MAINT4: Maintenance Function Control Register 4

(R/W, Address = 11H)

Symbol

Bit

Default

Description

RIBLBA[7:0]

7-0

(000)00001 Defines the user-programmable receive Inband loopback activate code. The default selection is 00001.

RIBLBA [7:0] form the 8-bit repeating code

RIBLBA [6:0] form the 7-bit repeating code

RIBLBA [5:0] form the 6-bit repeating code

RIBLBA [4:0] form the 5-bit repeating code

Table-42 MAINT5: Maintenance Function Control Register 5

(R/W, Address = 12H)

Symbol

Bit

Default

Description

RIBLBD[7:0]

7-0

(00)001001 Defines the user-programmable receive Inband loopback deactivate code. The default selection is 001001.

RIBLBD [7:0] form the 8-bit repeating code

RIBLBD [6:0] form the 7-bit repeating code

RIBLBD [5:0] form the 6-bit repeating code

RIBLBD [4:0] form the 5-bit repeating code

Table-43 MAINT6: Maintenance Function Control Register 6

(R/W, Address = 13H)

Symbol

-

Bit

7

Default

Description

0

Reserved.

BPV_INS

6

BPV error insertion

A ‘0’ to ‘1’ transition on this bit will cause a single bipolar violation error to be inserted into the transmit data stream.

This bit must be cleared and set again for a subsequent error to be inserted.

ERR_INS

EXZ_DEF

ERR_SEL

5

0

PRBS logic error insertion

A ‘0’ to ‘1’ transition on this bit will cause a single PRBS logic error to be inserted into the transmit PRBS data stream.

This bit must be cleared and set again for a subsequent error to be inserted.

EXZ definition select

= 0: ANSI

= 1: FCC

3-2

00

These bits choose which type of error will be counted

= 00: The PRBS logic error is counted by a 16-bit error counter.

= 01: The EXZ error is counted by a 16-bit error counter.

= 10: The Received CV (BPV) error is counted by a 16-bit error counter.

= 11: Both CV (BPV) and EXZ errors are counted by a 16-bit error counter.

CNT_MD

CNT_TRF

1

0

Counter operation mode select

= 0: Manual Report mode

= 1: Auto Report mode

= 0: Clear this bit for the next ‘0’ to ‘1’ transition on this bit.

= 1: Error counting result is transferred to CNT0 and CNT1 and the error counter is reset.

42

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

4.2.5 INTERRUPT CONTROL REGISTERS

Table-44 INTM0: Interrupt Mask Register 0

(R/W, Address = 14H)

Symbol

Bit

Default

Description

EQ_IM

7

1

Equalizer out of range interrupt mask

= 0: Equalizer out of range interrupt enabled

= 1: Equalizer out of range interrupt masked

IBLBA_IM

IBLBD_IM

PRBS_IM

TCLK_IM

DF_IM

6

5

4

3

2

1

0

1

In-band Loopback activate code detect interrupt mask

= 0: In-band Loopback activate code detect interrupt enabled

= 1: In-band Loopback activate code detect interrupt masked

In-band Loopback deactivate code detect interrupt mask

= 0: In-band Loopback deactivate code detect interrupt enabled

= 1: In-band Loopback deactivate code detect interrupt masked

PRBS synchronic signal detect interrupt mask

= 0: PRBS synchronic signal detect interrupt enabled

= 1: PRBS synchronic signal detect interrupt masked

TCLK loss detect interrupt mask

= 0: TCLK loss detect interrupt enabled

= 1: TCLK loss detect interrupt masked

Driver Failure interrupt mask

= 0: Driver Failure interrupt enabled

= 1: Driver Failure interrupt masked

AIS_IM

Alarm Indication Signal interrupt mask

= 0: Alarm Indication Signal interrupt enabled

= 1: Alarm Indication Signal interrupt masked

LOS_IM

Loss Of Signal interrupt mask

= 0: Loss Of Signal interrupt enabled

= 1: Loss Of Signal interrupt masked

43

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-45 INTM1: Interrupt Masked Register 1

(R/W, Address = 15H)

Symbol

Bit

Default

Description

DAC_OV_IM

7

1

DAC arithmetic overflow interrupt mask

= 0: DAC arithmetic overflow interrupt enabled

= 1: DAC arithmetic overflow interrupt masked

JAOV_IM

JAUD_IM

ERR_IM

EXZ_IM

CV_IM

6

5

4

3

2

1

0

1

JA overflow interrupt mask

= 0: JA overflow interrupt enabled

= 1: JA overflow interrupt masked

JA underflow interrupt mask

= 0: JA underflow interrupt enabled

= 1: JA underflow interrupt masked

PRBS/QRSS logic error detect interrupt mask

= 0: PRBS/QRSS logic error detect interrupt enabled

= 1: PRBS/QRSS logic error detect interrupt masked

Receive excess zeros interrupt mask

= 0: Receive excess zeros interrupt enabled

= 1: Receive excess zeros interrupt masked

Receive error interrupt mask

= 0: Receive error interrupt enabled

= 1: Receive error interrupt masked

TIMER_IM

CNT_IM

One-Second Timer expiration interrupt mask

= 0: One-Second Timer expiration interrupt enabled

= 1: One-Second Timer expiration interrupt masked

Counter overflow interrupt mask

= 0: Counter overflow interrupt enabled

= 1: Counter overflow interrupt masked

44

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-46 INTES: Interrupt Trigger Edge Select Register

(R/W, Address = 16H)

Symbol

Bit

Default

Description

EQ_IES

7

0

This bit determines the Equalizer out of range interrupt event.

= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the EQ_S bit in the STAT0 status register

= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the EQ_S bit in the STAT0

status register.

IBLBA_IES

IBLBD_IES

PRBS_IES

TCLK_IES

DF_IES

6

5

4

3

2

1

0

This bit determines the Inband Loopback Activate Code interrupt event.

= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the IBLBA_S bit in STAT0 status register

= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBA_S bit in STAT0

status register

This bit determines the Inband Loopback Deactivate Code interrupt event.

= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the IBLBD_S bit in STAT0 status register

= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the IBLBD_S bit in STAT0

status register

This bit determines the PRBS/QRSS synchronization status interrupt event.

= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the PRBS_S bit in STAT0 status register

= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the PRBS_S bit in STAT0

status register

This bit determines the TCLK Loss interrupt event.

= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the TCLK_LOS bit in STAT0 status register

= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the TCLK_LOS bit in STAT0

status register

This bit determines the Driver Failure interrupt event.

= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the DF_S bit in STAT0 status register

= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the DF_S bit in STAT0 status

register

AIS_IES

This bit determines the AIS interrupt event.

= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the AIS_S bit in STAT0 status register

= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the AIS_S bit in STAT0 status

register

LOS_IES

This bit determines the LOS interrupt event.

= 0: Interrupt is generated as a ‘0’ to ‘1’ transition of the LOS_S bit in STAT0 status register

= 1: Interrupt is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the LOS_S bit in STAT0 status

register

45

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SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

4.2.6 LINE STATUS REGISTERS

Table-47 STAT0: Line Status Register 0 (real time status monitor)

(R, Address = 17H)

Symbol

Bit

Default

Description

EQ_S

7

0

Equalizer status indication

= 0: In range

= 1: Out of range

IBLBA_S

6

0

In-band Loopback activate code receive status indication

= 0: No Inband Loopback activate code is detected

= 1: Activate signal is detected and then received over a period of more than t ms, with a bit error rate less than 10^-

². The bit remains set as long as the bit error rate does not exceed 10^-2.

Note1:

If automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms.

If automatic remote loopback switching is enabled (ARLP = 1), t = 5.1 s. The rising edge of this bit activates the

remote loopback operation in local end.

Note2:

If IBLBA_IM=0:

A ‘0’ to ‘1’ transition on this bit causes an activate code detected interrupt if IBLBA _IES bit is ‘0’;

Any changes of this bit causes an activate code detected interrupt if IBLBA _IES bit is set to ‘1’.

IBLBD_S

5

0

In-band Loopback deactivate code receive status indication

= 0: No Inband Loopback deactivate signal is detected

= 1: The Inband Loopback deactivate signal is detected and then received over a period of more than t, with a bit

error rate less than 10^-2. The bit remains set as long as the bit error rate does not exceed 10^-2.

Note1:

If automatic remote loopback switching is disabled (ARLP = 0), t = 40 ms.

If automatic remote loopback switching is enabled (ARLP = 1), t = 5.1 s. The rising edge of this bit disables the

remote loopback operation.

Note2:

If IBLBD_IM=0:

A ‘0’ to ‘1’ transition on this bit causes a deactivate code detected interrupt if IBLBD _IES bit is ‘0’

Any changes of this bit causes a deactivate code detected interrupt if IBLBD _IES bit is set to ‘1’

PRBS_S

4

0

Synchronous status indication of PRBS/QRSS (real time)

= 0: 2¹⁵-1 (E1) PRBS or 2²⁰-1 (T1/J1) QRSS is not detected

= 1: 2¹⁵-1 (E1) PRBS or 2²⁰-1 (T1/J1) QRSS is detected

Note:

If PRBS_IM=0:

A ‘0’ to ‘1’ transition on this bit causes a synchronous status detected interrupt if PRBS _IES bit is ‘0’.

Any changes of this bit causes an interrupt if PRBS_IES bit is set to ‘1’.

TCLK_LOS

3

2

0

TCLK loss indication

= 0: Normal

= 1: TCLK pin has not toggled for more than 70 MCLK cycles.

Note:

If TCLK_IM=0:

A ‘0’ to ‘1’ transition on this bit causes an interrupt if TCLK _IES bit is ‘0’.

Any changes of this bit causes an interrupt if TCLK_IES bit is set to ‘1’.

DF_S

Line driver status indication

= 0: Normal operation

= 1: Line driver short circuit is detected.

Note:

If DF_IM=0

A ‘0’ to ‘1’ transition on this bit causes an interrupt if DF _IES bit is ‘0’.

Any changes of this bit causes an interrupt if DF_IES bit is set to ‘1’.

46

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TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-47 STAT0: Line Status Register 0 (real time status monitor) (Continued)

(R, Address = 17H)

Symbol

Bit

Default

Description

AIS_S

1

0

Alarm Indication Signal status detection

= 0: No AIS signal is detected in the receive path

= 1: AIS signal is detected in the receive path

Note:

If AIS_IM=0

A ‘0’ to ‘1’ transition on this bit causes an interrupt if AIS _IES bit is ‘0’.

Any changes of this bit causes an interrupt if AIS_IES bit is set to ‘1’.

LOS_S

0

Loss Of Signal status detection

= 0: Loss of signal on RTIP/RRING is not detected.

= 1: Loss of signal on RTIP/RRING is detected.

Note:

If LOS_IM=0

A ‘0’ to ‘1’ transition on this bit causes an interrupt if LOS _IES bit is ‘0’.

Any changes of this bit causes an interrupt if LOS_IES bit is set to ‘1’.

Table-48 STAT1: Line Status Register 1 (real time status monitor)

(R, Address = 18H)

Symbol

-

Bit

7-6

5

Default

Description

00

0

Reserved.

RLP_S

Indicating the status of Remote Loopback

= 0: The remote loopback is inactive.

= 1: The remote loopback is active (closed).

LATT[4:0]

4-0

00000

Line Attenuation Indication

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

0 to 2 dB

2 to 4 dB

4 to 6 dB

6 to 8 dB

8 to 10 dB

10 to 12 dB

12 to 14 dB

14 to 16 dB

16 to 18 dB

18 to 20 dB

20 to 22 dB

22 to 24 dB

24 to 26 dB

26 to 28 dB

28 to 30 dB

30 to 32 dB

32 to 34 dB

34 to 36 dB

36 to 38 dB

38 to 40 dB

40 to 42 dB

42 to 44 dB

>44 dB

10000

10001

10010

10011

10100

10101

10110-11111

47

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

4.2.7 INTERRUPT STATUS REGISTERS

Table-49 INTS0: Interrupt Status Register 0

(R, Address = 19H) (this register is reset and relevant interrupt request is cleared after a read)

Symbol

Bit

Default

Description

EQ_IS

7

0

This bit indicates the occurrence of Equalizer out of range interrupt event.

= 0: No interrupt event from the Equalizer out of range occurred

= 1: Interrupt event from the Equalizer out of range occurred

IBLBA_IS

IBLBD_IS

PRBS_IS

TCLK_LOS_IS

DF_IS

6

5

4

3

2

1

0

This bit indicates the occurrence of the Inband Loopback Activate Code interrupt event.

= 0: No Inband Loopback Activate Code interrupt event occurred

= 1: Inband Loopback Activate Code interrupt event occurred

This bit indicates the occurrence of the Inband Loopback Deactivate Code interrupt event.

= 0: No Inband Loopback Deactivate Code interrupt event occurred

= 1: Interrupt event of the received Inband Loopback Deactivate Code occurred.

This bit indicates the occurrence of the interrupt event generated by the PRBS/QRSS synchronization status.

= 0: No PRBS/QRSS synchronization status interrupt event occurred

= 1: PRBS/QRSS synchronization status interrupt event occurred

This bit indicates the occurrence of the interrupt event generated by the TCLK loss detection.

= 0: No TCLK loss interrupt event.

= 1:TCLK loss interrupt event occurred.

This bit indicates the occurrence of the interrupt event generated by the Driver Failure.

= 0: No Driver Failure interrupt event occurred

= 1: Driver Failure interrupt event occurred

AIS_IS

This bit indicates the occurrence of the AIS (Alarm Indication Signal) interrupt event.

= 0: No AIS interrupt event occurred

= 1: AIS interrupt event occurred

LOS_IS

This bit indicates the occurrence of the LOS (Loss of signal) interrupt event.

= 0: No LOS interrupt event occurred

= 1: LOS interrupt event occurred

48

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TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-50 INTS1: Interrupt Status Register 1

(R, Address = 1AH) (this register is reset and the relevant interrupt request is cleared after a read)

Symbol

Bit

Default

Description

DAC_OV_IS

7

0

This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event.

= 0: No pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred

= 1: The pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred

JAOV_IS

JAUD_IS

ERR_IS

6

5

4

3

2

1

0

This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event.

= 0: No JA Overflow interrupt event occurred

= 1: JA Overflow interrupt event occurred

This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event.

= 0: No JA Underflow interrupt event occurred

= 1: JA Underflow interrupt event occurred

This bit indicates the occurrence of the interrupt event generated by the detected PRBS/QRSS logic error.

= 0: No PRBS/QRSS logic error interrupt event occurred

= 1: PRBS/QRSS logic error interrupt event occurred

EXZ_IS

This bit indicates the occurrence of the Excessive Zeros interrupt event.

= 0: No Excessive Zeros interrupt event occurred

= 1: EXZ interrupt event occurred

CV_IS

This bit indicates the occurrence of the Code Violation interrupt event.

= 0: No Code Violation interrupt event occurred

= 1: Code Violation interrupt event occurred

TMOV_IS

CNT_OV_IS

This bit indicates the occurrence of the One-Second Timer Expiration interrupt event.

= 0: No One-Second Timer Expiration interrupt event occurred

= 1: One-Second Timer Expiration interrupt event occurred

This bit indicates the occurrence of the Counter Overflow interrupt event.

= 0: No Counter Overflow interrupt event occurred

= 1: Counter Overflow interrupt event occurred

4.2.8 COUNTER REGISTERS

Table-51 CNT0: Error Counter L-byte Register 0

(R, Address = 1BH)

Symbol

Bit

Default

Description

CNT_L[7:0]

7-0

00H

This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.

Table-52 CNT1: Error Counter H-byte Register 1

(R, Address = 1CH)

Symbol

Bit

Default

Description

CNT_H[7:0]

7-0

00H

This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.

49

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TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

5

HARDWARE CONTROL PIN SUMMARY

Table-53 Hardware Control Pin Summary

Pin No.

TQFP

Symbol

Description

17

16

MODE1

MODE0

MODE[1:0]: Operation mode of control interface select

00= Hardware interface

01= Serial interface

10= Parallel – multiplexed – Motorola Interface

11= Parallel – multiplexed – Intel Interface

23

TERM

TERM: Termination interface select

This pin selects internal or external impedance matching for both receiver and transmitter

0= ternary interface with external impedance matching network. External impedance matching is not supported in T1/J1 transmit

line interface.

1= ternary interface with internal impedance matching network

21

20

RXTXM1

RXTXM0

RXTXM[1:0]: Receive and transmit path operation mode select

00= single rail with HDB3/B8ZS coding

01= single rail with AMI coding

10= dual rail interface with CDR enable

11= slicer mode

33

32

31

30

PULS3

PULS2

PULS1

PULS0

PULS[3:0]: These pins are used to select the following functions:

•

T1/E1/J1 mode

Transmit pulse template

Internal termination impedance (75Ω/100Ω/110Ω/120Ω)

PULS[3:0]

T1/E1/J1

TCLK

Cable impedance Cable range or

Cable loss

(internal matching

impedance)

LBO

0000

0001

E1

2.048 MHz

1.544 MHz

75Ω

-

0-43 dB

120Ω

100Ω

110Ω

100Ω

-

0010

DSX1

J1

0-133 ft

0-0.6 dB

0.6-1.2 dB

1.2-1.8 dB

1.8-2.4 dB

2.4-3.0 dB

0-3.0 dB

0-36 dB

0011

133-266 ft

266-399 ft

399-533 ft

533-655 ft

0-655 ft

0100

0101

0110

0111

1000

DS1

0 dB LBO

-7.5 dB LBO

-15.0 dB LBO

-22.5 dB LBO

-

1001

0-28.5 dB

0-21 dB

1010

1011

0-13.5 dB

1100 - 1111

29

28

EQ

EQ: Receive equalizer on/off

When the chip is configured by hardware, this pin selects Short Haul or Long Haul operation mode

0= short haul (10 dB)

1= long haul (36 dB for T1/J1, 43 dB for E1)

RPD

RPD: Receiver power down control

0= Normal operation

1= receiver power down

27

26

PATT1

PATT0

PATT[1:0]: Transmit test pattern select

In hardware control mode, these pins select the transmit pattern

00 = normal

01= All Ones

10= PRBS

11= transmitter power down

50

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TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-53 Hardware Control Pin Summary (Continued)

Pin No.

TQFP

Symbol

Description

15

14

JA1

JA0

JA[1:0]: Jitter attenuation position , bandwidth and the depth of FIFO select

00= JA is disabled

01= JA in receiver, broad bandwidth, FIFO=64 bits

10= JA in receiver, narrow bandwidth, FIFO=128 bits

11= JA in transmitter, narrow bandwidth, FIFO=128 bits

22

MONT

MONT: Receive monitor n gain select

0= 0 dB

1= up to 26 dB

25

24

LP1

LP0

LP[1:0]: Loopback mode select

00= no loopback

01= analog loopback

10= digital loopback

11= remote loopback

13

11

THZ

THZ: Transmitter Driver High Impedance Enable

This signal enables or disables transmitter driver. A low level on this pin enables the driver while a high level on this pin places the

driver in high impedance state.

RCLKE

RCLKE: the active edge of RCLK select when hardware control mode is used

0= select the rising edge as active edge of RCLK

1= select the falling edge as active edge of RCLK

51

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TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

6

TEST SPECIFICATIONS

Table-54 Absolute Maximum Rating

Symbol

Parameter

Min

-0.5

Max

4.6

5.5

Unit

V

VDDA, VDDD

VDDIO

Core Power Supply

I/O Power Supply

-0.5

V

VDDT

Transmit Power Supply

-0.5

V

Input Voltage, Any Digital Pin

GND-0.5

V

Vin

Input Voltage, Any RTIP and RRING pin¹

ESD Voltage, any pin

VDDA+0.5

V

2000 ²

500 ³

Transient latch-up current, any pin

Input current, any digital pin ⁴

100

10

mA

Iin

-10

DC Input current, any analog pin ⁴

Maximum power dissipation in package

Case Temperature

±100

mA

Pd

1.41

120

W

°C

Tc

Ts

Storage Temperature

-65

+150

CAUTION:

Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

1.Reference to ground

2.Human body model

3.Charge device model

4.Constant input current

Table-55 Recommended Operation Conditions

Symbol

Parameter

Min

3.13

-40

Typ

3.3

25

Max

3.47

85

Unit

V

VDDA,VDDD

VDDIO

VDDT

Core Power Supply

I/O Power Supply

V

Transmitter Power Supply

Ambient operating temperature

E1, 75 Ω load

V

TA

°C

50% ones density data

100% ones density data

-

52

64

58

70

mA

E1, 120 Ω Load

T1, 100 Ω Load

J1, 110 Ω Load

50% ones density data

100% ones density data

-

58

70

64

76

Total current dissipation^1,2,3

50% ones density data

100% ones density data

-

59

88

65

95

50% ones density data

100% ones density data

-

47

58

53

64

1.Power consumption includes power consumption on device and load. Digital levels are 10% of the supply rails and digital outputs driving a 50 pF capacitive load.

2.Maximum power consumption over the full operating temperature and power supply voltage range.

3.Inshorthaulmode,ifinternalimpedancematchingischosen,E175ΩpowerdissipationvaluesaremeasuredwithtemplatePULS[3:0]=0000;E1120Ωpowerdissipationvaluesaremeasured

with template PULS[3:0] = 0001; T1 power dissipation values are measured with template PULS[3:0] = 0110; J1 power dissipation values are measured with template PULS[3:0] = 0111.

52

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-56 Power Consumption

Max^1,2

Unit

Symbol

Parameter

Min

Typ

E1, 3.3 V, 75 Ω Load

E1, 3.3 V, 120 Ω Load

50% ones density data:

100% ones density data:

-

172

212

-

mW

243

50% ones density data:

100% ones density data:

-

192

243

-

264

T1, 3.3 V, 100 Ω Load³

J1, 3.3 V, 110 Ω Load

-

195

291

-

50% ones density data:

100% ones density data:

330

50% ones density data:

100% ones density data:

-

155

192

mW

222

1.Maximum power and current consumption over the full operating temperature and power supply voltage range.

2.Power consumption includes power absorbed by line load and external transmitter components.

3.T1 is measured with maximum cable length.

Table-57 DC Characteristics

Symbol

Parameter

Input Low Level Voltage

Min

Typ

Max

Unit

V_IL

V_IH

-

0.8

V

Input High Voltage

2.0

-

V_OL

V_OH

V_MA

Output Low level Voltage (Iout=1.6mA)

Output High level Voltage (Iout=400µA)

0.4

2.4

-

VDDIO

Analog Input Quiescent Voltage (RTIP, RRING

pin while floating)

1.5

I_ZL

High Impedance Leakage Current

-10

10

µA

Ci

Input capacitance

15

50

pF

Co

Output load capacitance

Output load capacitance (bus pins)

100

53

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-58 E1 Receiver Electrical Characteristics

Symbol

Parameter

Receiver sensitivity

Min

Typ

Max

Unit

Test conditions

Short haul with cable loss@1024kHz:

Long haul with cable loss@1024kHz:

-10

-43

dB

Analog LOS level

Short haul

Long haul

800

mVp-p A LOS level is programmable for Long Haul

dB

-4

-48

0.05

±1%

Allowable consecutive zeros before LOS

G.775:

32

2048

I.431/ETSI300233:

LOS reset

12.5

% ones G.775, ETSI 300 233

Receive Intrinsic Jitter

20Hz - 100kHz

U.I.

JA enabled

Input Jitter Tolerance

1 Hz – 20 Hz

37

5

2

U.I.

G.823, with 6 dB cable attenuation

20 Hz – 2.4 KHz

18 KHz – 100 KHz

ZDM

Receiver Differential Input Impedance

Input termination resistor tolerance

20

KΩ

Internal mode

Receive Return Loss

51 KHz – 102 KHz

RRX

RPD

20

dB

G.703 Internal termination

102 KHz – 2.048 MHz

2.048 MHz – 3.072 MHz

Receive path delay

Single rail

Dual rail

7

2

U.I.

JA disabled

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SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-59 T1/J1 Receiver Electrical Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Test conditions

receiver sensitivity

Short haul with cable loss@772kHz:

Long haul with cable loss@772kHz:

-10

-36

dB

Analog LOS level

Short haul

Long haul

800

mVp-p A LOS level is programmable for Long Haul

dB

-4

-48

Allowable consecutive zeros before LOS

T1.231-1993

I.431

175

1544

LOS reset

12.5

% ones G.775, ETSI 300 233

Receive Intrinsic Jitter

10 Hz - 8 kHz

10 Hz - 40 kHz

8 kHz - 40 kHz

Wide band

JA enabled

0.02

0.025

0.050

U.I.

Input Jitter Tolerance

0.1 Hz – 1 Hz

138.0

28.0

0.4

U.I.

AT&T62411

4.9 Hz – 300 Hz

10 KHz – 100 KHz

ZDM

Receiver Differential Input Impedance

Input termination resistor tolerance

20

KΩ

Internal mode

±1%

RRX

Receive Return Loss

39 KHz – 77 KHz

20

dB

G.703

Internal termination

77 KHz - 1.544 MHz

1.544 MHz – 2.316 MHz

RPD

Receive path delay

Single rail

JA disabled

7

2

U.I.

Dual rail

55

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-60 E1 Transmitter Electrical Characteristics

Symbol

Vo-p

Parameter

Min

Typ

Max

Unit

Output pulse amplitudes

E1, 75Ω load

2.14

2.7

2.37

3.0

2.60

3.3

V

E1, 120Ω load

Vo-s

Zero (space) level

E1, 75Ω load

-0.237

-0.3

0.237

0.3

V

E1, 120Ω load

Transmit amplitude variation with supply

-1

+1

%

mV

ns

Difference between pulse sequences for 17 consecutive pulses (T1.102)

Output Pulse Width at 50% of nominal amplitude

200

256

1.05

Tpw

RTX

232

244

Ratio of the amplitudes of Positive and Negative Pulses at the center of the pulse interval

(G.703)

0.95

Ratio of the width of Positive and Negative Pulses at the center of the pulse interval (G.703)

Transmit Return Loss (G.703)

0.95

1.05

51 KHz – 102 KHz

102 KHz - 2.048 MHz

2.048 MHz – 3.072 MHz

20

15

12

dB

JTXp-p

Td

Intrinsic Transmit Jitter (TCLK is jitter free)

20 Hz – 100 KHz

0.050

U.I.

Transmit path delay (JA is disabled)

Single rail

Dual rail

8.5

4.5

U.I.

Isc

Line short circuit current

100

mA

56

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-61 T1/J1 Transmitter Electrical Characteristics

Symbol

Parameter

Min

2.4

Typ

Max

3.6

Unit

V

Vo-p

Vo-s

Output pulse amplitudes

Zero (space) level

3.0

-0.15

-1

0.15

+1

V

Transmit amplitude variation with supply

%

Difference between pulse sequences for 17 consecutive pulses

(T1.102)

200

mV

TPW

Output Pulse Width at 50% of nominal amplitude

Pulse width variation at the half amplitude (T1.102)

338

350

362

20

ns

Imbalance between Positive and Negative Pulses amplitude

(T1.102)

0.95

1.05

Output power level (T1.102)

@772kHz

@1544kHz (referenced to power at 772kHz)

12.6

-29

17.9

dBm

RTX

Transmit Return Loss

39 KHz – 77 KHz

77 KHz – 1.544 MHz

1.544 MHz – 2.316 MHz

20

15

12

dB

JTXP-P

Intrinsic Transmit Jitter (TCLK is jitter free)

10 Hz – 8 KHz

8 KHz – 40 KHz

10 Hz – 40 KHz

wide band

0.020

0.025

0.050

U.I.p-p

Td

Transmit path delay (JA is disabled)

Single rail

Dual rail

8.5

4.5

U.I.

I_SC

Line short circuit current

100

mA

57

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-62 Transmitter and Receiver Timing Characteristics

Symbol

Parameter

Min

Typ

Max

Unit

MCLK frequency

E1:

T1/J1:

2.048

1.544

MHz

MCLK tolerance

MCLK duty cycle

-100

30

100

70

ppm

%

Transmit path

TCLK frequency

E1:

T1/J1:

2.048

1.544

MHz

TCLK tolerance

-50

10

40

+50

90

ppm

%

TCLK Duty Cycle

t1

t2

Transmit Data Setup Time

Transmit Data Hold Time

ns

Delay time of THZ low to driver high impedance

Delay time of TCLK low to driver high impedance

10

us

75

U.I.

Receive path

Clock recovery capture range ¹

E1

± 80

± 180

50

ppm

%

T1/J1

RCLK duty cycle ²

40

60

RCLK pulse width ²

t4

E1:

T1/J1:

457

607

488

648

519

689

ns

t5

t6

RCLK pulse width low time

E1:

T1/J1:

203

259

244

324

285

389

RCLK pulse width high time

E1:

T1/J1:

203

259

244

324

285

389

ns

Rise/fall time ³

20

t7

t8

Receive Data Setup Time

E1:

T1/J1:

200

244

324

ns

Receive Data Hold Time

E1:

T1/J1:

200

244

324

1.Relative to nominal frequency, MCLK= ± 100 ppm

2.RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement

for E1 per ITU G.823).

3.For all digital outputs. C load = 15pF

58

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

TCLK

t1

t2

TD/TDP

TDN

Figure-20 Transmit System Interface Timing

t4

RCLK

t6

t7

t5

t8

RDP/RD

(RCLK_SEL = 0 software mode)

(RCLKE = 0 hardware mode)

RDN/CV

t7

t8

RDP/RD

(RCLK_SEL = 1 software mode)

(RCLKE = 1 hardware mode)

RDN/CV

Figure-21 Receive System Interface Timing

Table-63 Jitter Tolerance

Jitter Tolerance

Min

Typ

Max

Unit

Standard

E1: 1 Hz

20 Hz – 2.4 KHz

18 KHz – 100 KHz

T1/J1: 1 Hz

37

1.5

0.2

U.I.

G.823

Cable attenuation is 6dB

AT&T 62411

138.0

28.0

0.4

U.I.

4.9 Hz – 300 Hz

10 KHz – 100 KHz

59

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Figure-22 E1 Jitter Tolerance Performance

Figure-23 T1/J1 Jitter Tolerance Performance

60

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-64 Jitter Attenuator Characteristics

Parameter

Min

Typ

Max

Unit

Jitter Transfer Function Corner (-3dB) Frequency

E1, 32/64/128 bits FIFO

JABW = 0:

6.8

0.9

Hz

JABW = 1:

T1/J1, 32/64/128 bits FIFO

JABW = 0:

5

1.25

Hz

JABW = 1:

Jitter Attenuator

E1: (G.736)

@ 3 Hz

@ 40 Hz

-0.5

+19.5

dB

@ 400 Hz

@ 100 kHz

T1/J1: (Per AT&T pub.62411)

@ 1 Hz

0

@ 20 Hz

@ 1 kHz

@ 1.4 kHz

@ 70 kHz

+33.3

40

Jitter Attenuator Latency Delay

32 bits FIFO:

64 bits FIFO:

128 bits FIFO:

16

32

64

U.I.

Input jitter tolerance before FIFO overflow or underflow

32 bits FIFO:

64 bits FIFO:

128 bits FIFO:

28

58

120

U.I.

61

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Figure-24 E1 Jitter Transfer Performance

Figure-25 T1/J1 Jitter Transfer Performance

62

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

7

MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS

7.1 SERIAL INTERFACE TIMING

Table-65 Serial Interface Timing Characteristics

Symbol

t1

Parameter

Min

100

5

Typ

Max

Unit

ns

Comments

SCLK High Time

t2

SCLK Low Time

t3

Active CS to SCLK Setup Time

t4

Last SCLK Hold Time to Inactive CS Time

CS Idle Time

41

0

t5

t6

SDI to SCLK Setup Time

t7

SCLK to SDI Hold Time

82

t10

t11

SCLK to SDO Valid Delay Time

Inactive CS to SDO High Impedance Hold Time

95

90

CS

t4

t5

t3

t6

t1

LSB

3

t2

SCLK

SDI

t7

LSB

Figure-26 Serial Interface Write Timing

MSB

13

1

2

4

5

6

7

8

9

10

11

12

3

14

15

16

SCLK

CS

t4

t10

t11

SDO

0

1

2

4

5

6

7

Figure-27 Serial Interface Read Timing with SCLKE=1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCLK

CS

t4

t10

t11

7

SDO

0

1

2

3

4

5

6

Figure-28 Serial Interface Read Timing with SCLKE=0

63

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

7.2 PARALLEL INTERFACE TIMING

Table-66 Multiplexed Motorola Read Timing Characteristics

Symbol

tRC

Parameter

Min

190

180

Max

Unit

ns

Read Cycle Time

tDW

Valid DS Width

tRWV

tRWH

tASW

tADD

tADS

Delay from DS to Valid Read

R/W to DS Hold Time

15

65

10

0

Valid AS Width

Delay from AS active to DS active

Address to AS Setup Time

5

tADH

tPRD

Address to AS Hold Time

5

DS to Valid Read Data Propagation Delay

Delay from DS inactive to data bus High Impedance

Acknowledgement Delay

175

20

190

15

5

tDAZ

5

tAKD

tAKH

tAKZ

Acknowledgement Hold Time

Acknowledgement Release Time

Recovery Time from Read Cycle

tRecovery

tRC

tDW

DS+CS

tRWH

tRWV

R/W

tADD

tASW

AS

tDAZ

tPRD

Valid address

tADS

Valid Data

READ AD[7:0]

tADH

tAKH

tAKZ

tAKD

ACK

Figure-29 Multiplexed Motorola Read Timing

64

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-67 Multiplexed Motorola Write Timing Characteristics

Symbol

tWC

Parameter

Min

120

100

Max

Unit

ns

Write Cycle Time

tDW

Valid DS Width

tRWV

tRWH

tASW

tADD

tADS

Delay from DS to Valid Write

R/W to DS Hold Time

15

65

10

0

Valid AS Width

Delay from AS active to DS active

Address to AS Setup Time

Address to AS Hold Time

Delay from DS to Valid Write Data

Write Data to DS Hold Time

Acknowledgement Delay

Acknowledgement Hold Time

Acknowledgement Release Time

Recovery Time from Write Cycle

5

tADH

tDV

5

15

tDHW

tAKD

tAKH

tAKZ

65

5

150

15

5

tRecovery

5

tRecovery

tWC

tDW

tRWH

DS+CS

tRWV

R/W

AS

tADD

tASW

tDHW

tDV

Valid address

tADS

Valid Data

Write AD[7:0]

tADH

tAKH

tAKZ

tAKD

ACK

Figure-30 Multiplexed Motorola Write Timing

65

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-68 Multiplexed Intel Read Timing Characteristics

Symbol

tRC

Parameter

Min

190

180

0

Max

Unit

ns

Read Cycle Time

tRDW

tARD

Valid RD Width

Delay from ALE to Valid Read

Valid ALE Width

tALEW

tADS

10

5

Address to ALE Setup Time

tADH

Address to ALE Hold Time

5

tPRD

RD to Valid Read Data Propagation Delay

Delay from RD inactive to data bus High Impedance

Acknowledgement Delay

175

20

190

15

tDAZ

5

tAKD

tAKH

Acknowledgement Hold Time

Acknowledgement Release Time

Recovery Time from Read Cycle

tAKZ

5

tRecovery

tRC

tRDW

RD+CS

tARD

tALEW

ALE

tDAZ

tPRD

Valid address

tADS

Valid Data

READ AD[7:0]

tADH

tAKH

tAKZ

tAKD

RDY

Figure-31 Multiplexed Intel Read Timing

66

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

Table-69 Multiplexed Intel Write Timing Characteristics

Symbol

tWC

Parameter

Min

120

100

10

0

Max

Unit

ns

Write Cycle Time

Valid WR Width

Valid ALE Width

tWRW

tALEW

tAWD

tADS

Delay from ALE to Valid Write

Address to ALE Setup Time

Address to ALE Hold Time

5

tADH

5

tDV

Delay from WR to Valid Write Data

Write Data to WR Hold Time

Acknowledgement Delay

15

tDHW

tAKD

65

5

150

15

5

tAKH

Acknowledgement Hold Time

Acknowledgement Release Time

Recovery Time from Write Cycle

tAKZ

tRecovery

5

tRecovery

tWC

tWRW

WR+CS

tAWD

tALEW

ALE

tDHW

tDV

Valid address

tADS

Valid Data

Write AD[7:0]

tADH

tAKH

tAKZ

tAKD

RDY

Figure-32 Multiplexed Intel Write Timing

67

INDUSTRIAL

TEMPERATURE RANGES

SINGLE CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT

ORDERING INFORMATION

XXXXXXX

Device Type

XX

X

Process/

Temperature

Range

Blank

Industrial (-40 °C to +85 °C)

Thin Quad Flatpack (TQFP, PP44)

Long Haul/Short Haul LIU

PP

82V2081

DATASHEET DOCUMENT HISTORY

08/26/2003 pgs. 17, 18, 19, 20, 29, 30, 41, 55, 56

07/19/2004 pgs. 30, 56, 57

02/11/2009 pg. 68 removed IDT from orderable part number

CORPORATE HEADQUARTERS

for SALES:

for Tech Support:

2975 Stender Way

Santa Clara, CA 95054

800-345-7015 or 408-727-6116

fax: 408-492-8674

408-330-1753

email:TELECOMhelp@idt.com

www.idt.com*

To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

68


型号：	82V2081PPG8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	PCM Transceiver, 1-Func, PQFP44, TQFP-44 PC 电信电信集成电路
文件：	总68页 (文件大小：826K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

82V2081PPG8 [IDT]

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