8344AYI-01T [IDT]
Low Skew Clock Driver, CMOS, PQFP48;
| 型号： | 8344AYI-01T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, CMOS, PQFP48 驱动 逻辑集成电路 |
| 文件： | 总13页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
LOW SKEW, 1-TO-24 DIFFERENTIAL-
TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8344I-01
GENERAL DESCRIPTION
FEATURES
The ICS8344I-01 is a low voltage, low skew
• Twenty-four LVCMOS/LVTTL outputs,
7Ω typical output impedance
ICS
HiPerClockS™
fanout buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
• Two selectable differential CLKx, nCLKx inputs
IDT. The ICS8344I-01 has two selectable clock in-
puts. The CLKx, nCLKx pairs can accept most
• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
standard differential input levels. The ICS8344I-01 is designed
to translate any differential signal level to LVCMOS/LVTTL lev-
els. The low impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmission lines.
The effective fanout can be increased to 48 by utilizing the
ability of the outputs to drive two series terminated lines.
Redundant clock applications can make use of the dual clock
inputs which also facilitate board level testing. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin. The outputs are driven low when disabled.
The ICS8344I-01 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
• Maximum output frequency: 200MHz
• Translates any single ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
• Synchronous clock enable
• Output skew: 250ps (maximum)
• Part-to-part skew: 1ns (maximum)
• Bank skew: 125ps (maximum)
• Propagation delay: 5.25ns (maximum)
• Output supply modes:
Core/Output
3.3V/3.3V
Guaranteed output and part-to-part skew characteristics make
the ICS8344I-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
2.5V/2.5V
3.3V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK0
48 47 46 45 44 43 42 41 40 39 38 37
0
nCLK0
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
1
36
35
34
33
32
31
30
29
28
27
26
25
Q7
2
Q6
CLK1
nCLK1
1
3
VDDO
GND
Q5
Q0:Q7
4
ICS8344I-01
5
48-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
6
Q4
Q8:Q15
Q16:Q23
7
Q3
8
Q2
9
VDDO
GND
Q1
Top View
10
11
12
Q0
LE
nD
13 14 15 16 17 18 19 20 21 22 23 24
Q
CLK_EN
OE
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS8344I-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 5, 6
7, 8, 11, 12
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
Single-ended outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
3, 9, 28,
34, 39, 45
4, 10, 14,18,
27, 33, 40, 46
VDDO
Power
Power
Output supply pins.
GND
Power supply ground.
Clock select input. When HIGH, selects CLK1, nCLK inputs,
13
CLK_SEL
Input
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levelss.
15, 19
16
VDD
Power
Input
Input
Input
Input
Power supply pins.
nCLK1
CLK1
nCLK0
CLK0
Pullup
Pulldown Non-inverting differential clock input.
Pullup Inverting differential clock input.
Inverting differential clock input.
17
20
21
Pulldown Non-inverting differential clock input.
Synchronizing control for enabling and disabling clock
Pullup
22
CLK_EN
Input
outputs. LVCMOS / LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs
Q0:Q23. LVCMOS / LVTTL interface levels.
23
24
OE
nc
Input
Unused
Output
Pullup
No connect.
25, 26, 29, 30
31, 32, 35, 36
37, 38, 41, 42
Q0, Q1, Q2, Q3
Q4, Q5, Q6, Q7
Q8, Q9, Q10, Q11
Single-ended outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Single-ended outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
43, 44, 47, 48 Q12, Q13, Q14, Q15
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
TBD
pF
RPULLUP
Input Pullup Resistor
51
51
7
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
5
12
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PRELIMINARY
TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Banks 1, 2, 3
Inputs
Outputs
Q0:Q23
OE
0
CLK_EN
X
0
1
Hi-Z
1
Disabled in logic LOW state. NOTE 1
Enabled. NOTE 1
1
NOTE 1: The clock enable and disable function is synchronous to the falling
edge of the selected reference clock.
TABLE 3B. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
CLK0, nCLK0
Selected
CLK1, nCLK1
De-selected
Selected
0
1
De-selected
TABLE 3C. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Q0:Q23
LOW
Input to Output Mode
Polarity
OE
1
CLK0, CLK1
nCLK0, nCLK1
0
1
Differential to Single Ended
Differential to Single Ended
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
0
HIGH
LOW
1
0
Biased; NOTE 1
1
1
Biased; NOTE 1
HIGH
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
0
1
1
Inverting
NOTE 1: Please refer to the Application Information section on page 8, Figure 1, which discusses Wiring the Differential
Input to Accept Single-Ended Levels.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, OR VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ;
TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
3.135
2.375
3.135
2.375
3.3
2.5
3.3
2.5
3.465
2.625
3.465
2.625
70
V
V
VDD
Power Supply Voltage
V
VDDO
Output Supply Voltage
V
IDD
Power Supply Current
Output Supply Current
mA
mA
IDDO
25
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, OR VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ;
TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_SEL,
CLK_EN, OE
CLK_SEL,
CLK_EN, OE
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
CLK_EN, OE
CLK_SEL
VDD = VIN = 3.465V or 2.625V
5
µA
µA
µA
µA
V
IIH
V
DD = VIN = 3.465V or 2.625V
150
CLK_EN, OE
CLK_SEL
V
DD = 3.465 or 2.625V, VIN = 0V
-150
-5
IIL
Input Low Current
Output High Voltage
Output Low Voltage
VDD = 3.465 or 2.625V, VIN = 0V
VDDO = 3.135V, IOH = -36mA
VDDO = 2.375V, IOH = -27mA
VDDO = 3.135V, IOL = 36mA
VDDO = 2.375V, IOL = 27mA
2.6
1.8
VOH
VOL
V
0.5
0.5
V
V
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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PRELIMINARY
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, OR VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ;
TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
nCLK0, nCLK1
CLK0, CLK1
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
5
µA
µA
µA
µA
V
Input
IIH
High Current
150
nCLK0, nCLK1 VDD = 3.465V or 2.625V, VIN = 0V
CLK0, CLK1 DD = 3.465V or 2.625V, VIN = 0V
-150
-5
Input
IIL
Low Current
V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage:
NOTE 1, 2
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, OR VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ;
TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
f ≤ 200MHz
Minimum Typical Maximum Units
200
5.25
125
200
175
250
1
MHz
ns
ps
ps
ps
ps
ns
ps
ps
ꢀ
Propagation Delay, NOTE 1
Q0:Q7
2.5
Bank Skew;
NOTE 2, 6
tsk(b)
tsk(o)
Q8:Q15
Measured on the rising edge of VDDO/2
Q16:Q23
Output Skew; NOTE 3, 6
Measured on the rising edge of VDDO/2
tsk(pp) Part-to-Part Skew; NOTE 4, 6 Measured on the rising edge of VDDO/2
tR
Output Rise Time; NOTE 5
Output Fall Time; NOTE 5
Output Duty Cycle
30ꢀ to 70ꢀ
30ꢀ to 70ꢀ
f ≤ 200MHz
f = 10MHz
f = 10MHz
200
200
40ꢀ
800
800
60ꢀ
5
tF
odc
tEN
tDIS
Output Enable Time; NOTE 5
Output Disable TIme; NOTE 5
ns
ns
4
All parameters measured at 200MHz and VPPtyp unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS8344I-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2.05V 5ꢀ
1.25V 5ꢀ
SCOPE
VDD
VDDO
,
SCOPE
VDD
Qx
VDDO
Qx
LVCMOS
GND
GND
LVCMOS
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
VDD
SCOPE
nCLK0,
nCLK1
VDD
VDDO
,
VPP
VCMR
Cross Points
Qx
LVCMOS
GND
CLK0,
CLK1
GND
-1.25V 5ꢀ
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
VDDO
VDDO
Qx
2
Qx
2
PART 2
VDDO
VDDO
Qy
Qy
2
2
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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PRELIMINARY
nCLK0,
nCLK1
VDDO
2
CLK0,
CLK1
Q0:Q23
tPW
tPERIOD
Q0:Q23
tPD
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
80ꢀ
tF
80ꢀ
20ꢀ
20ꢀ
Clock
Outputs
tR
OUTPUT RISE/FALL TIME
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PRELIMINARY
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias DcDircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUTS
CLK/nCLK INPUTS
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
All unused LVCMOS output can be left floating. There should be
no trace attached.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS8344I-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PRELIMINARY
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 2A to 2F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 2A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
HIPERCLOCKS LVHSTL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
nCLK
nCLK
HiPerClockS
HiPerClockS
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
FIGURE 2F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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ICS8344I-01
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 6. θ VS. AIR FLOW TABLE FOR 48 LEAD LQFP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8344I-01 is: 1503
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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PRELIMINARY
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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PRELIMINARY
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8344AYI-01
Marking
Package
Shipping Packaging
tray
Temperature
ICS8344AYI-01
ICS8344AYI-01
ICS8344AI01L
ICS8344AI01L
48 Lead LQFP
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS8344AYI-01T
ICS8344AYI-01LF
ICS8344AYI-01LFT
48 Lead LQFP
1000 tape & reel
tray
48 lead "Lead-Free" LQFP
48 lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
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800-345-7015
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Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
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相关型号：
8344BYI
Low Skew Clock Driver, 8344 Series, 24 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48
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8344BYIT
Low Skew Clock Driver, 8344 Series, 24 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48
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8345-B
In the business fields Communication and Transport: power supplies, switchgear, instrumentation and process control engineering
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8345-B01A-P0
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8345-B01A-P3
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8345-B01A-R0
In the business fields Communication and Transport: power supplies, switchgear, instrumentation and process control engineering
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8345-B01A-R3
In the business fields Communication and Transport: power supplies, switchgear, instrumentation and process control engineering
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8345-B01A-U0
In the business fields Communication and Transport: power supplies, switchgear, instrumentation and process control engineering
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