83948I_16 [IDT]
Low Skew, 1-to-12 Differential-to- LVCMOS/LVTTL Fanout Buffer;
| 型号： | 83948I_16 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-12 Differential-to- LVCMOS/LVTTL Fanout Buffer |
| 文件： | 总13页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
83948I
Low Skew, 1-to-12 Differential-to-
LVCMOS/LVTTL Fanout Buffer
Datasheet
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
General Description
Features
The 83948I is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL
Fanout Buffer and a member of the family of High Performance
Clock Solutions from IDT. The 83948I has two selectable clock
inputs. The CLK, nCLK pair can accept most standard differential
input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL
input levels. The low impedance LVCMOS/LVTTL outputs are
designed to drive 50 series or parallel terminated transmission
lines. The effective fanout can be increased from 12 to 24 by
utilizing the ability of the outputs to drive two series terminated
lines.
• Twelve LVCMOS/LVTTL outputs
• Selectable differential CLK/nCLK or LVCMOS/LVTTL clock
input
• CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
• Maximum output frequency: 250MHz
• Output skew: 350ps (maximum)
• Part-to-part skew: 1.5ns (maximum)
• 3.3V core, 3.3V output
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
• For drop in replacement part use 83948i-147
The 83948I is characterized at full 3.3V core/3.3V output.
Guaranteed output and part-to-part skew characteristics make the
83948I ideal for those clock distribution applications demanding
well defined performance and repeatability.
Pin Assignment
Pullup
CLK_EN
D
Q
32 31 30 29 28 27 26 25
Pullup
LVCMOS_CLK
1
1
2
3
4
5
6
7
8
CLK_SEL
GND
24
23
22
21
20
Q0
Pullup
CLK
nCLK
LVCMOS_CLK
CLK
Q4
0
Pulldown
Q1
VDDO
Q5
Pullup
CLK_SEL
Q2
nCLK
CLK_EN
GND
Q3
OE
VDD
Q6
Block Diagram
19
18
17
Q4
VDDO
Q7
GND
Q5
9
10 11 12 13 14 15 16
Q6
Q7
83948I
Q8
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Q9
Y Package
Top View
Q10
Q11
Pullup
OE
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Table 1. Pin Descriptions
Number
Name
Type
Description
Clock select input. When HIGH, selects LVCMOS_CLK input.
1
CLK_SEL
Input
Pullup
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
Single-ended clock input. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
2
3
4
5
6
7
LVCMOS_CLK
CLK
Input
Input
Input
Input
Input
Power
Pullup
Pullup
nCLK
Pulldown Inverting differential clock input.
CLK_EN
OE
Pullup
Pullup
Clock enable pin. LVCMOS/LVTTL interface levels.
Output enable pin. LVCMOS/LVTTL interface levels.
Positive supply pin.
VDD
8, 12, 16,
20, 24, 28, 32
GND
Power
Output
Power
Power supply ground.
9, 11, 13,
15, 17, 19,
21, 23, 25,
27, 29, 31
Q11, Q10, Q9,
Q8, Q7, Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
10, 14, 18,
22, 26, 30
VDDO
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
k
RPULLDOWN Input Pulldown Resistor
k
Power Dissipation Capacitance
(per output)
CPD
25
7
pF
ROUT
Output Impedance
Function Tables
Table 3A. Clock Select Function Table
Control Input
Clock
CLK_SEL
CLK/nCLK
Selected
LVCMOS_CLK
0
1
De-selected
Selected
De-selected
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Table 3B. Clock Input Function Table
Inputs
Outputs
Q[0:11]
LOW
CLK_SEL LVCMOS_CLK
CLK
nCLK
Input to Output Mode
Polarity
0
0
0
0
0
0
1
1
–
–
–
–
–
–
0
1
0
1
Differential to Single-Ended
Differential to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
0
1
–
–
Biased; NOTE 1
Inverting
–
–
LOW
Non-Inverting
Non-Inverting
HIGH
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
47.9C/W (0 lfpm)
-65C to 150C
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
Units
V
VDD
VDDO
IDD
Positive Supply Voltage
3.6
3.6
55
Output Supply Voltage
Power Supply Current
3.0
3.3
V
mA
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Table 4B. DC Characteristics, VDD = VDDO = 3.3V 0.3V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2
Typical
Maximum
Units
V
VIH
Input High Voltage
VDD + 0.3
0.8
VIL
Input Low Voltage
-0.3
V
VPP
VCMR
IIN
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Input Current
0.15
1.3
V
GND + 0.5
VDD – 0.85
100
V
µA
V
VOH
VOL
Output High Voltage
IOH = -20mA
IOL = 20mA
2.5
Output Low Voltage
0.4
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = VDDO = 3.3V 0.3V, TA = -40°C to 85°C
Parameter Symbol
fMAX Output Frequency
Test Conditions
Minimum
Typical
Maximum
Units
250
MHz
CLK/nCLK;
NOTE 1A
ƒ 150MHz
ƒ 150MHz
2.25
2
3.75
4
ns
ns
ps
tPD
Propagation Delay
LVCMOS_CLK;
NOTE 1B
Measured on
Rising Edge @ VDDO/2
tsk(o)
Output Skew; NOTE 2, 6
350
CLK/nCLK
LVCMOS_CLK
1.5
ns
ns
ns
ps
ns
ns
Part-to-Part Skew;
NOTE 3, 6
Measured on
Rising Edge @ VDDO/2
tsk(pp)
2
tR / tF
tPW
tPZL, PZH
tPLZ, PHZ
Output Rise/Fall Time
Output Pulse Width
0.8V to 2V
0.2
1.0
ƒ < 150MHz
tCycle/2 - 800
tCycle/2 + 800
t
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
CLK_EN to
11
11
t
1
0
1
1
ns
ns
ns
ns
Clock Enable
CLK/nCLK
tS
Setup Time;
CLK_EN to
NOTE 5
LVCMOS_CLK
CLK/nCLK to
CLK_EN
Clock Enable
Hold Time;
NOTE 5
tH
LVCMOS_CLK to
CLK_EN
NOTE 1A: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 1B: Measured from VDD/2 or crosspoint of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Parameter Measurement Information
1.65V 0.15V
V
DD
SCOPE
V
V
nCLK
CLK
DD,
DDO
VPP
VCMR
Cross Points
Qx
GND
GND
-1.65V 0.15V
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
Differential Input Level
Part 1
VDDO
VDDO
2
Qx
Qx
Qy
2
Part 2
VDDO
2
VDDO
2
Qy
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
VDDO
VDDO
2
VDDO
2
2V
2V
2
Q0:Q11
tPW
0.8V
0.8V
Q0:Q11
tPERIOD
tR
tF
tPW
tPERIOD
odc =
Output Rise/Fall Time
Output Pulse Width
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Parameter Measurement Information, continued
VDD
2
LVCMOS_CLK
nCLK
CLK
VDDO
2
Q0:Q11
➤
tPD
➤
Propagation Delay
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
VDD
R1
1K
Single Ended Clock Input
R2/R1 = 0.609.
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 1. Single-Ended Signal Driving Differential Input
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVCMOS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to
ground.
All unused LVCMOS output can be left floating. There should be
no trace attached.
CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k resistor can be used.
©2016 Integrated Device Technology, Inc
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May 19, 2016
83948I Datasheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 2A to 2F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 2A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
Figure 2A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 2B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
*R3
*R4
Zo = 60Ω
Zo = 60Ω
CLK
CLK
nCLK
nCLK
Differential
Input
Differential
Input
SSTL
HCSL
R1
R2
120Ω
120Ω
Figure 2E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 2F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Reliability Information
Table 6. JA vs. Air Flow Table for a 32 Lead LQFP
JA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
Transistor Count
The transistor count for 83948I is: 1040
Pin compatible with the MPC948/948L
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Package Outline and Package Dimensions
Package Outline - Y Suffix for 32 Lead LQFP
Table 7. Package Dimensions for 32 Lead LQFP
JEDEC Variation: ABC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
0.15
1.45
0.45
0.20
A1
0.05
1.35
0.30
0.09
0.10
1.40
0.37
A2
b
c
D & E
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
D1 & E1
D2 & E2
e
L
0.45
0°
0.75
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
©2016 Integrated Device Technology, Inc
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83948I Datasheet
Ordering Information
Table 8. Ordering Information
Part/Order Number
83948AYILF
83948AYILFT
Marking
ICS83948AYIL
ICS83948AYI
Package
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
Tape & Reel
©2016 Integrated Device Technology, Inc
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May 19, 2016
83948I Datasheet
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T5
4
AC Characteristics table - tLZ, tHZ row changed symbol to read tPLZ, tPHZ and
changed Parameter to read Output Enable Time.
Added rows: tS ""Clock Enable Setup Time"" and tH ""Clock Enable Hold
Time"".
B
5/20/02
T5
4
AC Characteristics table, tS and tH rows - replaced SYNC_OE with CLK_EN.
Added an extra note to Propagation Delay row.
B
B
B
6/26/02
8/8/02
AC Characteristics table, fMAX row corrected typo error of 150MHz to
250MHz.
T5
T5
4
4
AC Characteristics table - tPW row, added f< 150MHz for tPW Test Conditions.
11/11/02
1
2
6
9
Features Section - added Lead-Free bullet.
T2
T8
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
Added Recommendations for Unused Output Pins.
Ordering Information Table - added Lead-Free part number, marking and
note.
C
12/15/05
8
11
Added Differential Clock Input Interface Section.
Ordering Information Table - corrected Temperature column.
Updated datasheet format.
C
C
T8
T8
3/6/08
11
1
Removed leaded orderable parts from Ordering Information table
11/14/12
General Description - Removed ICS Chip and HiPerClockS.
Features Section - Removed reference to leaded packages
Removed ICS from the Part Number.
Ordering Information - Removed ICS from the Part/Order Number. Removed
1000 from the Tape & Reel. Removed the LF note from below the table.
Updated Header and Footer.
C
C
12/16/15
5/19/16
T8
11
Product Discontinuation Notice - Last time buy expires May 6, 2017.
PDN CQ-16-01
©2016 Integrated Device Technology, Inc
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May 19, 2016
83948I Datasheet
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Sales
Tech Support
www.idt.com/go/support
1-800-345-7015 or 408-284-8200
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and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
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For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.
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