83PN187I [IDT]
Programmable FemtoClock NG LVPECL Oscillator Replacement;
| 型号： | 83PN187I |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Programmable FemtoClock NG LVPECL Oscillator Replacement |
| 文件： | 总22页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Programmable FemtoClock® NG
LVPECL Oscillator Replacement
83PN187I
Data Sheet
General Description
Features
The 83PN187I is a programmable LVPECL synthesizer that is
“forward” footprint compatible with standard 5mm x 7mm oscillators.
The device uses IDT’s fourth generation FemtoClock® NG
technology for an optimum of high clock frequency and low phase
noise performance. Forward footprint compatibility means that a
board designed to accommodate the crystal oscillator interface and
the optional control pins is also fully compatible with a canned
oscillator footprint - the canned oscillator will drop onto the
10-VFQFN footprint for second sourcing purposes. This capability
provides designers with programability and lead time advantages of
silicon/crystal based solutions while maintaining compatibility with
industry standard 5mm x 7mm oscillator footprints for ease of supply
chain management. Oscillator-level performance is maintained with
IDT’s 4th Generation FemtoClock® NG PLL technology, which
delivers sub 0.5ps rms phase jitter.
• Fourth Generation FemtoClock® Next Generation (NG)
technology
• Footprint compatible with 5mm x 7mm differential oscillators
• One differential LVPECL output pair
• Crystal oscillator interface can also be overdriven by a
single-ended reference clock
• Output frequency range: 125MHz –187.5MHz
• Crystal/input frequency: 25MHz, 12pF parallel resonant crystal
• VCO range: 2GHz – 2.5GHz
• Cycle-to-cycle jitter: 10ps (maximum), 3.3V 5%
• RMS phase jitter @ 156.25MHz, 12kHz – 20MHz:
0.339ps (typical)
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
The 83PN187I defaults to 150MHz using a 25MHz crystal with 2
programming pins floating (pulled down/pulled up with internal pullup
or pulldown resistors) but can also be set to 4 different frequency
multiplier settings to support a wide variety of applications. The
below table shows some of the more common application settings.
Common Applications and Settings
FSEL[1:0]
XTAL (MHz)
Output Frequency (MHz)
Application(s)
Pin Assignment
00
01
10
25
25
25
156.25
187.5
125
XAUI, 10GigE
8Gig Fibre Channel
Ethernet
SAS, Embedded
Processor
10
9
11 (default)
25
150
1
2
3
VCC
nQ
OE
RESERVED
VEE
8
7
6
Block Diagram
Q
4
5
Pullup
OE
XTAL_IN
PFD
&
FemtoClock® NG
VCO
Q
nQ
OSC
÷N
XTAL_OUT
83PN187I
10-Lead VFQFN
÷M
5mm x 7mm x 1mm package body
K Package
Top View
Pullup
Pullup
FSEL0
FSEL1
Control
Logic
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Table 1. Pin Descriptions
Number
Name
OE
Type
Description
1
2
3
Input
Pullup
Output enable. LVCMOS/LVTTL interface levels.
Reserved pin. Do not connect.
Negative supply pin.
RESERVED
VEE
Reserve
Power
4,
5
XTAL_OUT
XTAL_IN
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. This
oscillator interface can also be driven by a single-ended reference clock.
Input
6, 7
8
Q, nQ
VCC
Output
Power
Differential output pair. LVPECL interface levels.
Power supply pin.
Output divider control inputs. Sets the output divider value to one of four values.
See Table 3. LVCMOS/LVTTL interface levels.
9
FSEL0
FSEL1
Input
Input
Pullup
Pullup
Output divider control inputs. Sets the output divider value to one of four values.
See Table 3. LVCMOS/LVTTL interface levels
10
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
k
Function Table
Table 3. Divider Function Table
FSEL[1:0]
0 0
M Value
÷100
÷90
N Value
÷16
0 1
÷12
1 0
÷80
÷16
1 1 (default)
÷84
÷14
©2016 Integrated Device Technology, Inc
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83PN187I Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
3.63V
Inputs, VI
XTAL_IN
Other Inputs
0V to 2V
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, JA
39.2C/W (0 mps)
-65C to 150C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
VCC Power Supply Voltage
IEE Power Supply Current
Test Conditions
Minimum
Typical
Maximum
3.465
Units
V
3.135
3.3
131
mA
Table 4B. Power Supply DC Characteristics, VCC = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
VCC Power Supply Voltage
IEE Power Supply Current
Test Conditions
Minimum
Typical
Maximum
2.625
Units
V
2.375
2.5
124
mA
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VCC = 3.465V
VCC = 2.625V
VCC = 3.465V
VCC = 2.625V
Minimum
Typical
Maximum
VCC + 0.3
VCC + 0.3
0.8
Units
2
V
V
V
V
VIH
Input High Voltage
1.7
-0.3
-0.3
VIL
Input Low Voltage
0.7
Input
High Current
OE,
FSEL[1:0]
IIH
VCC = VIN = 3.465V or 2.625V
5
µA
µA
Input
Low Current
OE,
FSEL[1:0]
IIL
VCC = 3.465V or 2.625V, VIN = 0V
-150
©2016 Integrated Device Technology, Inc
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83PN187I Data Sheet
Table 4D. LVPECL DC Characteristics, VCC = 3.3V 5% or 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC – 1.3
VCC – 2.0
0.6
Typical
Maximum
VCC – 0.8
VCC – 1.6
1.0
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
V
VOL
VSWING
NOTE 1: Outputs termination with 50 to VCC – 2V.
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
MHz
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
©2016 Integrated Device Technology, Inc
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83PN187I Data Sheet
AC Electrical Characteristics
Table 6A. AC Characteristics, Vcc = 3.3V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
1250
187.5
MHz
156.25MHz,
Integration Range: 12kHz – 20MHz
0.339
0.321
0.309
0.315
0.5
0.5
0.5
0.5
ps
ps
ps
ps
187.5MHz,
Integration Range: 12kHz – 20MHz
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
125MHz,
Integration Range: 12kHz – 20MHz
150MHz,
Integration Range: 12kHz – 20MHz
tjit(cc)
tR / tF
odc
Cycle-to-Cycle Jitter; NOTE 2
Output Rise/Fall Time
Output Duty Cycle
10
350
51
ps
ps
%
20% to 80%
100
49
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to the Phase Noise plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Table 6B. AC Characteristics, Vcc = 2.5V 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
125
187.5
MHz
156.25MHz,
Integration Range: 12kHz – 20MHz
0.347
0.326
0.315
0.317
0.5
0.5
0.5
0.5
ps
ps
ps
ps
187.5MHz,
Integration Range: 12kHz – 20MHz
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
125MHz,
Integration Range: 12kHz – 20MHz
150MHz,
Integration Range: 12kHz – 20MHz
tjit(cc)
tR / tF
odc
Cycle-to-Cycle Jitter; NOTE 2
Output Rise/Fall Time
Output Duty Cycle
20
350
51
ps
ps
%
20% to 80%
100
49
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Refer to the Phase Noise plots.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Typical Phase Noise at 125MHz (3.3V core, 3.3V output)
Offset Frequency (Hz)
Typical Phase Noise at 150MHz (3.3V core, 3.3V output)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Typical Phase Noise at 156.25MHz (3.3V core, 3.3V output)
Offset Frequency (Hz)
Typical Phase Noise at 187.5MHz (3.3V core, 3.3V output)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Parameter Measurement Information
2V
2V
SCOPE
SCOPE
Qx
V
CC
V
Qx
CC
nQx
nQx
VEE
VEE
-1.3V 0.165V
-0.5V 0.125V
2.5V LVPECL Output Load AC Test Circuit
3.3V LVPECL Output Load AC Test Circuit
nQ
Q
RMS Phase Jitter
Output Duty Cycle/Pulse Width/Period
nQ
Q
nQ
Q
tcycle n
tcycle n+1
tjit(cc) = tcycle n – tcycle n+1
|
|
1000 Cycles
Cycle-to-Cycle Jitter
Output Rise/Fall Time
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Application Information
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 1. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 1. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Crystal Input Interface
The 83PN187I has been characterized with 12pF parallel resonant
crystals. The capacitor values shown in Figure 2A below were
determined using a 25MHz, 12pF parallel resonant crystal and were
chosen to minimize the ppm error. Other parallel resonant crystal’s
values can be used. For example, a crystal with a CL = 18pF can be
used, but would require the tuning capacitors to be adjusted.
XTAL_IN
XTAL_IN
C1
16pF
C1
4pF
X1
18pF Parallel Crystal
X1
12pF Parallel Crystal
XTAL_OUT
XTAL_OUT
C2
16pF
C2
4pF
Figure 2B. Crystal Input Interface, using 18pF crystal
Figure 2A. Crystal Input Interface, using 12pF crystal
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and making R2 50. By overdriving the crystal oscillator, the
device will be functional, but note, the device performance is
guaranteed by using a quartz crystal.
3.3V
3.3V
R1
100
C1
Ro
~ 7 Ohm
Zo = 50 Ohm
XTAL_I N
RS
43
0.1uF
R2
100
Driver_LVCMOS
XTAL_OU T
Crystal Input Interf ace
Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
0.1uF
R1
50
Zo = 50 Ohm
XTAL_OUT
LVPECL
Cry stal Input Interface
R2
50
R3
50
Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Termination for 3.3V LVPECL Outputs
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be used
for functionality. These outputs are designed to drive 50
3.3V
R3
125
R4
125
3.3V
3.3V
Zo = 50
+
_
Input
Zo = 50
R1
84
R2
84
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Termination for 2.5V LVPECL Outputs
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 5B can be eliminated and the termination is
shown in Figure 5C.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
50Ω
R1
250Ω
R3
250Ω
+
50Ω
50Ω
50Ω
+
–
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
2.5V LVPECL Driver
R2
62.5Ω
R4
62.5Ω
R3
18Ω
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
50Ω
R2
50Ω
Figure 5C. 2.5V LVPECL Driver Termination Example
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 83PN187I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 83PN187I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 131mA = 453.915mW
Power (outputs)MAX = 32mW/Loaded Output pair
Total Power_MAX (3.3V, with all outputs switching) = 453.915mW + 32mW = 485.915mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 39.2°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.486W * 39.2°C/W = 104.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 10 Lead VFQFN, Forced Convection
JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
39.2°C/W
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pair.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.8V
(VCC_MAX – VOH_MAX) = 0.8V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V
(VCC_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.8V)/50] * 0.8V = 19.2mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.82mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Reliability Information
Table 8. JA vs. Air Flow Table for a 10 Lead VFQFN
JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
39.2°C/W
Transistor Count
The transistor count for 83PN187I is: 24,932
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Package Outline
Package Outline - K Suffix for 10-Lead VFQFN
D
B
4
INDEX AREA
(D/ 2 xE/ 2)
aaa
C 2x
9
TOP VIEW
ccc
C
C
C
SEATING
PLANE
8
SIDE VIEW
e1
0.08
NX L2
7
NX b1
bbb
C
A
B
7
NX b2
bbb
C
A
4
B
INDEX AREA
(D/ 2 xE/ 2)
PIN# 1 ID
D2
BOTTOM VIEW
FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.
ORIGINATOR
ZAHRUL
DWG. NO : PKGML00305
DRAFT
MLP QUAD
ENGINEERING MANAGER
TOOLING MANAGER
TECH. SALES MANAGER
DATE
PACKAGE OUTLINE
1
ARAVEN
KANDA
5.00x7.00 MLPQ 10LD
1.00/ 2.54 Pit ch
2007- APR- 18
Page 1 Of 4
©2016 Integrated Device Technology, Inc
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83PN187I Data Sheet
Package Outline, continued
Package Outline - K Suffix for 10-Lead VFQFN
COMMON DIMENSION
TOLERANCE OF FORM AND POSITION
0.15
aaa
bbb
ccc
0.10
0.10
COMMON DIMENSION
V : Very t hin
SYMBOL
MIN
0.80
0.00
NOM
0.90
0.02
MAX
1.00
A
A1
0.05
NOTES
1, 2
1, 2
1, 2
Summary Table
Body
Very Very Thin
Lead
Lead
Count
10
Pin # 1 ID
R0.30
Variat ion
Pit ch (e1 & e2)
1.00/ 2.54
Size
5.00X7.00
VNJR- 1
FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.
ORIGINATOR
ZAHRUL
DWG. NO : PKGML00305
DRAFT
MLP QUAD
ENGINEERING MANAGER
TOOLING MANAGER
TECH. SALES MANAGER
DATE
PACKAGE OUTLINE
5.00x7.00 MLPQ 10LD
1.00/ 2.54 Pit ch
1
ARAVEN
KANDA
2007- APR- 18
PAGE: 2 of
4
©2016 Integrated Device Technology, Inc
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Revision A March 4, 2016
83PN187I Data Sheet
Package Outline, continued
Package Outline - K Suffix for 10-Lead VFQFN
NOTE:
1. Dimensioning and t olerancing conf orm t o ASME Y14.5M- 1994.
2. All dimensions are in millimet ers, angles are in degrees(°).
3. N is t he t ot al number of t erminals.
4. The locat ion of t he t erminal # 1 ident if ier and t erminal numbering convent ion
conf orms t o JEDEC publicat ion 95 SPP- 002.
5. ND and NE ref er t o t he number of t erminals on each D and E side respect ively.
6. NJR ref ers t o NON JEDEC REGISTERED
7. Dimension b applies t o met allized t erminal and is measured bet ween 0.10mm
and 0.30mm f rom t he t erminal t ip. If t he t erminal has t he opt ional radius
on t he ot her end of t he t erminal, t he dimension b should not be measured
in t hat radius area.
8. Coplanarit y applies t o t he t erminals and all ot her bot t om surf ace met allizat ion.
9. Drawing shown are f or illust rat ion only.
FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.
ORIGINATOR
ZAHRUL
DWG. NO : PKGML00305
DRAFT
MLP QUAD
ENGINEERING MANAGER
TOOLING MANAGER
TECH. SALES MANAGER
DATE
PACKAGE OUTLINE
1
ARAVEN
KANDA
5.00x7.00 MLPQ 10LD
1.00/ 2.54 Pit ch
2007- APR- 18
PAGE: 3 of
4
©2016 Integrated Device Technology, Inc
18
Revision A March 4, 2016
83PN187I Data Sheet
Package Outline, continued
Package Outline - K Suffix for 10-Lead VFQFN
VNJR- 1
D BSC
E BSC
5.00
7.00
0.35
0.40
0.45
1.35
1.40
1.45
1.55
1.70
1.80
3.55
3.70
3.80
0.45
0.55
0.65
1.00
1.10
1.20
10
MIN
b1
b2
D2
E2
L1
L2
NOM
MAX
MIN
NOM
MAX
MIN
NOM
MAX
MIN
NOM
MAX
MIN
NOM
MAX
MIN
NOM
MAX
N
ND
NE
2
3
NOTES
-
PAD DESIGN
-
FOR REVISION UPDATE PLEASE REFER TO HISTORY OF CHANGES.
ORIGINATOR
ZAHRUL
DWG. NO : PKGML00305
DRAFT
MLP QUAD
ENGINEERING MANAGER
TOOLING MANAGER
TECH. SALES MANAGER
DATE
PACKAGE OUTLINE
1
ARAVEN
KANDA
5.00x7.00 MLPQ 10LD
1.00/ 2.54 Pit ch
2007- APR- 18
PAGE: 4 of
4
©2016 Integrated Device Technology, Inc
19
Revision A March 4, 2016
83PN187I Data Sheet
Ordering Information
Table 9. Ordering Information
Part/Order Number
83PN187DKILF
Marking
Package
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
ICS3PN187DIL
ICS3PN187DIL
“Lead-Free” 10 Lead VFQFN
“Lead-Free” 10 Lead VFQFN
83PN187DKILFT
Tape & Reel
©2016 Integrated Device Technology, Inc
20
Revision A March 4, 2016
83PN187I Data Sheet
Revision History Sheet
Rev
Table
Page
3, 16-19
20
Description of Change
Date
Supply Voltage, VCC. Rating changed from 4.5V min. to 3.63V per Errata NEN-11-03.
Updated 10-Lead VFQFN package information.
A
6/02/11
3/4/16
T9
Ordering Information - removed quantity in tape and reel. Deleted LF note below table.
Removed ICS from part numbers where needed.
Updated header and footer.
A
©2016 Integrated Device Technology, Inc
21
Revision A March 4, 2016
83PN187I Data Sheet
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