840304BGILF [IDT]
TSSOP-24, Tube;
| 型号： | 840304BGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TSSOP-24, Tube 时钟 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：1013K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL
FREQUENCY SYNTHESIZER
ICS840304I
GENERAL DESCRIPTION
FEATURES
• Four LVCMOS/LVTTL outputs,
ICS840304I is an optimized PCI-X and PCI-e clock
ICS
HiPerClockS™
20Ω typical output impedance
One REF_OUT LVCMOS/LVTTL clock output
generator and a member of the HiperClocks™family
of high performance clock solutions from IDT. The
ICS840304I uses a 25MHz parallel crystal to
generate 33.33MHz to 133.33MHz clock signals,
• Selectable crystal oscillator interface, 25MHz,
18pF parallel resonant crystal or
LVCMOS/LVTTL single-ended clock input
replacing solutions requiring multiple oscillator and fanout buffer
solutions. The device supports 1% downspread spread spectrum
clocking. The ICS840304I has excellent phase jitter (<1ps rms)
over integration range of 1.5MHz - 22MHz. Designed for
Backplane, networking and industrial applications, the
ICS840304I can also drive the high-speed PCI-X and PCI-e
SerDes clock inputs of communication processors, DSPs,
switches and bridges.
• Support the following output frequencies: 33.33MHz,
66.67MHz, 100MHz or 133.33MHz
• VCO: 400MHz
• PLL and N divider bypass and output enable
• RMS phase jitter @100MHz, using a 25MHz crystal,
(1.5MHz - 22MHz): 0.46ps (typical) @ 3.3V
• Supports SSC, 1% downspread
• Full 3.3V and 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pulldown
BYPASS
1
24
23
22
21
20
19 Q1
18
17
VDD
XTAL_IN
XTAL_OUT
GND
REF_SEL
REF_IN
BYPASS
nc
VDDO_REF
REF_OUT
GND_REF
nOE
Q0
Q1
Q2
2
3
4
5
6
7
8
9
1
0
Q0
XTAL_IN
GND_Q
Q2
0
1
OSC
FemtoClock
PLL
VCO = 400MHz
XTAL_OUT
REF_IN
÷N
VDDA
16 Q3
F_SEL0
VDD
F_SEL1
VDDO_Q
14 nREF_OE
10
11
12
15
Pulldown
13
SSC
Q3
Pulldown
ICS840304I
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm
body package
REF_SEL
M = ÷16
Pulldown
Pulldown
SSC
nOE
G Package
Top View
REF_OUT
2
Pulldown
Pullup
F_SEL[1:0]
nREF_OE
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
1
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 11
VDD
Power
Input
Power
Input
Input
Input
Core supply pins.
2,
3
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
4
5
6
7
GND
Power supply ground.
Reference select pin. When HIGH selects REF_IN. When LOW,
selects crystal. LVCMOS/LVTTL interface levels.
REF_SEL
REF_IN
BYPASS
Pulldown
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
When HIGH bypasses PLL. When LOW, selects N divider.
LVCMOS/LVTTL interface levels.
Pulldown
8
9
nc
Unused
Power
No connect.
VDDA
Analog supply pin.
10,
12
F_SEL0,
F_SEL1
Frequency select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Input
Pulldown
13
14
15
SSC
nREF_OE
VDDO_Q
Input
Input
Pulldown SSC control pin. LVCMOS/LVTTL interface levels. See Table 3B.
Pullup
Reference output enable pin. LVCMOS/LVTTL interface levels.
Output supply pin for Q0:Q3 outputs.
Power
16, 17,
19, 20
Q3, Q2,
Q1, Q0
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
20Ω typical output impedence.
Power supply ground for Q0:Q3 outputs.
Output
Power
18
GND_Q
Active LOW output enable. When logic HIGH, the outputs are Hi-Z.
21
nOE
Input
Pulldown When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
22
23
24
GND_REF
REF_OUT
VDDO_REF
Power
Output
Power
Power supply ground for REF_OUT.
Reference clock output.
Output power supply for REF_OUT.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
kΩ
kΩ
Ω
VDDO = 3.465V
TBD
TBD
51
CPD
Power Dissipation Capacitance
V
DDO = 2.625V
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
51
20
TABLE 3A. FREQUENCY SELECT FUNCTION TABLE
Inputs
TABLE 3B. SSC FUNCTION TABLE
Input
Output Frequency
(MHz)
Mode
M Divider
Value
N Divider
Value
SSC
0 (default)
1
F_SEL1 F_SEL0
SSC Off
1% Downspread
0
1
0
1
0
0
1
1
16
16
16
16
12
33.33
66.67
100
6
4
3
133.33
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
2
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
70°C/W (0 mps)
-65°C to 150°C
I
Outputs, VO
Package Thermal Impedance, θ
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO_Q = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
Core Supply Voltage
3.465
VDD
V
V
VDDA
VDDO_Q
IDD
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.24
3.135
3.3
3.3
3.465
V
141
24
mA
mA
mA
IDDA
IDDO_Q
18
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO_Q = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
Core Supply Voltage
2.625
VDD
V
V
VDDA
VDDO_Q
IDD
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.24
2.375
2.5
2.5
2.625
V
132
24
mA
mA
mA
IDDA
IDDO_Q
18
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
3
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
V
V
V
DD = 3.3V 5%
DD = 2.5V 5%
DD = 3.3V 5%
DD = 2.5V 5%
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
Input Low Voltage
Input High Current
0.7
REF_IN, REF_SEL,
BYPASS, nOE, SSC,
F_SEL0, F_SEL1
VDD = VIN = 3.465V
150
5
µA
µA
or 2.625V
IIH
VDD = VIN = 3.465V
or 2.625V
nREF_OE
REF_IN, REF_SEL,
BYPASS, nOE, SSC,
F_SEL0, F_SEL1
V
DD = 3.465V
-5
µA
µA
or 2.625, VIN = 0V
IIL
Input Low Current
VDD = 3.465V
nREF_OE
-150
or 2.625, VIN = 0V
V
V
V
DDO_Q = 3.3V 5%
2.6
1.8
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage: NOTE 1
DDO_Q = 2.5V 5%
DDO_Q = 3.3V 5%
or 2.5V 5%
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO_Q/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
19.44
26.5625
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
4
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = VDDO_Q = 3.3V 5ꢀ% TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
33.33
66.67
100
MHz
MHz
MHz
MHz
fOUT
Output Frequency
133.33
33.33MHz
(Integration Range: 1.5MHz to 10MHz)
66.67MHz
0.49
0.43
0.46
0.47
ps
ps
ps
ps
(Integration Range: 1.5MHz to 10MHz)
RMS Phase Jitter%
(Random); NOTE 1% 2
tjit(Ø)
100MHz
(Integration Range: 1.5MHz to 22MHz)
133.33MHz
(Integration Range: 1.5MHz to 22MHz)
tjit(per) Period Jitter; NOTE 3
30
50
ps
ps
tsk(o)
Output Skew; NOTE 4% 5
FOUT = 33.33MHz% 66.67MHz%
SSC Modulation Frequency;
NOTE 6
FM
29
7
33.33
kHz
ꢀ
100MHz% 133.33MHz
FOUT = 33.33MHz% 66.67MHz%
SSC Modulation Factor;
NOTE 6
FMF
1.25
10
100MHz% 133.33MHz
FOUT = 33.33MHz% 66.67MHz%
SSCred
Spectral Reduction; NOTE 4
dB
100MHz% 133.33MHz
20ꢀ to 80ꢀ
tL
PLL Lock Time
1
ms
ns
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
1.3
50
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Spread Spectrum clocking disabled.
NOTE 3: Jitter performance using crystal inputs.
NOTE 4: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO_Q/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Spread Spectrum clocking enabled.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
5
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = VDDO_Q = 2.5V 5ꢀ% TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
33.33
66.67
100
MHz
MHz
MHz
MHz
fOUT
Output Frequency
133.33
33.33MHz
(Integration Range: 1.5MHz to 10MHz)
66.67MHz
0.50
0.45
0.54
0.58
ps
ps
ps
ps
(Integration Range: 1.5MHz to 10MHz)
RMS Phase Jitter%
(Random); NOTE 1% 2
tjit(Ø)
100MHz
(Integration Range: 1.5MHz to 22MHz)
133.33MHz
(Integration Range: 1.5MHz to 22MHz)
tjit(per) Period Jitter; NOTE 3
35
50
ps
ps
tsk(o)
Output Skew; NOTE 4% 5
FOUT = 33.33MHz% 66.67MHz%
SSC Modulation Frequency;
NOTE 6
FM
29
7
33.33
kHz
ꢀ
100MHz% 133.33MHz
FOUT = 33.33MHz% 66.67MHz%
SSC Modulation Factor;
NOTE 6
FMF
1.25
10
100MHz% 133.33MHz
FOUT = 33.33MHz% 66.67MHz%
SSCred
Spectral Reduction; NOTE 4
dB
100MHz% 133.33MHz
20ꢀ to 80ꢀ
tL
PLL Lock Time
1
ms
ns
ꢀ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
1.3
50
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Spread Spectrum clocking disabled.
NOTE 3: Jitter performance using crystal inputs.
NOTE 4: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO_Q/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Spread Spectrum clocking enabled.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
6
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
TYPICAL PHASE NOISE AT 100MHZ @ 3.3V
100MHz
RMS Phase Noise Jitter
1.5MHz to 22MHz = 0.46ps (typical)
10 Gigabit Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 100MHZ @ 2.5V
100MHz
RMS Phase Noise Jitter
1.5MHz to 22MHz = 0.54ps (typical)
10 Gigabit Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
7
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
1.65V 5%
1.25V 5%
1.65V 5%
1.25V 5%
SCOPE
SCOPE
VDD,
VDDO_Q
VDD,
VDDO_Q
VDDA
VDDA
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.25V 5%
-1.65V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VOH
VREF
VOL
Phase Noise Mask
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
Offset Frequency
Histogram
Reference Point
(Trigger Edge)
f1
f2
Mean Period
(First edge after trigger)
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
PERIOD JITTER
VDDO_Q
VDDO_Q
2
2
Qx
Qy
Q0:Q3
tPW
tPERIOD
VDDO_Q
2
tPW
tsk(o)
x 100%
odc =
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80%
tF
80%
20%
20%
Clock
Outputs
tR
OUTPUT RISE/FALL TIME
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
8
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS840304I provides sepa-
rate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD, VDDA, and VDDO_Q should be
individually connected to the power supply plane through vias,
and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation is
required. Figure 1 illustrates how a 10Ω resistor along with a
10µF and a .01µF bypass capacitor should be connected to
3.3V or 2.5V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840304I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
C2
33p
XTAL_OUT
XTAL_IN
X1
18pF Parallel Crystal
C1
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
9
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half.
This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
applications, R1 and R2 can be 100Ω. This can also be
accomplished by removing R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface dia-
gram is shown in Figure 3. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS inputs,
it is recommended that the amplitude be reduced from full swing
to half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
REF_IN INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_IN to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
10
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation technique
for EMI reduction. When spread-spectrum is enabled, a 32kHz
triangle waveform is used with 1% down-spread (+0.0% / 1%)
from the nominal clock frequency. An example of a triangle fre-
quency modulation profile is shown in Figure 4A below.
tive to the nominal clock frequency can be seen in the fre-
quency domain, as shown in Figure 4B. The ratio of this width
to the fundamental frequency is typically 1%, and will not ex-
ceed TBD. The resulting spectral reduction will be greater than
7dB, as shown in Figure 4B. It is important to note the
ICS840304I 7dB minimum spectral reduction is the component-
specific EMI reduction, and will not necessarily be the same as
the system EMI reduction.
The ICS840304I triangle modulation frequency deviation will
not exceed TBD down-spread from the nominal clock frequency
(+0.0% / 1%). An example of the amount of down spread rela-
∆ − 10 dBm
Fnom
B
A
➤
(1 - δ) Fnom
δ = 1%
➤
➤
0.5/fm
1/fm
FIGURE 4A. TRIANGLE FREQUENCY MODULATION
FIGURE 4B. CLOCK OUTPUT IN FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF
(B) SPREAD-SPECTRUM ON
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
11
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
62°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
TRANSISTOR COUNT
The transistor count for ICS840304I is: 4465
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
12
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
13
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS840304BGI
Marking
Package
Shipping Packaging
tube
Temperature
ICS840304BGI
ICS840304BGI
ICS840304BGIL
ICS840304BGIL
24 Lead TSSOP
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS840304BGIT
ICS840304BGILF
ICS840304BGILFT
24 Lead TSSOP
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER
14
ICS840304BGI REV A DECEMBER 4, 2006
ICS840304I
FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
©2020 ICPDF网 联系我们和版权申明