840N022BGILF [IDT]
FemtoClock® NG Crystal-to-LVCMOS/LVTTL Clock;
| 型号： | 840N022BGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FemtoClock® NG Crystal-to-LVCMOS/LVTTL Clock |
| 文件： | 总13页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FemtoClock® NG
Crystal-to-LVCMOS/LVTTL Clock
840N022
DATA SHEET
General Description
Features
The 840N022 is a LVCMOS/LVTTL clock synthesizer designed for
Ethernet applications. The device generates a selectable 125MHz or
62.5MHz clock signal with excellent phase jitter performance. The
device uses IDT’s fourth generation FemtoClock® NG technology
for an optimum of high clock frequency, low phase noise
performance and low power consumption.The device supports 2.5V
or 3.3V voltage supply and is packaged in a small, lead-free (RoHS
6) 8-lead TSSOP package. The extended temperature range
supports wireless infrastructure, telecommunication, and networking
end equipment requirements.
• Fourth generation FemtoClock® NG technology
• 125MHz output clock synthesized from a 25MHz fundamental
mode crystal
• One LVCMOS/LVTTL clock output
• Crystal interface designed for a 12pF parallel resonant crystal
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.148ps (maximum)
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.479ps (maximum)
• LVCMOS interface levels for the control inputs
• Full 2.5V or 3.3V supply voltage
FREQ_SEL Frequency Table
Input
FREQ_SEL
0 (default)
1
Output Frequency
• Lead-free (RoHS 6) packaging
• -40°C to 85°C ambient operating temperature
• Use replacement part: 840N202CKI-dddLF
fXTAL = 25MHz
fXTAL = 20MHz
100MHz
125MHz
62.5MHz
50MHz
NOTE: FREQ_SEL is an asynchronous control.
OE Function Table
Input
OE
0
Output Enable
Output Q is disabled in high-impedance state
Output Q is enabled.
1 (default)
NOTE: OE is an asynchronous control.
Pin Assignment
Block Diagram
VDDA
OE
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
VDD
Q
GND
FREQ_SEL
FemtoClock® NG
VCO
490-637.5MHz
XTAL_IN
PFD
÷5,
÷10
OSC
&
Q
LPF
XTAL_OUT
840N022
8-lead TSSOP
÷25
4.40mm x 3.0mm x 0.925mm
package body
Pulldown
Pullup
FREQ_SEL
OE
G Package
Top View
840N022 REVISION A 8/14/15
1
©2015 Integrated Device Technology, Inc.
840N022 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
VDDA
OE
Type
Description
1
2
Power
Input
Analog power supply.
Pullup
Output enable pin. LVCMOS interface levels.
3,
4
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
5
6
7
8
FREQ_SEL
Input
Power
Output
Power
Pulldown
Frequency select pin. LVCMOS interface levels.
Power supply ground.
GND
Q
Single-ended clock output. LVCMOS/LVTTL interface levels.
Core supply pin.
VDD
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
OE, FREQ_SEL
VDD = 3.465V
Minimum
Typical
3.5
11
Maximum
Units
pF
pF
pF
k
k
CIN
Input Capacitance
Power Dissipation
Capacitance
CPD
VDD = 2.625V
9
RPullup
Input Pullup Resistor
51
RPulldown
Input Pulldown Resistor
51
V
DD = 3.3V
DD = 2.5V
15
ROUT
Output Impedance
V
19
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
2
REVISION A 8/14/15
840N022 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
3.63V
Inputs, VI
XTAL_IN
0V to 2V
Other Inputs
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
117°C/W (0 mps)
-65C to 150C
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, V = 3.3V±5% or 2.5V±5%, T = -40°C to 85°C
DD
A
Symbol Parameter
Test Conditions
Minimum
Typical
3.3
Maximum
3.465
VDD
Units
V
VDD
VDDA
IDDA
IDD
Core Supply Voltage
2.375
Analog Supply Voltage
Analog Supply Current
Power Supply Current
VDD – 0.18
3.3
V
18
mA
mA
67
Table 3B. LVCMOS/LVTTL DC Characteristics, V = 3.3V±5% or 2.5V±5%, T = -40°C to 85°C
DD
A
Symbol Parameter
Test Conditions
DD = 3.3V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
V
2
V
V
V
V
VIH Input High Voltage
VDD = 2.5V
VDD = 3.3V
1.7
-0.3
OE
FREQ_SEL
VDD = 3.3V
-0.3
0.5
VIL
Input Low Voltage
OE
V
DD = 2.5V
-0.3
-0.3
0.7
0.5
5
V
V
FREQ_SEL
OE
VDD = 2.5V
V
DD = VIN = 3.465V or 2.625V
DD = VIN = 3.465V or 2.625V
µA
µA
µA
µA
V
IIH
Input High Current
Input Low Current
FREQ_SEL
OE
V
150
V
DD = 3.465V or 2.625V, VIN = 0V
-150
-5
IIL
FREQ_SEL VDD = 3.465V or 2.625V, VIN = 0V
DD = 3.465V
V
2.6
1.8
Output High
Voltage; NOTE 1
VOH
Q
VDD = 2.625V
V
Output Low Voltage;
NOTE 1
VOL
Q
VDD = 3.465V or 2.625V
0.5
V
NOTE 1: Output terminated with 50 to VDD / 2. See Parameter Measurement Information Section,
LVCMOS Output Load Test Circuit Diagrams.
REVISION A 8/14/15
3
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
840N022 DATA SHEET
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
19.60
25.50
80
MHz
Equivalent Series Resistance (ESR)
Shunt Capacitance
7
pF
Capacitive Load (CL)
12
pF
AC Characteristics
Table 5. AC Characteristics, V = 3.3V±5% or 2.5V±5%, T = -40°C to 85°C
DD
A
Symbol
Parameter
Test Conditions
Minimum
98.00
Typical
125
Maximum
127.50
Units
MHz
MHz
FREQ_SEL = 0
FREQ_SEL = 1
fOUT
Output Frequency
49.00
62.5
63.75
fOUT = 125MHz, 25MHz Crystal,
Integration Range:
0.104
0.286
0.148
0.479
ps
ps
1.875MHz – 20MHz
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
f
OUT = 125MHz, 25MHz Crystal,
Integration Range:
12kHz – 20MHz
125MHz, Offset: 10Hz
125MHz, Offset: 100Hz
125MHz, Offset: 1kHz
125MHz, Offset: 10kHz
125MHz, Offset: 100kHz
125MHz, Offset: 1MHz
125MHz, Offset: 10MHz
20% to 80%
-51.7
-83.6
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps
-115.9
-130.2
-134.7
-141.8
-158.3
N
Single-Side Band Noise Power
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
48
600
52
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized with 20MHz and 25MHz crystals.
NOTE 1: Please refer to the phase noise plots.
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
4
REVISION A 8/14/15
840N022 DATA SHEET
Typical Phase Noise at 125MHz
Offset Frequency (Hz)
Typical Phase Noise at 125MHz
Offset Frequency (Hz)
REVISION A 8/14/15
5
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
840N022 DATA SHEET
Parameter Measurement Information
1.65V ± 5%
1.65V ± 5%
1.25V ± 5%
1.25V ± 5%
SCOPE
SCOPE
V
V
DD
DD
V
DDA
Qx
Qx
V
DDA
GND
GND
-1.25V ± 5%
-1.65V ± 5%
2.5V LVCMOS/LVTTL Output Load Test Circuit
3.3V LVCMOS/LVTTL Output Load Test Circuit
80%
tF
80%
tR
20%
20%
Q
RMS Phase Jitter
Output Rise/Fall Time
Q
Output Duty Cycle/Pulse Width/Period
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
6
REVISION A 8/14/15
840N022 DATA SHEET
Applications Information
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by
one side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/ns. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 1A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50 applications,
R1 and R2 can be 100. This can also be accomplished by removing
R1 and changing R2 to 50. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 1B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
VCC
XTAL_OUT
R1
100
C1
Rs
Zo = 50 ohms
Ro
XTAL_IN
.1uf
R2
100
Zo = Ro + Rs
LVCMOS Driver
Figure 1A. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_OUT
C2
Zo = 50 ohms
XTAL_I N
.1uf
Zo = 50 ohms
R1
50
R2
50
LVPECL Driver
R3
50
Figure 1B. General Diagram for LVPECL Driver to XTAL Input Interface
REVISION A 8/14/15
7
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
840N022 DATA SHEET
Schematic Example
Figure 2 shows an example 840N022 application schematic in which
the device is operated at VDD = +3.3V. The schematic example focus-
es on functional connections and is intended as an example only and
may not represent the exact user configuration. Refer to the pin de-
scription and functional tables in the datasheet to ensure the logic
control inputs are properly set. For example OE and FREQ_SEL can
be configured from an FPGAinstead of set with pull- up and pulldown
resistors as shown
placement of the filter components be on the device side of the PCB
as close to the power pins as possible. If space is limited, the 0.1µF
capacitors on the VDD and VDDA pins must be placed on the device
side with direct return to the ground plane though vias. The remaining
filter components can be on the opposite side of the PCB.
Power supply filter component recommendations are a general
guideline to be used for reducing external noise from coupling into
the devices. The filter performance is designed for a wide range of
noise frequencies. This low-pass filter starts to attenuate noise at ap-
proximately 10kHz. If a specific frequency noise component is
known, such as switching power supplies frequencies, it is recom-
mended that component values be adjusted and if required, addition-
al filtering be added. Additionally, good general design practices for
power plane voltage stability suggests adding bulk capacitance in the
local area of all devices.
The crystal is to be laid out on the 840N022 side of the board and
close to XTAL_IN and XTAL_OUT pins. Tuning capacitors C1 and C2
can be fine tuned to center the oscillator center frequency.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise, so to achieve optimum jitter perfor-
mance isolation of the VDD pin from power supply is required. In order
to achieve the best possible filtering, it is recommended that the
Logic Control Input Examples
for OE and FREQ_SEL
3. 3V
Set Logic
Input to '1'
Set Logic
Input to '0'
VC C
VCC
FB1
2
1
VDD
C4
BLM18BB221SN1
RU1
1K
RU2
Not Install
C5
0.1uF
10uF
R1 10
To Logic
Input
pins
To Logic
In put
pins
VDD A
C7
10uF
RD1
RD2
1K
Not Install
Place one 0.1uF bypass cap
directly adjacent to the VDD
pin and one directly adjacent
to the VDDA pin.
VDD
C6
0. 1uF
VD DA
C3
U3
0. 1uF
2
5
OE
FREQ_SEL
OE
FREQ_SEL
R3
33
Zo = 50 Ohm
3
4
7
XTAL_OUT
XTAL_IN
Q
25MHz (12pf )
X1
C1
C2
LVCMOS Receiv er
5pF
5pF
Figure 2. 840N022 Schematic Example
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
8
REVISION A 8/14/15
840N022 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 840N022.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 840N022 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The
following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * (IDD + IDDA) = 3.465V *(67mA + 18mA) = 294.53mW
Output Impedance ROUT Current due to Loading 50 to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.7mA
•
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW
Total Power (ROUT) = 10.7mW * 1 = 10.7mW
Dynamic Power Dissipation at 125MHz
Power (125MHz) = CPD * Frequency * (VDD)2 = 11pF * 125MHz * (3.465V)2 = 16.51mW
Total Power (125MHz) = 16.51mW * 1 = 16.51mW
Total Power Dissipation
•
Total Power
= Power (core)MAX + Power (ROUT) + Power (125MHz)
= 294.53mW + 10.7mW + 16.51mW
= 321.74mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 117°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.322W *117°C/W = 122.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance for 8 Lead TSSOP, Forced Convection
JA
JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
117°C/W
REVISION A 8/14/15
9
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
840N022 DATA SHEET
Reliability Information
Table 7. vs. Air Flow Table for a 8-lead TSSOP
JA
JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
117°C/W
Transistor Count
The transistor count for 840N022 is: 24,811
Package Outline and Package Dimensions
Package Outline - G Suffix for 8 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Minimum
Symbol
Maximum
N
A
8
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.5
0.80
0.19
0.09
2.90
c
D
E
6.40 Basic
0.65 Basic
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
10
REVISION A 8/14/15
840N022 DATA SHEET
Ordering Information
Table 9. Ordering Information
Part/Order Number
840N022BGILF
840N022BGILFT
Marking
22BIL
22BIL
Package
Lead-Free, 8-lead TSSOP
Lead-Free, 8-lead TSSOP
Shipping Packaging
Tube
Temperature
-40C to 85C
-40C to 85C
Tape & Reel
REVISION A 8/14/15
11
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
840N022 DATA SHEET
Revision History Sheet
Rev
Table
Page
Description of Change
Date
Product Discontinuation Notice - Last time buy expires August 14, 2016
PDN CQ-15-04
A
8/14/15
FEMTOCLOCK® NG CRYSTAL-TO-LVCMOS/LVTTL CLOCK
SYNTHESIZER
12
REVISION A 8/14/15
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this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
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While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as
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Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.
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