8421004AGI-01LFT [IDT]
Clock Generator, 170MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24;
| 型号： | 8421004AGI-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 170MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-24 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：796K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FemtoClock™ Crystal-to-HSTL
Frequency Synthesizer
ICS8421004I-01
DATA SHEET
General Description
Features
The ICS8421004I-01 is a 4 output HSTL Synthesizer
optimized to generate Ethernet reference clock
frequencies. Using a 25MHz, 18pF parallel resonant
crystal, the following frequencies can be generated
based on the 2 frequency select pins (F_SEL[1:0]):
• Four HSTL outputs (VOH_MAX = 1.5V)
S
IC
• Selectable crystal oscillator interface or LVCMOS/LVTTL
HiPerClockS™
single-ended input
• Supports the following output frequencies: 156.25MHz, 125MHz,
62.5MHz
156.25MHz, 125MHz and 62.5MHz. The ICS8421004I-01 uses
IDT’s 3rd generation low phase noise VCO technology and can
achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet
jitter requirements. The ICS8421004I-01 is packaged in a small
24-pin TSSOP package.
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.44ps (typical)
• Power supply modes:
Core/Output
3.3V/1.8V
2.5V/1.8V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Frequency Select Function Table
Inputs
Output Frequency (MHz),
F_SEL1
F_SEL0
M Div. Value
N Div. Value
M/N Div. Value
(25MHz Ref.)
156.25
125
0
0
1
1
0
1
0
1
25
25
25
25
4
5
6.25
5
10
2.5
62.5
not used
not used
Block Diagram
F_SEL[1:0]
Pin Assignment
2
Pulldown
nQ1
Q1
nQ2
Q2
1
2
24
23
Pulldown
nPLL_SEL
Q0
V
DDO
3
4
22
21
V
Q3
DDO
Q0
F_SEL[1:0]
nQ0
nQ0
MR
nPLL_SEL
nc
5
6
7
8
9
20 nQ3
Pulldown
25MHz
0 0 ÷4 (default)
0 1 ÷5
REF_CLK
XTAL_IN
1
0
1
0
19
18
17
GND
nc
Q1
1 0 ÷10
nXTAL_SEL
nQ1
1 1 Not Used
Phase
Detector
VCO
16 REF_CLK
VDDA
OSC
GND
XTAL_IN
XTAL_OUT
F_SEL0 10
15
14
13
XTAL_OUT
nXTAL_SEL
VDD
11
12
Q2
Pulldown
Pulldown
F_SEL1
nQ2
ICS421004I-01
24-Lead TSSOP
4.4mm x 7.8mm x 0.92mm
package body
M = 25 (fixed)
Q3
nQ3
MR
G Package
Top View
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 2
Name
nQ1, Q1
VDDO
Type
Description
Output
Power
Output
Differential output pair. HSTL interface levels.
Output supply pins.
3, 22
4, 5
Q0, nQ0
Differential output pair. HSTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
6
MR
Input
Pulldown
PLL select. When LOW, selects PLL (PLL enabled). When HIGH, the PLL is
bypassed. LVCMOS/LVTTL interface levels.
7
nPLL_SEL
Input
Pulldown
8, 18
9
nc
Unused
Power
No connect.
VDDA
Analog supply pin.
10,
12
F_SEL0,
F_SEL1
Input
Power
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pins.
11
VDD
13,
14
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
15, 19
16
GND
Power
Input
Power supply ground.
REF_CLK
Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects between crystal or REF_CLK inputs as the PLL reference source. Selects
Pulldown XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL
interface levels.
17
nXTAL_SEL
Input
20, 21
23, 24
nQ3, Q3
Q2, nQ2
Output
Output
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
4
RPULLDOWN Input Pulldown Resistor
51
kΩ
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
70°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
3.135
1.6
Typical
3.3
Maximum
3.465
3.465
2.0
Units
V
VDD
VDDA
VDDO
IDD
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.3
V
1.8
V
113
mA
mA
mA
IDDA
IDDO
13
No Load
0
Table 3B. Power Supply DC Characteristics, VDD = 2.5V 5%, VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
2.375
1.6
Typical
2.5
Maximum
2.625
2.625
2.0
Units
V
VDD
VDDA
VDDO
IDD
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Core Supply Current
Analog Supply Current
Output Supply Current
2.5
V
1.8
V
100
mA
mA
mA
IDDA
IDDO
13
No Load
0
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Table 3C. LVCMOS/LVTTL DC Characteristics, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
DD = 3.3V
VDD = 2.5V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
V
2
V
V
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
DD = 3.3V
DD = 2.5V
Input Low Voltage
V
0.7
Input
High Current
REF_CLK, MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
VDD = VIN = 3.465V or
2.625V
IIH
IIL
150
µA
µA
Input
Low Current
REF_CLK, MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
VDD = 3.465V or 2.625V,
VIN = 0V
-5
Table 3D. HSTL DC Characteristics, VDD = 3.3V 5% or 2.5V 5%, VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
0.95
0
Typical
Maximum
1.5
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
V
V
V
V
VOL
0.4
VOX
0.40
0.6
0.60
VSWING
1.4
NOTE 1: Outputs termination with 50Ω to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
22.4
27.2
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum
140
Typical
Maximum
170
Units
MHz
MHz
MHz
ps
fOUT
Output Frequency
112
136
56
68
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
30
156.25MHz, (1.875MHz – 20MHz)
125MHz, (1.875MHz – 20MHz)
62.5MHz, (1.875MHz – 20MHz)
20% to 80%
0.44
0.48
0.49
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
48
800
52
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross
points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Table 5B. AC Characteristics, VDD = 2.5V 5%, VDDO = 1.8V 0.2V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum
140
Typical
Maximum
170
Units
MHz
MHz
MHz
ps
fOUT
Output Frequency
112
136
56
68
tsk(o)
tjit(Ø)
Output Skew; NOTE 1, 2
30
156.25MHz, (1.875MHz – 20MHz)
125MHz, (1.875MHz – 20MHz)
62.5MHz, (1.875MHz – 20MHz)
20% to 80%
0.41
0.49
0.50
ps
RMS Phase Jitter (Random);
NOTE 3
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
48
800
52
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the differential cross
points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Typical Phase Noise at 156.25MHz (3.3V Core / 1.8V Output)
Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.44ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
Ethernet Filter to raw data
Offset Frequency (Hz)
Typical Phase Noise at 62.5MHz (3.3V Core / 1.8V Output)
Ethernet Filter
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.49ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
Ethernet Filter to raw data
Offset Frequency (Hz)
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Parameter Measurement Information
3.3V 5%
2.5V 5%
1.8V 0.2V
2.5V 5%
1.8V 0.2V
3.3V 5%
V
DD
SCOPE
V
SCOPE
DD
V
Qx
Qx
V
DDO
DDO
V
V
DDA
DDA
HSTL
HSTL
nQx
nQx
GND
GND
0V
0V
3.3V/1.8V Output Load AC Test Circuit
2.5V/1.8V Output Load AC Test Circuit
Phase Noise Plot
nQx
Qx
Phase Noise Mask
nQy
Qy
Offset Frequency
tsk(o)
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
Output Skew
RMS Phase Jitter
nQ0, nQ1
Q0, Q1
nQ0, nQ1
80%
tF
80%
tR
VSWING
20%
tPW
20%
tPERIOD
Q0, Q1
tPW
odc =
x 100%
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform- ance,
power supply isolation is required. The ICS8421004I-01 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA and VDDO should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
HSTL Outputs
All control pins have internal pull-downs; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
All unused HSTL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
REF_CLK Input
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the REF_CLK to ground.
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Crystal Input Interface
The ICS8421004I-01 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 25MHz 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1 and R2
can be 100Ω. This can also be accomplished by removing R1 and
making R2 50Ω. By overdriving the crystal oscillator, the device will
be functional, but note, the device performance is guaranteed by
using a quartz crystal.
VDD
VDD
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Schematic Example
Figure 4 shows an example of ICS8421004I-01 application
schematic. In this example, t he device is operated at VDD = 3.3V and
VDDO = 1.8V. Both input options are shown. The device can either be
driven by using a quartz crystal or a 3.3V LVCMOS signal. The C1
and C2 = 22pF are recommended for frequency accuracy. For
differential board layouts, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. The LVHSTL output driver
termination examples are shown in this schematic. The decoupling
capacitor should be located as close as possible to the power pin.
nPLL_SEL
MR
Zo = 50 Ohm
Zo = 50 Ohm
Q0
F_SEL0
VDD
F_SEL1
nQ0
+
-
VDDA
C3
R1
10
C4
VDD
VDDO
10uF
0.01u
Logic Control Input Examples
R2
R3
50
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
50
RU1
1K
RU2
Not Install
To Logic
Input
To Logic
Input
pins
VDD=3.3V
pins
RD1
RD2
1K
VDDO=1.8V
Not Install
U1
VDDO
Zo = 50 Ohm
nXTAL_SEL
Q3
nQ3
+
-
25MHz
18pF
X1
C1
Zo = 50 Ohm
22pF
VDD
C2
22pF
Q1
R4
50
R5
50
Ro ~ 7 Ohm
R6
43
Zo = 50 Ohm
VDDO
VDD
(U1-3)
(U1-22)
C6
(U1-11)
VDDO
Driver_LVCMOS
C5
0.1uF
C7
0.1uF
0.1uF
Figure 4. ICS8421004I-01 Schematic Layout Example
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8421004I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for theICS8421004I-01 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (113mA + 13mA) = 436.59mW
Power (outputs)MAX = 27.8mW/Loaded Output pair
If all outputs are loaded, the total power is 4 x 27.8mW = 111.2mW
Total Power_MAX (3.465V, with all outputs switching) = 436.59mW + 111.2mW = 547.79mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 70°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.548W * 70°C/W = 123.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 24 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the HSTL output pairs.
HSTL output driver circuit and termination are shown in Figure 4.
VDDO
Q1
VOUT
RL
50Ω
Figure 4. HSTL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /RL) * (VDDO_MAX – VOH_MAX
)
Pd_L = (VOL_MAX/RL) * (VDDO_MAX– VOL_MAX
)
Pd_H = (1.5V/50Ω) * (2V – 1.5V) = 15mW
Pd_L = (0.4V/50Ω) * (2V – 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 27.8mW
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
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©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 24 Lead TSSOP
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
Transistor Count
The transistor count for ICS8421004I-01 is: 2951
Package Outline and Package Dimensions
Package Outline - G Suffix for 24 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
24
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.5
0.80
0.19
0.09
7.70
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
13
©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Ordering Information
Table 9. Ordering Information
Part/Order Number
8421004AGI-01
8421004AGI-01T
8421004AGI-01LF
8421004AGI-01LFT
Marking
Package
24 Lead TSSOP
24 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS421004AI01
ICS421004AI01
ICS21004AI01L
ICS21004AI01L
“Lead-Free” 24 Lead TSSOP
“Lead-Free” 24 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
14
©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
B
T3A, T3B
T5A, T5B
3
Power Supply Tables - corrected VDDO min./max.
8/8/06
5
9
AC Tables - added temperature junction note.
Added LVCMOS to XTAL Interface section.
Added schematic example.
10
B
11/16/09
11 - 12 Power Considerations - corrected Power Dissipation, Junction Temperature and Total
Power Dissipation calculations.
T9
14
Ordering Information Table - added LF marking.
ICS8421004AGI-01 REVISION B NOVEMBER 20, 2009
15
©2009 Integrated Device Technology, Inc.
ICS8421004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
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Technical Support
800-345-7015 (inside USA)
netcom@idt.com
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
San Jose, California 95138
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2009. All rights reserved.
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8421004AGI-01T
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