843011AGT [IDT]

Clock Generator, 113.33MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8;
843011AGT
型号: 843011AGT
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

Clock Generator, 113.33MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, MO-153, TSSOP-8

光电二极管
文件: 总14页 (文件大小:275K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS843011 is a Fibre Channel Clock Generator. One differential 3.3V LVPECL output  
The ICS843011 uses a 26.5625MHz crystal to synthesize  
Crystal oscillator interface designed for 26.5625MHz  
18pF parallel resonant crystal  
106.25MHz or a 25MHz crystal to synthesize 100MHz. The  
ICS843011 has excellent <1ps phase jitter performance, over  
the 637kHz – 10MHz integration range. The ICS843011 is  
packaged in a small 8-pin TSSOP, making it ideal for use in  
systems with limited board space.  
Output frequency: 106.25MHz or 100MHz  
VCO range: 560MHz - 680MHz  
RMS phase jitter @ 100MHz, using a 25MHz crystal  
(637kHz - 10MHz): 0.80ps (typical)  
RMS phase noise at 106.25MHz  
Phase noise:  
Offset  
Noise Power  
100Hz ............... -92.8 dBc/Hz  
1kHz ............. -119.6 dBc/Hz  
10kHz ............. -129.5 dBc/Hz  
100kHz ............. -130.5 dBc/Hz  
3.3V operating supply  
Available in both standard (RoHS 5) and lead-free  
(RoHS 6) packages  
-40°C to 85°C ambient operating temperature  
FREQUENCY TABLE  
Crystal (MHz) Output Frequency (MHz)  
26.5625  
25  
106.25  
100  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
VCCA  
VEE  
VCC  
Q0  
1
2
3
4
8
7
6
5
VCO  
XTAL_IN  
OSC  
XTAL_OUT  
nQ0  
Q0  
Phase  
Detector  
÷6  
637.5MHz w/  
26.5625MHz Ref.  
XTAL_OUT  
XTAL_IN  
nQ0  
nc  
ICS843011  
M = ÷24 (fixed)  
8-Lead TSSOP  
4.40mm x 3.0mm x 0.925mm package body  
G Package  
TopView  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
TABLE 1. PIN DESCRIPTIONS  
Number  
Name  
VCCA  
VEE  
Type  
Description  
1
2
Power  
Power  
Analog supply pin.  
Negative supply pin.  
3,  
4
XTAL_OUT,  
XTAL_IN  
Crystal oscillator interface. XTAL_IN is the input,  
XTAL_OUT is the output.  
Input  
5
6, 7  
8
nc  
nQ0, Q0  
VCC  
Unused  
Output  
Power  
No connect.  
Differential clock outputs. LVPECL interface levels.  
Core supply pin.  
TABLE 2. PIN CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
CIN  
Input Capacitance  
4
pF  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
ABSOLUTE MAXIMUM RATINGS  
SupplyVoltage, V  
4.6V  
NOTE: Stresses beyond those listed under Absolute  
Maximum Ratings may cause permanent damage to the  
device.These ratings are stress specifications only.Functional  
operation of product at these conditions or any conditions be-  
yond those listed in the DC Characteristics or AC Character-  
istics is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect product reliability.  
CC  
Inputs, V  
-0.5V to VCC + 0.5V  
I
Outputs, IO  
Continuous Current  
Surge Current  
50mA  
100mA  
PackageThermal Impedance, θ  
101.7°C/W (0 mps)  
-65°C to 150°C  
JA  
StorageTemperature, T  
STG  
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum Units  
VCC  
VCCA  
ICCA  
IEE  
Core Supply Voltage  
3.465  
3.465  
12  
V
Analog Supply Voltage  
Analog Supply Current  
Power Supply Current  
3.135  
3.3  
V
included in IEE  
mA  
mA  
93  
TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C  
Symbol  
VOH  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
Peak-to-Peak Output Voltage Swing  
VCC - 1.4  
VCC - 2.0  
0.6  
VCC - 0.9  
VCC - 1.7  
1.0  
V
V
V
VOL  
VSWING  
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.  
TABLE 4. CRYSTAL CHARACTERISTICS  
Parameter  
Test Conditions  
Minimum  
25  
Typical Maximum Units  
Fundamental  
Mode of Oscillation  
Frequency  
26.5625  
MHz  
Ω
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
50  
7
pF  
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
FOUT  
Output Frequency  
93.33  
113.33  
MHz  
106.25MHz;  
Integration Range: 637KHz - 10MHz  
100MHz;  
0.80  
0.80  
ps  
RMS Phase Jitter (Random);  
NOTE 1  
tjit(Ø)  
ps  
Integration Range: 637KHz - 10MHz  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20ꢀ to 80ꢀ  
300  
48  
600  
52  
ps  
NOTE 1: Please refer to the Phase Noise Plot.  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
TYPICAL PHASE NOISE AT 100MHZ  
0
-10  
-20  
Filter  
-30  
-40  
100MHz  
RMS Phase Noise Jitter  
-50  
637K to 10MHz = 0.80ps (typical)  
-60  
-70  
-80  
-90  
Raw Phase Noise Data  
-100  
-110  
-120  
-130  
-140  
-150  
-160  
-170  
-180  
-190  
Phase Noise Result by adding  
a Filter to raw data  
100  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET FREQUENCY (HZ)  
TYPICAL PHASE NOISE AT 106.25MHZ  
0
-10  
-20  
Fibre Channel Filter  
-30  
-40  
106.25MHz  
RMS Phase Noise Jitter  
-50  
637K to 10MHz = 0.80ps (typical)  
-60  
-70  
-80  
-90  
Raw Phase Noise Data  
-100  
-110  
-120  
-130  
-140  
-150  
-160  
-170  
-180  
-190  
Phase Noise Result by adding  
Fibre Channel Filter to raw data  
100  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET FREQUENCY (HZ)  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
PARAMETER MEASUREMENT INFORMATION  
2V  
Phase Noise Plot  
SCOPE  
VCC  
Qx  
Phase Noise Mask  
LVPECL  
VEE  
nQx  
Offset Frequency  
f1  
f2  
-1.3V 0.165V  
RMS Jitter = Area Under the Masked Phase Noise Plot  
3.3V OUTPUT LOAD AC TEST CIRCUIT  
RMS PHASE JITTER  
nQ0  
80ꢀ  
tF  
80ꢀ  
tR  
Q0  
VSWING  
20ꢀ  
Pulse Width  
tPERIOD  
Clock  
Outputs  
20ꢀ  
tPW  
odc =  
tPERIOD  
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD  
OUTPUT RISE/FALL TIME  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
APPLICATION INFORMATION  
POWER SUPPLY FILTERING TECHNIQUES  
As in any high speed analog circuitry, the power supply pins  
are vulnerable to random noise. The ICS843011 provides  
separate power supplies to isolate any high switching  
noise from the outputs to the internal PLL. VCC, and VCCA  
should be individually connected to the power supply  
plane through vias, and bypass capacitors should be  
used for each pin. To achieve optimum jitter performance,  
power supply isolation is required. Figure 1 illustrates how  
a 10Ω resistor along with a 10μF and a .01μF bypass  
capacitor should be connected to each VCCA pin.  
3.3V  
VCC  
.01μF  
.01μF  
10Ω  
VCCA  
10μF  
FIGURE 1. POWER SUPPLY FILTERING  
CRYSTAL INPUT INTERFACE  
The ICS843011 has been characterized with 18pF parallel allel resonant crystal and were chosen to minimize the ppm er-  
resonant crystals. The capacitor values, C1 and C2, shown in ror.The optimum C1 and C2 values can be slightly adjusted for  
Figure 2 below were determined using a 26.5625MHz, 18pF par- different board layouts.  
XTAL_OUT  
C1  
33p  
X1  
18pF Parallel Crystal  
XTAL_IN  
C2  
22p  
Figure 2. CRYSTAL INPUt INTERFACE  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
APPLICATION SCHEMATIC  
Figure 3A shows a schematic example of the ICS843011. used for generating 106.25MHz output frequency. The C1  
An example of LVEPCL termination is shown in this sche- = 27pF and C2 = 33pF are recommended for frequency  
accuracy. For different board layout, the C1 and C2 values  
matic. Additional LVPECL termination approaches are  
shown in the LVPECL Termination Application Note. In this may be slightly adjusted for optimizing frequency accuracy.  
example, an 18 pF parallel resonant 26.5625MHz crystal is  
VCC  
VCCA  
VCC  
R2  
10  
C3  
10uF  
C4  
0.01u  
R3  
R5  
133  
133  
U1  
Zo = 50 Ohm  
Zo = 50 Ohm  
Q
VCC  
1
8
7
6
5
VCCA  
VEE  
XTAL_OUT  
XTAL_IN  
VCC  
Q0  
nQ0  
NC  
+
-
2
3
4
18pF  
nQ  
C2  
33pF  
X1  
ICS843011  
R4  
R6  
C5  
0.1u  
82.5  
82.5  
C1  
22pF  
VCC=3.3V  
FIGURE 3A. ICS843011 SCHEMATIC EXAMPLE  
PC BOARD LAYOUT EXAMPLE  
Figure 3B shows an example of ICS843011 P.C. board  
layout. The crystal X1 footprint shown in this example al-  
lows installation of either surface mount HC49S or through-  
hole HC49 package. The footprints of other components in  
this example are listed in the Table 6. There should be at  
least one decoupling capacitor per power pin. The  
decoupling capacitors should be located as close as pos-  
sible to the power pins. The layout assumes that the board  
has clean analog power ground plane.  
TABLE 6. FOOTPRINT TABLE  
Reference  
C1, C2  
C3  
Size  
0402  
0805  
0603  
0603  
C4, C5  
R2  
NOTE: Table 6, lists component  
sizes shown in this layout example.  
FIGURE 3B. ICS843011 PC BOARD LAYOUT EXAMPLE  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
POWER CONSIDERATIONS  
This section provides information on power dissipation and junction temperature for the ICS843011.  
Equations and example calculations are also provided.  
1. Power Dissipation.  
The total power dissipation for the ICS843011 is the sum of the core power plus the power dissipated in the load(s).  
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.  
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.  
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 93mA = 322.2mW  
Power (outputs)MAX = 30mW/Loaded Output pair  
Total Power_MAX (3.465V, with all outputs switching) = 322.2mW + 30mW = 352.2mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the  
device. The maximum recommended junction temperature for the devices is 125°C.  
The equation for Tj is as follows: Tj = θJA * Pd_total + TA  
Tj = JunctionTemperature  
θJA = Junction-to-AmbientThermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = AmbientTemperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a  
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W perTable 6 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.352W * 90.5°C/W = 116.9°C. This is below the limit of 125°C.  
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,  
and the type of board (single layer or multi-layer).  
TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION  
θJA byVelocity (Meters per Second)  
0
1
2.5  
89.8°C/W  
Multi-Layer PCB, JEDEC Standard Test Boards  
101.7°C/W  
90.5°C/W  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
3. Calculations and Equations.  
The purpose of this section is to derive the power dissipated into the load.  
LVPECL output driver circuit and termination are shown in Figure 4.  
VCC  
Q1  
VOUT  
RL  
50  
VCC - 2V  
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION  
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination  
voltage ofV - 2V.  
CC  
For logic high, VOUT = V  
= V  
– 0.9V  
OH_MAX  
CC_MAX  
)
= 0.9V  
OH_MAX  
(V  
- V  
CCO_MAX  
For logic low, VOUT = V  
= V  
– 1.7V  
OL_MAX  
CC_MAX  
)
= 1.7V  
OL_MAX  
(V  
- V  
CCO_MAX  
Pd_H is power dissipation when the output drives high.  
Pd_L is the power dissipation when the output drives low.  
))  
Pd_H = [(V  
– (V  
- 2V))/R ] * (V  
- V  
) = [(2V - (V  
- V  
/R ] * (V  
- V  
) =  
OH_MAX  
CC_MAX  
CC_MAX  
OH_MAX  
_MAX  
OH_MAX  
CC_MAX  
OH_MAX  
CC  
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mWL  
))  
Pd_L = [(V  
– (V  
- 2V))/R ] * (V  
- V  
) = [(2V - (V  
- V  
/R ] * (V  
- V  
) =  
OL_MAX  
CC_MAX  
CC_MAX  
OL_MAX  
_MAX  
OL_MAX  
CC_MAX  
OL_MAX  
L
CC  
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW  
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
RELIABILITY INFORMATION  
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP  
θJA byVelocity (Meters per Second)  
0
1
2.5  
89.8°C/W  
Multi-Layer PCB, JEDEC Standard Test Boards  
101.7°C/W  
90.5°C/W  
TRANSISTOR COUNT  
The transistor count for ICS843011 is: 2436  
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REV. B JULY 26, 2010  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP  
TABLE 8. PACKAGE DIMENSIONS  
Millimeters  
SYMBOL  
Minimum  
Maximum  
N
A
8
--  
1.20  
0.15  
1.05  
0.30  
0.20  
3.10  
A1  
A2  
b
0.05  
0.80  
0.19  
0.09  
2.90  
c
D
E
6.40 BASIC  
0.65 BASIC  
E1  
e
4.30  
4.50  
L
0.45  
0°  
0.75  
8°  
α
aaa  
--  
0.10  
Reference Document: JEDEC Publication 95, MO-153  
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REV. B JULY 26, 2010  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
TABLE 9. ORDERING INFORMATION  
Part/Order Number  
843011AG  
Marking  
3011A  
3011A  
011AL  
011AL  
Package  
Shipping Package  
tube  
Temperature  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
8 lead TSSOP  
843011AGT  
8 lead TSSOP  
2500 tape & reel  
tube  
843011AGLF  
843011AGLFT  
8 lead "Lead-Free" TSSOP  
8 lead "Lead-Free" TSSOP  
2500 tape & reel  
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc.(IDT) assumes no responsibility for either its use or for infringement of  
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial  
applications.Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves  
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
REVISION HISTORY SHEET  
Rev  
B
B
Table  
3A  
T9  
Page  
3
12  
Description of Change  
Date  
8/23/04  
10/13/04  
Power Supply DC Characteristics Table - added ICCA spec.  
Ordering Information Table - corrected count from 154 to 100.  
Ordering Information Table - corrected Lead-Free marking from 3011AL to  
011AL.  
Changed ambient operating temperature bullet from -30°C to 85°C to  
-40°C to 85°C and throughout data sheet.  
B
T9  
12  
1
10/20/04  
12/10/04  
B
6
7
Crystal Input Interface - changed capacitor C2 value from 27p to 22p.  
Application Schematic - corrected schematic to reflect Crystal Input Interface  
change.  
T9  
T9  
12  
Ordering Information Table - deleted tube count in Shipping Packaging  
column.  
Updated datasheet's header/footer with IDT from ICS.  
Removed ICS prefix from Part/Order Number column.  
Added Contact Page.  
B
B
1/26/07  
7/26/10  
12  
14  
843011AG  
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REV. B JULY 26, 2010  
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ICS843011  
FEMTOCLOCKS™ CRYSTAL-TO-  
3.3V LVPECL CLOCK GENERATOR  
We’ve Got Your Timing Solution.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
Sales  
Tech Support  
netcom@idt.com  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
Fax: 408-284-2775  
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.  
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of  
their respective owners.  
Printed in USA  
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REV. B JULY 26, 2010  
14  

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