8430252CG-45 [IDT]
Clock Generator, 156.25MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16;
| 型号： | 8430252CG-45 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 156.25MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总17页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FemtoClock® Crystal-to-
3.3V LVPECL Frequency Synthesizer
ICS8430252-45
GENERAL DESCRIPTION
FEATURES
The ICS8430252-45 is a 2 output LVPECL and LVCMOS/LVTTL
Synthesizer optimized to generate Ethernet reference clock
frequencies . Using a 25MHz, 18pF parallel resonant crystal,
the following fre-quencies can be generated: 156.25MHz
LVPECL output and, 125MHz LVCMOS output. The 8430252-
• One differential 3.3V LVPECL output and
One LVCMOS/LVTTL output
• Crystal oscillator interface designed for a 25MHz,
18pF parallel resonant crystal
rd
45 uses IDT’s 3 generation low phase noise VCO technology
• A 25MHz crystal generates both an output frequency of
156.25MHz (LVPECL) and 125MHz (LVCMOS)
and can achieve 1ps or lower typical rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS8430252-45 is
packaged in a small 16-pin TSSOP package.
• VCO frequency: 625MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz) using
a 25MHz crystal: 0.39ps (typical)
• Full 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
PIN ASSIGNMENT
BLOCK DIAGRAM
Pullup
OE
1
2
3
4
5
6
7
8
OE
VEE
QA
16
15
14
13
12
11
10
9
CLK_EN
VEE
QB
25MHz
QA
÷5
XTAL_IN
VCCO_A
nc
nc
VCCA
VCC
nQB
Phase
Detector
VCO
VCCO_B
XTAL_IN
XTAL_OUT
VEE
OSC
625MHz
QB
XTAL_OUT
÷4
nQB
Feedback Divider
÷25
ICS8430252-45
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
Pullup
CLK_EN
G Package
Top View
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ICS8430252-45
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
Output enable pin. LVCMOS/LVTTL interface levels.
See Table 3A Function Table.
1
OE
Input
2, 9, 15
VEE
QA
Power
Output
Power
Negative supply pin.
LVCMOS/LVTTL clock output.
Output supply pin for QA output.
No connect.
3
4
VCCO_A
nc
5, 6
7
Unused
Power
Power
VCCA
VCC
Analog supply pin.
8
Core supply pin.
XTAL_OUT,
XTAL_IN
10, 11
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
12
VCCO_B
Power
Output
Output supply pin for QB, nQB outputs.
13, 14
nQB, QB
Differential clock outputs. LVPECL interface levels.
Clock enable pin. LVCMOS/LVTTL interface levels.
See Table 3B Function Table.
16
CLK_EN
Input
Pullup
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
VCC, VCCA, VCCO_A, VCCO_B = 3.465V
VCCO_A = 3.3V
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
kΩ
Ω
CPD
Power Dissipation Capacitance
Input Pullup Resistor
18
51
20
RPULLUP
ROUT
Output Impedance
QA
TABLE 3A. OE SELECT FUNCTION TABLE
Input
OE
0
Output
QA
Hi-Z
1
Active
TABLE 3B. CLK_EN SELECT FUNCTION TABLE
Input
Outputs
CLK_EN
QB
nQB
High
0
1
Low
Active
Active
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FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
89°C/W (0 lfpm)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum Typical Maximum Units
Core Supply Voltage
Analog Supply Voltage
3.135
VCC – 0.10
3.135
3.3
3.3
3.3
3.465
VCC
V
V
VCCA
VCCO_A, VCCO_B Output Supply Voltage
3.465
95
V
IEE
Power Supply Current
Analog Supply Current
mA
mA
ICCA
10
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VCC + 0.3
V
V
Input Low Voltage
-0.3
0.8
5
Input High Current OE, CLK_EN
Input Low Current OE, CLK_EN
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VCC = VIN = 3.465V
IIL
VCC = 3.465V, VIN = 0V
-150
2.6
VOH
VOL
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VCCO_A/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_B = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
VCCO_B - 1.4
VCCO_B - 2.0
0.6
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO_B - 0.9
VCCO_B - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_B - 2V.
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FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
25
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A, VCCO_B = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
156.25
125
MHz
MHz
ps
fOUT
Output Frequency Range
QA
125MHz (1.875MHz - 20MHz)
0.41
RMS Phase Jitter
(Random); NOTE 1
tjit(Ø)
tR / tF
odc
QB, nQB
QA
156.25MHz (1.875MHz - 20MHz)
0.39
ps
500
300
47
1200
700
53
ps
Output
20ꢀ to 80ꢀ
Rise/Fall Time
QB, nQB
QA
ps
ꢀ
Output Duty Cycle
QB, nQB
48
52
ꢀ
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE 1: Please refer to the Phase Noise Plots.
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FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
TYPICAL PHASE NOISE AT 156.25MHZ
0
-10
-20
10Gb Ethernet Filter
-30
-40
-50
-60
-70
-80
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.39ps (typical)
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Raw Phase Noise Data
Phase Noise Result by adding
10Gb Ethernet Filterto raw data
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 125MHZ
0
-10
10Gb Ethernet Filter
-20
-30
125MHz
RMS Phase Jitter (Random)
-40
-50
1.875Mhz to 20MHz = 0.41ps (typical)
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Raw Phase Noise Data
Phase Noise Result by adding
10Gb Ethernet Filterto raw data
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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ICS8430252-45
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
PARAMETER MEASUREMENT INFORMATION
2V
1.65V 5ꢀ
2V
1.65V 5ꢀ
SCOPE
SCOPE
VCC
,
VCC
,
Qx
VCCO_B
VCCO_B
VCCA
VCCA
Qx
LVCMOS
GND
LVPECL
nQx
VEE
-1.3V 0.165V
-1.65V 5ꢀ
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
VCCO_LVCMOS
2
QA
tPW
Phase Noise Mask
tPERIOD
tPW
odc =
x 100ꢀ
Offset Frequency
f1
f2
tPERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQB
QB
80ꢀ
tF
80ꢀ
tR
tPW
tPERIOD
20ꢀ
20ꢀ
QA
tPW
odc =
x 100ꢀ
tPERIOD
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT RISE/FALL TIME
nQB
QB
LVPECL OUTPUT RISE/FALL TIME
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ICS8430252-45
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430252-45 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_X
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin.To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUT:
SELECT PINS:
All select pins have internal pull-ups and pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CRYSTAL INPUT INTERFACE
The ICS8430252-45 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
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ICS8430252-45
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
OVER-DRIVING THE CRYSTAL INTERFACE
signal in half. This can be done in one of two ways. First, R1
and R2 in parallel should equal the transmission line imped-
ance. For most 50Ω applications, R1 and R2 can be 100Ω. This
can also be accomplished by removing R1 and changing R2 to
50Ω. The values of the resistors can be increased to reduce the
loading for slower and weaker LVCMOS driver. Figure 3B
shows an example of the interface diagram for an LVPECL
driver. This is a standard LVPECL termination with one side of
the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though
some components might not be used, they can be utilized for
debugging purposes. The datasheet specifications are charac-
terized and guaranteed by using a quartz crystal as the input.
The XTAL_IN input can be overdriven by an LVCMOS driver or
by one side of a differential driver through an AC coupling
capacitor. The XTAL_OUT pin can be left floating. The amplitude
of the input signal should be between 500mV and 1.8V and the
slew rate should not be less than 2V/nS. For 3.3V LVCMOS
inputs, the amplitude must be reduced from full swing to at
least half the swing in order to prevent signal interference with
the power rail and to reduce internal noise. Figure 3A shows an
example of the interface diagram for a high speed 3.3V
LVCMOS driver. This configuration requires that the sum of the
output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the
VCC
XTAL_OUT
R1
100
C1
Rs
Zo = 50 ohms
Ro
XTAL_IN
.1uf
R2
100
Zo = Ro + Rs
LVCMOS Driver
FIGURE 3A. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
XTAL_OUT
C2
Zo = 50 ohms
XTAL_IN
.1uf
Zo = 50 ohms
R1
50
R2
50
LVPECL Driver
R3
50
FIGURE 3B. GENERAL DIAGRAM FOR LVPECL DRIVER TO XTAL INPUT INTERFACE
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ICS8430252-45
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
puts are designed to drive 50Ω transmission lines. Matched
impedance techniques should be used to maximize operat-
ing frequency and minimize signal distortion. Figures 4A
and 4B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers
simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
The differential outputs are low impedance follower out-
puts that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground) or
current sources must be used for functionality. These out-
3.3V
R3
R4
125Ω
125Ω
3.3V
3.3V
Z
Z
o = 50Ω
+
_
LVPECL
Input
o = 50Ω
R1
84Ω
R2
84Ω
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUTT ERMINATION
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ICS8430252-45
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
LAYOUT GUIDELINE
Figure 5 shows an example of ICS8430252-45 application
schematic. In this example, the device is operated at VCC=3.3V.
The 18pF parallel resonant 25MHz crystal is used.The C1 = 22pF
and C2 = 22pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. Two examples of LVPECL and
one example of LVCMOS terminations are shown in this
schematic. Additional termination approaches are shown in the
LVPECL Termination Application Note.
R6
33
Zo = 50
QA
LVCMOS
3.3V
R1
133
R2
133
Zo = 50 Ohm
QB
U1
TL1
+
-
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Zo = 50 Ohm
OE
VEE
QA
VCCO_A
nc
nc
CLK_EN
VEE
QB
nQB
VCCO_B
XTAL_IN
XTAL_OU T
VEE
nQB
VCCO_A
VCCO_B
C7
TL2
0.1u
C4
0.1u
R3
82.5
R4
82.5
VCCA
VCC
VCC
VCC
R5
VCCA
10
C3
0.1u
C1
22pF
C5
0.1u
ICS8430252-45
C6
10u
Zo = 50 Ohm
X1 25MHz
18pF
+
-
Zo = 50 Ohm
VCC=3.3V
C2
VDDO_A=3.3V
VDDO_B=3.3V
Logic Input Pin Examples
Set Logic
22pF
R7
50
R8
50
Set Logic
Input to
'0'
VCC
VCC
Input to
'1'
R9
50
Optional
LVPECL
Y-Termination
RU1
1K
RU2
Not Install
To Logic
Input
pins
To Logic
Input
pins
RD1
Not Install
RD2
1K
FIGURE 5. ICS8430252-45 SCHEMATIC EXAMPLE
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ICS8430252-45
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430252-45.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430252-45 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 95mA = 329.17mW
EE_MAX
MAX
CC_MAX
(95mA includes the LVCMOS output terminated with 50Ω to V /2 at 125MHz)
CC
Power (outputs) = 30mW/Loaded Output pair
MAX
Total Power
(3.465V, with all outputs switching) = 329.17mW + 30mW = 359.17mW
_MAX
2. Junction Temperature.
Junction temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The maximum
recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the
bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming a
JA
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.359W * 81.8°C/W = 99.4°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 16-PIN TSSOP, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 0.9V
CC_MAX
OUT
OH_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
CC
OH_MAX
CC_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
CC
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8430252-45 is: 2070
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FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS8430252CG-45
www.idt.com
REV ISION A FEBRUARY 19, 2014
14
ICS8430252-45
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
TABLE 10. ORDERING INFORMATION
Part/Order Number
8430252CG-45
Marking
30252C45
30252C45
0252C45L
0252C45L
Package
Shipping Packaging Temperature
16 Lead TSSOP
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
8430252CG-45T
8430252CG-45LF
8430252CG-45LFT
16 Lead TSSOP
tape & reel
tube
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
ICS8430252CG-45
www.idt.com
REV ISION A FEBRUARY 19, 2014
15
ICS8430252-45
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Added Schematic Layout and Guideline.
Date
A
9
10/4/06
1
4
General Description - deleted HiperClocks logo and text reference.
AC Characteristics Table - added thermal note.
T6
8
9
15
Updated Over-Driving the Crystal Interface section.
A
2/19/14
Termination for 3.3V LVPECL Outputs - updated Figures 4A and 4B.
Ordering Information Table - deleted ICS prefix in Part/Order column. And
deleted tape & reel count in Shipping Packaging column.
T10
ICS8430252CG-45
www.idt.com
REV ISION A FEBRUARY 19, 2014
16
ICS8430252-45
FemtoClock® Crystal-to-3.3V LVPECL Frequency Synthesizer
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
www.IDT.com/go/contactIDT
© 2014 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are
trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and
marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
8430252CGI-45T
Clock Generator, 156.25MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
IDT
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