843034DY-06LF [IDT]
Clock Generator, 375MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-48;
| 型号： | 843034DY-06LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 375MHz, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026, LQFP-48 时钟 外围集成电路 晶体 |
| 文件： | 总21页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCKS™ MULTI-RATE 3.3V
LVPECL FREQUENCY SYNTHESIZER
ICS843034-06
GENERAL DESCRIPTION
FEATURES
The ICS843034-06 is a general purpose, low phase
• Dual differential 3.3V LVPECL outputs
ICS
noise LVPECL synthesizer which can generate
• 4:1 Input Mux:
HiPerClockS™
frequencies for a wide variety of applications. The
ICS843034-06 has a 4:1 input multiplexer from which
the following inputs can be selected: one differential
input, one single-ended input, or one of two crystal
One differential input
One single-ended input
Two crystal oscillator interfaces
oscillators, thus making the device ideal for frequency translation
or frequency generation. The ICS843034-06 has dual LVPECL
outputs that may be programmed for ÷2, ÷4 or ÷5 of the VCO
frequency. The ICS843034-06 also supplies a buffered copy of
the reference clock or crystal frequency on the single-ended
REF_OUT pin which can be enabled or disabled (disabled by
default). The output frequency can be programmed using either
a serial or parallel programming interface. This device supports
Spread Spectrum Clocking (SSC) for EMI reduction.
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 112MHz to 375MHz
• Crystal input frequency range: 12MHz to 40MHz
• VCO range: 560MHz to 750MHz
• Supports Spread Spectrum Clocking (SSC)
• Parallel or serial interface for programming feedback divider
and output dividers
• RMS phase jitter at 166.6MHz, using a 22.222MHz crystal
(12kHz to 20MHz): 1.3ps (typical), SSC - Off
• 3.3V supply mode
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
Pullup
OE_A
÷
÷
÷
001
011
100
2
4
5
Pullup
VCO_SEL
XTAL_IN0
FOUTA0
nFOUTA0
PIN ASSIGNMENT
00
01
OSC
OSC
Pullup
XTAL_OUT0
XTAL_IN1
0
1
VCCO_A
XTAL_OUT1
Phase
Detector
VCO
CLK
nCLK
VCCO_B
10
11
Pullup/Pulldown
FOUTB0
nFOUTB0
Pulldown
48 47 46 45 44 43 42 41 40 39 38 37
REF_CLK
÷M
XTAL_OUT1
XTAL_IN1
XTAL_OUT0
XTAL_IN0
REF_CLK
SEL1
M8
RESERVED
RESERVED
RESERVED
OE_REF
OE_A
1
36
Pulldown
Pulldown
SEL1
SEL0
2
35
34
33
32
31
30
29
28
27
26
25
3
4
ICS843034-06
Pullup
OE_B
MR
5
VCCO_REF
REF_OUT
48-Pin LQFP
7mm x 7mm x 1.4mm
package body
Pulldown
6
SEL0
OE_B
7
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
OE_REF
S_LOAD
VCCA
VCC
8
Y Package
Top View
S_LOAD
S_DATA
S_CLOCK
MR
NA0
9
TEST
S_DATA
NA1
10
11
12
Configuration
Interface
Logic
S_CLOCK
NA2
nP_LOAD
M8:M0
VEE
M0:M4 M6:M8 Pulldown, M5 Pullup
13 14 15 16 17 18 19 20 21 22 23 24
NA2 Pulldown, NA1:0 Pullup
NA2:NA0
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
™
IDT / ICS™ 3.3V LVPECLFREQUENCY SYNTHESIZER
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ICS843034DY-06 REV. C JANUARY 14, 2008
ICS843034-06
FEMTOCLOCKS™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes opera-
tion using a 22.22MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 6, NOTE 1.
automatically occur during power-up. The TEST output is LOW
when operating in the parallel input mode. The relationship
between the VCO frequency, the crystal frequency and the M
divider is defined as follows: fVCO = fxtal x M
The ICS843034-06 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 22.22MHz crystal provides a 22.22MHz phase de-
tector reference frequency. The VCO of the PLL operates over
a range of 560MHz to 750MHz. The output of the M divider is
also applied to the phase detector.
The M value and the required values of M0 through M8 are shown
in Table 4B to program the VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 22.22MHz ref-
erence are defined as 26 ≤ M ≤ 33. The frequency out is defined
as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and NA output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide
and NA output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider and NA output
divider on each rising edge of S_CLOCK. The serial mode can
be used to program the M and NA bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the
TEST output as follows:
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The ICS843034-06 supports either serial or parallel programming
modes to program the M feedback divider and N output divider.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on the M and
NA inputs are passed directly to the M divider and N output divid-
ers. On the LOW-to-HIGH transition of the nP_LOAD input, the
data is latched and the M and N dividers remain loaded until the
next LOW transition on nP_LOAD or until a serial event occurs.
As a result, the M and NA bits can be hardwired to set the M
divider and NA output divider to a specific default state that will
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data, Shift Register Output
Output of M divider
Same frequency as FOUTA0
S
ERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
SSC3 SSC2 SSC1 SSC0 T1
tS tH
T0
X
X
X
NA2 NA1 NA0
M8
M7
M6
M5
M4
M3
M2
M1
M0
nP_LOAD
tS
P
ARALLEL
L
OADING
M0:M8, NA0:NA2
nP_LOAD
M, N
t
t
H
S
S_LOAD
Time
NOTE: X = Don’t Care
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
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FEMTOCLOCKS™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. SSM OPERATION
SS Bit Pattern
Operation
SS3
0
SS2
0
SS1
0
SS0
0
Mode
%
off
0
0
0
0
1
center
center
center
center
center
center
center
off
±0.25
±0.25
±0.85
±0.85
±1.45
±1.45
±1.7
0
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
down
down
down
down
down
down
down
-0.25
-0.25
-0.85
-0.85
-1.45
-1.45
-1.7
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
NOTE: SS modulation frequency is approximately 32kHz using
reference frequency of 22.22MHz, providing a VCO frequency of
666.66MHz.
SPREAD SPECTRUM MODULATION
The ICS843034-06 offers the option of a spread spectrum
modulated output clock. The spread spectrum is controlled via
4 bits in the serial bit stream. These four bits configure the
SSM to be enabled and the amount of spread modulation to be
selected. See Table 1 for the definition of the four bits. The four
bits are added at the beginning of the serial data stream and
are labeled SS3, SS2, SS1 and SS0. The initial state of SS3,
SS2, SS1 and SS0 is 0, 0, 0, 0 which places the ICS843034-06
in the mode of spread spectrum off. Additionally, a parallel load
will result in spread spectrum modulation being off. The
ICS843034-06 offers down-spread or center-spread using tri-
angle-wave modulation. NOTE: PLL operation not guaranteed
for M >31 when using center spread.
POWER-UP OPERATION
MR PIN OPERATION
The 843034-06 has internal power–up reset circuitry that initiates
the phase lock loop to automatically acquire lock on power-up.
On power-up the M/N values for the feedback and output dividers
will be acquired from the M and N pins if nP_Load is held Low. If
nP_Load is High during power-up, M/N values are indeterminate.
The M/N values may be changed by either changing the values
on the M/N pins when nP_LOAD is low or with a serial load when
nP_LOAD is high and S_LOAD is low.
Any time there is a change in the input frequency, either due to
an external change or a change in the SEL pins, the MR pin must
go high and low to relock to the new input frequency. A change in
the M feedback divider by either a serial or parallel load will also
cause a relock to the new input frequency.
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IDT / ICS™ 3.3V LVPECLFREQUENCY SYNTHESIZER
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ICS843034DY-06 REV. C JANUARY 14, 2008
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FEMTOCLOCKS™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 2. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 41, 42,
43, 44,
45, 47, 48
M8, M0, M1,
M2, M3,
M4, M6, M7
M divider input. Data latched on LOW-to-HIGH transition of
nP_LOAD input. LVCMOS/LVTTL interface levels.
Input
Pulldown
2, 3, 4
RESERVED
Reserve
Input
Reserve pins.
Output enable. Controls enabling and disabling of REF_OUT output.
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTA0,
nFOUTA0 outputs. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB0,
nFOUTB0 outputs. LVCMOS/LVTTL interface levels.
5
OE_REF
Pulldown
Pullup
6
7
OE_A
OE_B
Input
Input
Pullup
8, 14
9, 10
11
VCC
NA0, NA1
NA2
Power
Input
Core supply pins.
Pullup
Determines output divider value as defined in Table 4C,
Function Table. LVCMOS/LVTTL interface levels.
Input
Pulldown
12, 24
VEE
Power
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
13
TEST
Output
LVCMOS/LVTTL interface levels.
FOUTA0,
nFOUTA0
15, 16
17
Output
Power
Output
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTA0, nFOUTA0.
VCCO_A
FOUTB0,
nFOUTB0
18, 19
Differential output for the synthesizer. LVPECL interface levels.
20
21
22
23
VCCO_B
REF_OUT
VCCO_REF
nc
Power
Output
Power
Output supply pin for FOUTB0, nFOUTB0.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_OUT output.
No connect.
Unused
Active High Master Reset. When logic HIGH, forces the internal PLL
to a reset condition which holds the VCO at the minumum value.
25
MR
Input
Pulldown When logic LOW, the internal dividers and the outputs are enabled.
Assertion of MR does not affect loaded M, N, S and T values.
LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
26
27
28
S_CLOCK
S_DATA
Input
Input
Input
Pulldown
Pulldown
S_LOAD
Pulldown
29
30, 31
32
VCCA
Power
Input
Input
Analog supply pin.
SEL0, SEL1
REF_CLK
Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
XTAL_IN0,
XTAL_OUT0
XTAL_IN1,
Crystal oscillator interface. XTAL_IN0 is the input,
XTAL_OUT0 is the output.
Crystal oscillator interface. XTAL_IN1 is the input,
XTAL_OUT1 is the output.
33, 34
35, 36
Input
Input
XTAL_OUT1
Continued on next page...
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IDT / ICS™ 3.3V LVPECLFREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 2. PIN DESCRIPTIONS, CONTINUED
Number
Name
Type
Description
37
CLK
Input Pulldown Non-inverting differential clock input.
Pullup/
38
nCLK
Input
Inverting differential clock input.VCC/2 default when left floating.
Pulldown
Parallel load input. Determines when data present at M8:M0 is loaded into
39
nP_LOAD
Input Pulldown M divider, and when data present at NA2:NA0 is loaded into the N output
dividers. LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
40
46
VCO_SEL
M5
Input
Input
Pullup
Pullup
M divider input. Data latched on LOW-to-HIGH transition of nP_LOAD input.
LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
Ω
RPULLUP
51
51
7
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
REF_OUT
5
12
™
IDT / ICS™ 3.3V LVPECLFREQUENCY SYNTHESIZER
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ICS843034DY-06 REV. C JANUARY 14, 2008
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FEMTOCLOCKS™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 4A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset the PLL.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 4B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
1
8
M3
1
4
M2
0
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Divide
577.7
•
26
•
•
•
•
•
•
•
•
•
•
666.6
•
30
•
0
0
0
0
1
1
1
1
0
•
•
•
•
•
•
•
•
•
733.3
33
0
0
0
1
0
0
0
0
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal, CLK, or REF_CLK input frequency of
22.22MHz.
TABLE 4C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
*NA2
*NA1
*NA0
Minimum
280
Maximum
375
0
0
1
0
1
0
1
1
0
2
4
5
140
187.5
150
112
*NOTE: Programming for Bank A and Bank B.
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FEMTOCLOCKS™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Supply Voltage, V
4.6V
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, VO (LVCMOS)
-0.5V to VCCO + 0.5V
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 65.7°C/W (0 mps)
Storage Temperature, T -65°C to 150°C
STG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = VCCO_REF = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
Core Supply Voltage
3.465
VCC
V
V
VCCA
Analog Supply Voltage
VCC – 0.17
3.3
VCCO_A,
VCCO_B,
VCCO_REF
Output Supply Voltage
3.135
3.3
3.465
V
IEE
Power Supply Current
Analog Supply Current
190
17
mA
mA
ICCA
TABLE 5B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = VCCO_REF = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VCC + 0.3
0.8
Units
VIH
VIL
Input High Voltage
Input Low Voltage
REF_CLK, MR,
2
V
V
-0.3
SEL[1:0], OE_REF,
S_CLOCK, S_DATA,
S_LOAD, nP_LOAD,
NA2, M1:M4, M6:M8
V
CC = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
OE_A, M5, OE_B,
VCO_SEL, NA0, NA1
VCC = VIN = 3.465V
REF_CLK, MR,
SEL[1:0], OE_REF,
S_CLOCK, S_DATA,
S_LOAD, nP_LOAD,
NA2, M1:M4, M6:M8
VCC = 3.465V,
VIN = 0V
-5
Input
Low Current
IIL
V
CC = 3.465V,
VIN = 0V
OE_A, M5, OE_B,
VCO_SEL, NA0, NA1
-150
µA
TEST; NOTE 1
REF_OUT
2.6
V
V
Output
High Voltage
VOH
VCCO_REF = 3.3V±5%
VCCO_REF = 3.3V±5%
VCCO_REF - 0.3V
TEST; NOTE 1
REF_OUT
0.5
0.4
V
V
Output
Low Voltage
VOL
NOTE 1: Outputs terminated with 50Ω to V
/2. See Parameter Measurement Information Section,
CCO_X
“Output Load Test Circuit Diagrams.
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FEMTOCLOCKS™ MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 5C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.465V
Minimum Typical Maximum Units
nCLK
CLK
150
150
µA
µA
µA
µA
V
VIN = VCC = 3.465V
nCLK
CLK
VIN = 0V, VCC = 3.465V
VIN = 0V, VCC = 3.465V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage; NOTE 1
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5D. LVPECL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO_A, VCCO_B - 2V.
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
XTAL_IN0/XTAL_OUT0,
XTAL_IN1/XTAL_OUT1
12
12
40
MHz
fIN
Input Frequency
CLK/nCLK, REF_CLK
S_CLOCK
40
50
MHz
MHz
Input Rise/Fall
Time
tR/tF
REF_CLK
5
ns
NOTE: For the input crystal, CLK/nCLK and REF_CLK frequency range, the M value must be set for the VCO to operate
within the 560MHz to 750MHz range. Using the minimum input frequency of 12MHz, valid values of M are 47 ≤ M ≤ 62.
Using the maximum frequency of 40MHz, valid values of M are 14 ≤ M ≤ 18.
TABLE 7. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
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IDT / ICS™ 3.3V LVPECLFREQUENCY SYNTHESIZER
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PRELIMINARY
TABLE 8. AC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = VCCO_REF = 3.3V±5%, VEE = 0V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
112
375
MHz
166.6MHz,
Integration Range:
12kHz - 20MHz
Phase Jitter, RMS (Random), SSC-Off
NOTE 1, 2
tjit(Ø)
1.3
ps
tjit(cc)
tsk(o)
Cycle-to-Cycle Jitter; NOTE 3, 4
Output Skew; NOTE 2, 4, 5
35
ps
ps
100
Output
tR / tF
LVPECL Outputs
Rise/Fall Time
20% to 80%
200
700
ps
M, N to nP_LOAD
5
5
ns
ns
ns
ns
ns
ns
%
tS
Setup Time
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
tH
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
odc
Output Duty Cycle
PLL Lock Time
45
55
tLOCK
100
ms
NOTE: Characterized using a 22.22MHz crystal producing a VCO frequency of 666.66MHz, unless otherwise noted.
NOTE: See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Characterized with REF_OUT output disabled.
NOTE 3: Jitter performance using XTAL inputs.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
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PRELIMINARY
TYPICAL PHASE NOISE AT 166.6MHZ
Filter
166.6MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 1.3ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
a Filter to raw data
OFFSET FREQUENCY (HZ)
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PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
2V
V
VCC
SCOPE
,
Qx
V
V
V
CC
CCO_A,
CCA
nCLK
CLK
CCO__B
VPP
VCMR
Cross Points
LVPECL
nQx
VEE
VEE
-1.3V ± 0.165V
DIFFERENTIAL INPUT LEVELS
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
nFOUTx
FOUTx
nFOUTA0
nFOUTB0
FOUTA0
FOUTB0
nFOUTy
➤
➤
➤
tcycle n
tcycle n+1
➤
FOUTy
tjit(cc) = tcycle n – tcycle n+1
tsk(o)
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nFOUTA0
80%
tF
80%
FOUTA0
tPW
20%
20%
tPERIOD
Clock
Outputs
tR
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
LVCMOS OUTPUT RISE/FALL TIME
80%
80%
tR
VSWING
20%
Clock
Outputs
20%
tF
LVPECL OUTPUT RISE/FALL TIME
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PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843034-06 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VCC, VCCA and VCCO_x should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation is
required. Figure 2 illustrates how a 10Ω resistor along with a
10µF and a 0.01µF bypass capacitor should be connected to
each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10µF
FIGURE 2. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LVCMOS/LVTTL LEVELS
Figure 3 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias CcCircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 3. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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PRELIMINARY
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4D show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 4A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
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PRELIMINARY
CRYSTAL INPUT INTERFACE
The ICS843034-06 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 5 below were determined using a 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum
C1 and C2 values can be slightly adjusted for different board
layouts.
XTAL_OUT
XTAL_IN
C1
18p
X1
18pF Parallel Crystal
C2
22p
FIGURE 5. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance.In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 6. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_I N
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 6. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
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PRELIMINARY
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUTS
OUTPUTS:
LVCMOS OUTPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK/nCLK INPUTS
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
REF_CLK INPUT
For applications not requiring the use of the reference clock, it
can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUT
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 7A and 7B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board de-
signers simulate to guarantee compatibility across all printed cir-
cuit and clock component process variations.
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUTx and nFOUTx are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 7A. LVPECL OUTPUT TERMINATION
FIGURE 7B. LVPECL OUTPUT TERMINATION
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843034-06.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843034-06 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
·
·
Power (core) = V
* I
= 3.465V * 190mA = 658.35mW
MAX
CC_MAX
EE_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
(3.465V, with all outputs switching) = 658.35mW + 60mW = 718.35mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 65.7°C/W per Table 9 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.718W * 65.7°C/W = 117.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 9. THERMAL RESISTANCE θ FOR 48-PIN LQFP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
65.7°C/W
55.9°C/W
52.4°C/W
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PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 8.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 8. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CCO_MAX
)
= 0.9V
OH_MAX
(V
– V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
– V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
– V
– V
/R ] * (V
– V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
/R ] * (V
– V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 10. θ VS. AIR FLOW TABLE FOR 48 LEAD LQFP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
65.7°C/W
55.9°C/W
52.4°C/W
TRANSISTOR COUNT
The transistor count for ICS843034-06 is: 7846
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PRELIMINARY
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0
°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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TABLE 12. ORDERING INFORMATION
Part/Order Number
843034DY-06LF
Marking
Package
Shipping Packaging
tray
Temperature
ICS43034D06L
ICS43034D06L
48 Lead "Lead-Free" LQFP
48 Lead "Lead-Free" LQFP
0°C to 70°C
0°C to 70°C
843034DY-06LFT
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
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PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
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+65 6 887 5505
England
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo and HiPerClockS are trademarks of
Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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