843207AY-350LFT [IDT]
Clock Generator;
| 型号： | 843207AY-350LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总16页 (文件大小：3411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL
350MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843207-350
GENERAL DESCRIPTION
FEATURES
• Seven independently configurable LVPECL outputs at
87.5MHz, 175MHz or 350MHz
The ICS843207-350 is a low phase-noise
ICS
HiPerClockS™
frequency margining synthesizer that targets
clocking for high performance interfaces such
as SPI4.2 and is a member of the HiPerClockS™
family of high performance clock solutions from
• Individual tri-state control of each output
• Selectable crystal oscillator interface designed for 14MHz,
18pF parallel resonant crystal or LVCMOS single-ended input
IDT. In the default mode, the each output can be configured
individually to generate an 87.5MHz, 175MHZ or 350MHz
LVPECL output clock signal from a 14MHz crystal input.
There is also a frequency margining mode available where
the device can be configured, using control pins, to vary
the output frequency up or down from nominal by 5%. The
ICS843207-350 is provided in a 48-pin LQFP package.
• Output frequency can be varied 5% from nominal
• VCO range: 620MHz - 750MHz
• RMS phase jitter @ 350MHz, using a 14MHz crystal
(12kHz - 20MHz): 1.29ps (typical)
• Full 3.3V output supply mode
• 0°C to 70°C ambient operating temperature
PIN ASSIGNMENT
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
48 47 46 45 44 43 42 41 40 39 38 37
1
VCCA
VCC
VCCO
nQ6
Q6
VCCO
Q0
36
35
34
33
2
Q0
00 HiZ
01 ÷2
10 ÷8
11 ÷4
nQ0
Q1
3
BLOCK DIAGRAM
ICS843207-350
4
nQ0
nQ1
VEE
VCCO
Q2
5
32
31
30
48-Pin LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Pullup
Pullup
Pullup
Pullup
2
2
SEL[1:0]
VEE
6
7
VCCO
nQ5
Q5
Q1
00 HiZ
01 ÷2
10 ÷8
11 ÷4
8
29
28
27
Top View
nQ2
Q3
9
nQ1
10
11
12
nQ4
Q4
nQ3
VCCO
SEL[3:2]
26
25
VCCO
13 14 15 16 17 18 19 20 21 22 23 24
Q2
00 HiZ
01 ÷2
10 ÷8
11 ÷4
nQ2
2
2
2
SEL[5:4]
Pulldown
nPLL_SEL
XTAL_IN
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q3
14MHz
1
0
nQ3
OSC
0
1
SEL[7:6]
Phase
Detector
Predivider
÷2
VCO
XTAL_OUT
REF_CLK
620 - 750MHz
Q4
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Pulldown
nQ4
Pulldown
Pullup
Pullup
Pullup
nXTAL_SEL
÷100
(÷95, ÷105)
SEL[9:8]
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q5
nQ5
Pulldown
Pulldown
Pulldown
MODE
2
SEL[11:10]
MARGIN
00 HiZ
01 ÷2
10 ÷8
11 ÷4
Q6
To O/P Dividers
MR
nQ6
2
SEL[13:12]
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
FUNCTIONAL DESCRIPTION
pin to change the M feedback divider. Frequency margining
mode operation occurs when the MODE input is HIGH. The
phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. The output of the VCO is scaled by
an output divider prior to being sent to the LVPECL output
buffer. The divider provides a 50% output duty cycle. The
relationship between the crystal input frequency, the M divider,
the VCO frequency and the output frequency is provided in
Table 1A. When changing back from frequency margining
mode to nominal mode, the device will return to the default
nominal configuration described above.
The ICS843207-350 features a fully integrated PLL and
therefore requires no external components for setting the loop
bandwidth. A 14MHz fundamental crystal is used as the input
to the on chip oscillator. The output of the oscillator is fed into
the pre-divider. In frequency margining mode, the 14MHz
crystal frequency is divided by 2 and a 7MHz reference
frequency is applied to the phase detector. The VCO of the
PLL operates over a range of 620MHz to 800MHz. The output
of the M divider is also applied to the phase detector. The
default mode for the ICS843207-350 is a nominal 350MHz with
each output configurable to divide by 1, 2 or 4. The nominal
output frequency can be changed by placing the device into
the margining mode using the mode pin and using the margin
TABLE 1A. FREQUENCY SELECT FUNCTION TABLE
XTAL (MHz)
SELx
SELx-1
VCO (MHz)
700
Output Divider
Output Frequency (MHz)
14
14
14
14
0
0
1
1
0
1
0
1
N/A
2
HiZ
350
87.5
175
700
700
8
700
4
TABLE 1B. FREQUENCY MARGIN FUNCTION TABLE
Reference
Frequency (MHz)
Feedback
Divider
MODE
MARGIN XTAL (MHz)
Pre-Divider (P)
VCO (MHz)
% Change
1
0
1
0
X
1
14
14
14
2
1
2
7
95
665
700
735
-5.0
Nom. Mode
5.0
14
7
100
105
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
TABLE 2. PIN DESCRIPTIONS
Number
Name
Type
Type
Description
Description
1, 7, 12,
25, 30, 34
VCCO
Power
Output supply pins.
2, 3
4, 5
Q0, nQ0
Q1, nQ1
VEE
Ouput
Ouput
Power
Ouput
Ouput
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Negative supply pins.
6, 16, 31
8, 9
Q2, nQ2
Q3, nQ3
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
10, 11
MODE pin. LOW = default mode. HIGH = frequency margining mode.
See Table 4B. LVCMOS/LVTTL interface levels.
Sets the frequency margin to 5% in frequency margining mode.
See Table 1B. LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
13
14
MODE
Margin
Input
Input
Pulldown
Pulldown
Pulldown
15
MR
Input
17
18
REF_CLK
Input
Input
Pulldown Reference input clock. LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the crystal and the reference clock
nXTAL_SEL
Pulldown
inputs. LVCMOS/LVTTL interface levels.
19,
20
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Input
21, 35
VCC
Power
Core supply pins.
PLL select pin. When HIGH, PLL is bypassed and input is fed directly
Pulldown to the output dividers. When LOW, PLL is enabled.
LVCMOS/LVTTL interface levels.
22
nPLL_SEL
Input
Input
23, 24,
37, 38,
39, 40,
41, 42,
43, 44,
45, 46,
47, 48
SEL0, SEL1,
SEL2, SEL3,
SEL4, SEL5,
SEL6, SEL7,
SEL8, SEL9,
SEL10, SEL11,
SEL12, SEL13
Output divider select pins. See Table 1A.
Pullup
LVCMOS/LVTTL interface levels.
26, 27
28, 29
32, 33
36
Q4, nQ4
Q5, nQ5
Q6, nQ6
VCCA
Ouput
Ouput
Ouput
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Analog supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pulldown Resistor
51
51
TABLE 4A. nXTAL_SEL CONTROL INPUT FUNCTION TABLE
Input
TABLE 4B. MODE CONTROL INPUT FUNCTION TABLE
Input
Condition
Q0:Q6, nQ0:Q6
MODE
nXTAL_SEL
Selected Source
XTAL_IN, XTAL_OUT
REF_CLK
0
1
Default Mode
0
1
Frequency Margining Mode
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
VCC
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
VCC – 0.15
3.135
3.3
3.3
3.465
220
V
mA
mA
ICCA
15
TABLE 5B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VCC = 3.3V
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
VCC = 3.3V
-0.3
REF_CLK, MARGIN,
MODE, nPLL_SEL,
MR, nXTAL_SEL
VCC = VIN = 3.465
150
5
µA
µA
µA
Input
High Current
IIH
SEL0:SEL13
VCC = VIN = 3.465
REF_CLK, MARGIN,
MODE, nPLL_SEL,
MR, nXTAL_SEL
V
CC = 3.465V,
VIN = 0V
-5
Input
Low Current
IIL
VCC = 3.465V,
VIN = 0V
SEL0:SEL13
-150
µA
Input Transistion
Rise/Fall Rate
∆t/∆v
SEL0:SEL13, MODE
20
ns/v
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
TABLE 5C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
14
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
40
7
pF
300
µW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 7. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
REF_CLK
12.4
12.4
14
14
15
15
MHz
MHz
Input
fIN
Frequency
XTAL_IN/XTAL_OUT
TABLE 8. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
N = ÷2
Minimum
310
Typical
350
Maximum Units
375
MHz
MHz
MHz
fOUT
Output Frequency
N = ÷4
155
175
187.5
93.75
N = ÷8
77.5
87.5
Mode = LOW
350MHz, (12kHz - 20MHz)
Mode = LOW
175MHz, (12kHz - 20MHz)
Mode = LOW
87.5MHz, (12kHz - 20MHz)
1.29
1.34
1.46
ps
ps
ps
RMS Phase Jitter,
Random; NOTE 1
tjit(Ø)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
425
50
ps
%
NOTE 1: Characterized using a 14MHz crystal.
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
TYPICAL PHASE NOISE AT 175MHZ
10 Gigabit Ethernet Filter
175MHz
RMS Phase Noise Jitter
12kHz to 20MHz = 1.34ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 350MHZ
10 Gigabit Ethernet Filter
350MHz
RMS Phase Noise Jitter
12kHz to 20MHz = 1.29ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
10 Gigabit Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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ICS843207AY-350 REV A OCTOBER 19, 2006
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FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
2V
Phase Noise Plot
SCOPE
VCC
VCCO
,
Qx
VCCA
Phase Noise Mask
LVPECL
nQx
VEE
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.3V 0.165V
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0:nQ6
80%
tF
80%
tR
Q0:Q6
VSWING
20%
tPW
Clock
Outputs
20%
tPERIOD
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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ICS843207AY-350 REV A OCTOBER 19, 2006
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FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843207-350 provides
3.3V
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VCC, VCCA, and VCCO should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin.To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
VCC
.01µF
.01µF
10Ω
VCCA
10µF
capacitor should be connected to each VCCA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843207-350 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using a 14MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can
be left floating. The input edge rate can be as slow as
10ns. For LVCMOS inputs, it is recommended that the
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to
reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal
in half. This can be done in one of two ways. First, R1 and R2 in
parallel should equal the transmission line impedance. For most
50Ω applications, R1 and R2 can be 100Ω. This can also be
accomplished by removing R1 and making R2 50Ω.
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVPECL OUTPUT
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating fre-
quency and minimize signal distortion. Figures 4A and 4B
show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 4A. LVPECL OUTPUT TERMINATION
FIGURE 4B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843207-350.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843207-350 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 220mA = 762.3mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 7 * 30mW = 210mW
Total Power
(3.63V, with all outputs switching) = 762.3mW + 210mW = 972.3mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 9 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.972W *42.1°C/W = 110.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 9. THERMAL RESISTANCE θ FOR 48-PIN LQFP, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
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PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
CCO_MAX
OUT
OH_MAX
(V
- V
) = 0.9V
CCO_MAX
OH_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
12
ICS843207AY-350 REV A OCTOBER 19, 2006
ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 10. θ VS. AIR FLOW TABLE FOR 48 LEAD LQFP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843207-350 is: 4380
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
13
ICS843207AY-350 REV A OCTOBER 19, 2006
ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
14
ICS843207AY-350 REV A OCTOBER 19, 2006
ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
TABLE 12. ORDERING INFORMATION
Part/Order Number
ICS843207AY-350
Marking
Package
Shipping Packaging
tray
Temperature
43207A350
43207A350
3207A350L
3207A350L
48 Lead LQFP
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS843207AY-350T
ICS843207AY-350LF
ICS843207AY-350LFT
48 Lead LQFP
1000 tape & reel
tray
48 Lead "Lead-Free" LQFP
48 Lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ LVPECL FREQUENCY MARGINING SYNTHESIZER
15
ICS843207AY-350 REV A OCTOBER 19, 2006
ICS843207-350
FEMTOCLOCKS™ CRYSTAL-TO-LVPECL 350MHZ FREQUENCY MARGINING SYNTHESIZER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
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800-345-7015
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+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
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