84329AVT_技术文档

ICS84329

Integrated

Circuit

Systems, Inc.

700MH , LOW JITTER, CRYSTAL-TO-3.3V

Z

D

IFFERENTIAL LVPECL FREQUENCY

SYNTHESIZER

GENERAL DESCRIPTION

FEATURES

The ICS84329 is a general purpose, single output • Fully integrated PLL, no external loop filter requirements

ICS

high frequency synthesizer and a member of the

HiPerClockS™ family of High Performance Clock

• Series resonant crystal oscillator interface

Solutions from ICS. The VCO operates at a fre-

• 1 differential 3.3V LVPECL output

HiPerClockS™

• Output frequency range: 25MHz to 700MHz

• VCO range: 200MHz to 700MHz

• Parallel interface for programming counter

and output dividers during power-up

quency range of 200MHz to 700MHz. The VCO

frequency is programmed in steps equal to the value of the

crystal frequency divided by 16.TheVCO and output frequency

can be programmed using the serial or parallel interfaces to the

configuration logic.The output can be configured to divide the

VCO frequency by 1, 2, 4, and 8. Output frequency steps as

small as 125KHz to 1MHz can be achieved using a 16MHz

crystal depending on the output dividers.

• Serial 3 wire interface

• RMS Period jitter: 5.5ps (maximum)

• Cycle-to-cycle jitter: 35ps (maximum)

• 3.3V supply voltage

• 0°C to 70°C ambient operating temperature

• Lead-Free package fully RoHS compliant

• Pin compatible with the MC12429

PIN ASSIGNMENT

BLOCK DIAGRAM

OE

25 24 23 22 21 20 19

S_CLOCK

26

18

N1

N0

M8

M7

M6

M5

M4

XTAL_IN

OSC

XTAL_OUT

S_DATA

S_LOAD

V^CCA

27

28

1

17

16

15

14

13

12

ICS84329

28-Lead PLCC

V Package

÷ 16

nc

2

11.6mm x 11.4mm x 4.1mm

TopView

nc

3

4

XTAL_IN

PLL

PHASE DETECTOR

÷1

÷2

÷4

÷8

5

6

7

8

9 10 11

1

0

FOUT

nFOUT

VCO

÷ M

S_LOAD

S_DATA

S_CLOCK

nP_LOAD

CONFIGURATION

INTERFACE

LOGIC

TEST

32 31 30 29 28 27 26 25

24

1

2

3

4

5

6

7

8

S_CLOCK

S_DATA

S_LOAD

VCCA

nc

M0:M8

N0:N1

23

22

21

20

19

18

17

N1

N0

M8

M7

M6

M5

M4

ICS84329

32-Lead LQFP

Y package

VCCA

7mm x 7mm x 1.4mm

TopView

nc

XTAL_IN

9

10 11 12 13 14 15 16

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

1

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

FUNCTIONAL DESCRIPTION

latched and the M divider remains loaded until the next LOW

transition on nP_LOAD or until a serial event occurs.The TEST

output is Mode 000 (shift register out) when operating in the

parallel input mode.The relationship between theVCO frequency,

the crystal frequency and the M divider is defined as follows:

NOTE: The functional description that follows describes op-

eration using a 16MHz crystal. Valid PLL loop divider values

for different crystal or input frequencies are defined in the In-

put Frequency Characteristics, Table 6, NOTE 1.

The ICS84329 features a fully integrated PLL and therefore

requires no external components for setting the loop band-

width. A series-resonant, fundamental crystal is used as the

input to the on-chip oscillator. The output of the oscillator is

divided by 16 prior to the phase detector.With a 16MHz crys-

tal this provides a 1MHz reference frequency.The VCO of the

PLL operates over a range of 200MHz to 700MHz.The output

of the M divider is also applied to the phase detector.

fxtal

16

x

fVCO =

M

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Function

Table. Valid M values for which the PLL will achieve lock are

defined as 200 ≤ M ≤ 511. The frequency out is defined as

follows:

fVCO fxtal

M

N

fout

x

=

The phase detector and the M divider force the VCO output fre-

quency to be M times the reference frequency by adjusting the

VCO control voltage. Note that for some values of M (either too

high or too low), the PLL will not achieve lock.The output of the

VCO is scaled by a divider prior to being sent to each of the

LVPECL output buffers.The divider provides a 50% output duty

cycle.

N

16

Serial operation occurs when nP_LOAD is HIGH and S_LOAD

is LOW. The shift register is loaded by sampling the S_DATA

bits with the rising edge of S_CLOCK. The contents of the

shift register are loaded into the M divider when S_LOAD tran-

sitions from LOW-to-HIGH.The M divide and N output divide

values are latched on the HIGH-to-LOW transition of S_LOAD.

If S_LOAD is held HIGH, data at the S_DATA input is passed

directly to the M divider on each rising edge of S_CLOCK.

The serial mode can be used to program the M and N bits and

test bitsT2:T0.The internal registers T2:T0 determine the state

of the TEST output as follows:

The programmable features of the ICS84329 support two input

modes to program the M divider and N output divider.The two

input operational modes are parallel and serial. Figure 1 shows

the timing diagram for each mode. In parallel mode the nP_LOAD

input is LOW.The data on inputs M0 through M8 and N0 through

N1 is passed directly to the M divider and N output divider. On

the LOW-to-HIGH transition of the nP_LOAD input, the data is

T2

0

T1

0

T0

0

1

TEST Output

Shift Register Out

High

fOUT

0

1

0

1

PLL Reference Xtal ÷ 16

VCO ÷ M

(non 50% Duty M divider)

fOUT

1

0

fOUT

LVCMOS Output Frequency < 200MHz

1

0

1

0

Low

S_CLOCK ÷ M

(non 50% Duty Cycle M divider)

S_CLOCK ÷ N divider

1

fOUT ÷ 4

fOUT

SERIAL LOADING

S_CLOCK

T2

T1

T0

N1

N0

M8 M7 M6 M5 M4 M3 M2 M1 M0

S_DATA

S_LOAD

nP_LOAD

t

H

S

t

S

PARALLEL LOADING

M, N

M0:M8, N0:N1

nP_LOAD

t

H

Time

S

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

www.icst.com/products/hiperclocks.html

84329AV

REV. D DECEMBER 15, 2004

2

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

TABLE 1. PIN DESCRIPTIONS

Name

Type

Description

V_CCA

Power

Analog supply pin.

XTAL_IN,

XTAL_OUT

Input

Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.

Output enable. When logic HIGH, the outputs are enabled (default).

When logic LOW, the outputs are disabled and drive differential low:

FOUT = LOW, nFOUT = HIGH. LVCMOS / LVTTL interface levels.

Parallel load input. Determines when data present at M8:M0 is loaded into

M divider, and when data present at N1:N0 sets the N output divide value.

LVCMOS / LVTTL interface levels.

M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input.

LVCMOS / LVTTL interface levels.

Determines N output divider value as defined in Table 3C Function Table.

LVCMOS / LVTTL interface levels.

OE

Input

Pullup

nP_LOAD

Input

Pullup

M0, M1, M2, M3,

M4, M5, M6, M7, M8

Pullup

N0, N1

V_EE

Input

Power

Output

Negative supply pins.

Test output which is used in the serial mode of operation.

LVCMOS / LVTTL interface levels.

TEST

V_CC

Power

Output

Core supply pins.

nFOUT, FOUT

Differential output for the synthesizer. 3.3V LVPECL interface levels.

Clocks the serial data present at S_DATA input into the shift register on the

rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.

Shift register serial input. Data sampled on the rising edge of S_CLOCK.

LVCMOS / LVTTL interface levels.

Controls transition of data from shift register into the M divider.

LVCMOS / LVTTL interface levels.

S_CLOCK

S_DATA

Input

Pulldown

S_LOAD

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

C_IN

Parameter

Test Conditions

Minimum Typical Maximum Units

Input Capacitance

Input Pullup Resistor

4

pF

KΩ

R_PULLUP

51

R_PULLDOWNInput Pulldown Resistor

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

3

ICS84329

Integrated

Circuit

Systems, Inc.

700MH , LOW JITTER, CRYSTAL-TO-3.3V

Z

D

IFFERENTIAL LVPECL FREQUENCY

SYNTHESIZER

TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE

Inputs

Conditions

nP_LOAD

M

N

S_LOAD S_CLOCK S_DATA

X

Reset. M and N bits are all set HIGH.

Data on M and N inputs passed directly to M divider and

N output divider. TEST mode 000.

L

↑

Data Data

X

Data is latched into input registers and remains loaded

until next LOW transition or until a serial event occurs.

Serial input mode. Shift register is loaded with data on

S_DATA on each rising edge of S_CLOCK.

Contents of the shift register are passed to the M divider

and N output divider.

X

L

↑

X

↑

L

X

H

X

Data

H

X

↓

L

Data

X

M divide and N output divide values are latched.

Parallel or serial input do not affect shift registers.

L

X

NOTE: L = LOW

H = HIGH

X = Don't care

↑ = Rising edge transition

↓= Falling edge transition

TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE

256

M8

0

128

M7

1

64

M6

1

32

M5

0

16

M4

0

8

M3

1

4

M2

0

2

M1

0

1

M0

0

VCO Frequency

(MHz)

M Divide

200

201

202

203

•

200

201

202

203

•

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

•

509

510

511

509

510

511

1

0

1

0

1

NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.

TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE

Inputs

Output Frequency (MHz)

N Divider Value

N1

0

N0

0

Minimum

200

Maximum

700

1

2

4

8

0

1

100

350

1

0

50

175

1

25

87.5

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

4

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

ABSOLUTE MAXIMUM RATINGS

SupplyVoltage, V

4.6V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device.These ratings are stress specifications only.Functional

operation of product at these conditions or any conditions be-

yond those listed in the DC Characteristics or AC Character-

istics is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

CC

Inputs, V

-0.5V to V_CC+ 0.5V

I

Outputs, I_O

Continuous Current

Surge Current

50mA

100mA

PackageThermal Impedance, θ

For 28 Lead PLCC

For 32 Lead LQFP

JA

37.8°C/W (0 lfpm)

47.9°C/W (0 lfpm)

StorageTemperature, T

-65°C to 150°C

STG

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_CC= V_CCA= 3.3V 5%, TA = 0°C TO 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V_CC

V_CCA

I_CC

Core Supply Voltage

3.135

3.3

3.465

125

V

Analog Supply Voltage

Power Supply Current

Analog Supply Current

V

mA

I_CCA

15

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V_CC= V_CCA= 3.3V 5%, TA = 0°C TO 70°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

V_IH

V_IL

Input High Voltage

2

V_CC+ 0.3

0.8

V

Input Low Voltage

Input High Current

-0.3

M0-M8, N0, N1,

OE, nP_LOAD

S_LOAD,

S_DATA, S_CLOCK

M0-M8, N0, N1,

OE, nP_LOAD

S_LOAD,

V

_CC= V_IN= 3.465V

V_CC= V_IN= 3.465V

_CC= 3.465V, V_IN= 0V

5

µA

I_IH

150

V

-150

I_IL

Input Low Current

V_CC= 3.465V, V_IN= 0V

-5

S_DATA, S_CLOCK

V_OH

V_OL

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

2.6

V

0.5

NOTE 1: Outputs terminated with 50Ω to V_CC/2. See Parameter Measurement Information, "3.3V Output Load Test Circuit".

TABLE 4C. LVPECL DC CHARACTERISTICS, V_CC= V_CCA= 3.3V 5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

V_CC- 1.4

V_CC- 2.0

0.6

Typical Maximum Units

V_OH

Output High Voltage; NOTE 1

V_CC- 1.0

V_CC- 1.7

0.95

V

V_OL

Output Low Voltage; NOTE 1

V_SWING

Peak-to-Peak Output Voltage Swing

NOTE 1: Outputs terminated with 50Ω to V_CC- 2V.

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

5

ICS84329

Integrated

Circuit

Systems, Inc.

700MH , LOW JITTER, CRYSTAL-TO-3.3V

Z

D

IFFERENTIAL LVPECL FREQUENCY

SYNTHESIZER

TABLE 5. CRYSTAL CHARACTERISTICS

Parameter

Test Conditions

Minimum Typical Maximum

Fundamental

Units

Mode of Oscillation

Frequency

10

25

70

7

MHz

Ω

Equivalent Series Resistance (ESR)

Shunt Capacitance

pF

TABLE 6. INPUT FREQUENCY CHARACTERISTICS, V_CC= V_CCA= 3.3V 5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

MHz

XTAL; NOTE 1

10

17

25

50

f_IN

Input Frequency XTAL; NOTE 1, 2

S_CLOCK

NOTE 1: For the crystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency

range of 200MHz or 700MHz. Using the minimum frequency of 10MHz valid values of M are 320 ≤ M ≤ 511.

Using the maximum frequency of 25MHz valid values of M are 128 ≤ M ≤ 448.

NOTE 2: For crystal frequencies greater than 17MHz, a series tuning capacitor is required for proper operation.

For more information, please refer to the Application Information, "Crystal Input and Oscillator Interface".

TABLE 7. AC CHARACTERISTICS, V_CC= V_CCA= 3.3V 5%, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

F_OUT

Output Frequency

700

5.5

12

MHz

ps

fOUT ≥ 65MHz

fOUT < 65MHz

fOUT ≥ 50MHz

fOUT < 50MHz

20% to 80%

tjit(per)

Period Jitter, RMS; NOTE 1, 2

Cycle-to-Cycle Jitter; NOTE 1, 2

ps

35

ps

tjit(cc)

50

ps

t_R/ t_F

t_S

Output Rise/Fall Time

Setup Time

300

5

800

ps

ns

t_H

Hold Time

5

ns

t_L

PLL Lock Time

Output Duty Cycle

10

55

ms

%

odc

45

50

See Parameter Measurement Information section.

Characterized using a 16MHz XTAL.

NOTE 1: This parameter is defined in accordance with JEDEC Standard 65

NOTE 2: See Applications section.

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

6

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

PARAMETER MEASUREMENT INFORMATION

2V

SCOPE

nFOUT

V_CC

V_CCA

,

Qx

FOUT

LVPECL

V_EE

➤

tcycle n

tcycle n+1

➤

nQx

t

jit(cc) =

t

cycle n –

tcycle n+1

1000 Cycles

-1.3V 0.165V

3.3V OUTPUT LOAD AC TEST CIRCUIT

CYCLE-TO-CYCLE JITTER

V_OH

nFOUT

FOUT

V_REF

Pulse Width

t_PERIOD

V_OL

1σ contains 68.26% of all measurements

2σ contains 95.4% of all measurements

3σ contains 99.73% of all measurements

4σ contains 99.99366% of all measurements

6σ contains (100-1.973x10^-7)% of all measurements

t_PW

odc =

t_PERIOD

Histogram

Reference Point

(Trigger Edge)

Mean Period

(First edge after trigger)

PERIOD JITTER

OUTPUT

D

UTY

C

YCLE/PULSE

WIDTH/PERIOD

S_DATA

80%

t_HOLD

S_CLOCK

V_SWING

20%

t_SET-UP

Clock

20%

Outputs

S_LOAD

t_F

t_R

t_SET-UP

M0:M8

N0:N1

t_HOLD

nP_LOAD

t_SET-UP

OUTPUT RISE/FALL TIME

SETUP AND

H

OLD

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

7

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

APPLICATION INFORMATION

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS84329 provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V_CCand V_CCA

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 2 illustrates how

a 10Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V_CCApin.

3.3V

V_CC

.01µF

10Ω

V_CCA

10µF

FIGURE 2. POWER SUPPLY FILTERING

TERMINATION FOR LVPECL OUTPUTS

The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques

tion for LVPECL outputs.The two different layouts mentioned should be used to maximize operating frequency and minimize

are recommended only as guidelines.

signal distortion. Figures 3A and 3B show two different layouts

which are recommended only as guidelines. Other suitable clock

FOUT and nFOUT are low impedance follower outputs that layouts may exist and it would be recommended that the board

generate ECL/LVPECL compatible outputs.Therefore, terminat- designers simulate to guarantee compatibility across all printed

ing resistors (DC current path to ground) or current sources circuit and clock component process variations.

must be used for functionality. These outputs are designed to

3.3V

Z_o= 50Ω

125Ω

FOUT

FIN

Z_o= 50Ω

FOUT

FIN

50Ω

V_CC- 2V

1

RTT =

Z_o

RTT

((V_OH+ V_OL) / (V_CC– 2)) – 2

84Ω

FIGURE 3A. LVPECL OUTPUT TERMINATION

FIGURE 3B. LVPECL OUTPUT TERMINATION

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

8

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

14

12

10

8

6

4

2

0

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525

Output Frequency (MHz)

FIGURE 4A. RMS JITTER VS. fOUT (using a 16MHz XTAL)

60

50

40

30

20

10

0

25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525

Output Frequency (MHz)

FIGURE 4B. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL)

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

9

ICS84329

Integrated

Circuit

Systems, Inc.

700MH , LOW JITTER, CRYSTAL-TO-3.3V

Z

D

IFFERENTIAL LVPECL FREQUENCY

SYNTHESIZER

CRYSTAL INPUT AND OSCILLATOR INTERFACE

The ICS84329 features an internal oscillator that uses an external

quartz crystal as the source of its reference frequency. The

oscillator is a series resonant, multi-vibrator type design. This

design provides better stability and eliminates the need for large

on chip capacitors.Though a series resonant crystal is preferred,

a parallel resonant crystal can be used. A parallel resonant mode

crystal used in a series resonant circuit will exhibit a frequency

of oscillation a few hundred ppm lower than specified. A few

hundred ppm translates to KHz inaccuracy.In general computing

applications, this level of inaccuracy is irrelevant. If better ppm

accuracy is required, an external capacitor can be added to a

quartz crystal in series to XTAL_IN. Figure 5A shows how to

interface with a crystal.

ICS84329

XTAL_OUT

XTAL_IN

Figures 5A and 5B show various crystal parameters which are

recommended only as guidelines. Figure 5A shows how to inter-

face a capacitor with a parallel resonant crystal. Figure 5B shows

the capacitor value needed for the optimum ppm performance

over various series resonant crystal frequencies. For IA64/32

platforms which required a Raltron Parallel Resonant Quartz

crystal part #AS-16.66-18-SMD-T-M1, a 7pF series capacitor can

be used to better the ppm accuracy.

FIGURE 5A. CRYSTAL INTERFACE

NOTE:For crystal frequencies higher than 17MHz,

a series tuning capacitor is required for proper operation.

FIGURE 5B. Recommended tuning capacitance for various series

resonant crystals.

30

10.000

25

12.000

20

14.318

15

10

5

16.000

20.000

24.000

0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

Series Resonant Crystal Frequency (MHz)

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

10

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

LAYOUT GUIDELINE

The schematic of the ICS84329 layout example used in this

layout guideline is shown in Figure6A.The ICS84329 recommended density of the components, the density of the traces, and the stack

actual system will depend on the selected component types, the

up of the P.C.board.

PCB board layout for this example is shown in Figure 6B. This

layout example is used as a general guideline. The layout in the

C3

22p

16MHz,18pF

X1

VCC

VCC=3.3V

C4

22p

R7

10

SP = Space (i.e. not intstalled)

M4

12

4

M4

13

XTALIN

3

M5

M6

M7

M8

N2

N1

M[8:0]= 110010000 (400)

N[1:0] =01 (Divide by 2)

M5

14

nc

2

M6

15

nc

1

VCCA

M7

16

VCCA

28

M8

17

S_LOAD

27

N0

18

S_DATA

26

C11

0.01u

C16

10u

N1

S_CLOCK

U1

84329AV

C1

VCC

0.1uF

Zo = 50 Ohm

Fout = 200 MHz

RU0

SP

RU1

SP

RU7

1K

RU8

1K

RU9

SP

RU10

1K

RU11

SP

RU12

1K

C2

0.1u

Zo = 50 Ohm

R2

50

R1

50

RD0

1K

RD1

1K

RD7

SP

RD8

SP

RD9

1K

RD10

SP

RD6

1K

RD12

SP

R3

50

FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

11

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

• The differential 50Ω output traces should have the

same length.

The following component footprints are used in this layout

example:

• Avoid sharp angles on the clock trace.Sharp angle

turns cause the characteristic impedance to change on

the transmission lines.

All the resistors and capacitors are size 0603.

POWER AND GROUNDING

Place the decoupling capacitors C1, C2 and C3, as close as

possible to the power pins. If space allows, placement of the

decoupling capacitor on the component side is preferred. This

can reduce unwanted inductance between the decoupling

capacitor and the power pin caused by the via.

• Keep the clock traces on the same layer.Whenever pos-

sible, avoid placing vias on the clock traces. Placement

of vias on the traces can affect the trace characteristic

impedance and hence degrade signal integrity.

• To prevent cross talk, avoid routing other signal traces in

parallel with the clock traces. If running parallel traces is

unavoidable, allow a separation of at least three trace

widths between the differential clock trace and the other

signal trace.

Maximize the power and ground pad sizes and number of vias

capacitors.This can reduce the inductance between the power

and ground planes and the component power and ground pins.

The RC filter consisting of R7, C11, and C16 should be placed

as close to the V_CCApin as possible.

• Make sure no other signal traces are routed between the

clock trace pair.

CLOCK TRACES AND TERMINATION

• The matching termination resistors should be located as

close to the receiver input pins as possible.

Poor signal integrity can degrade the system performance or

cause system failure. In synchronous high-speed digital systems,

the clock signal is less tolerant to poor signal integrity than other

signals. Any ringing on the rising or falling edge or excessive ring

back can cause system failure. The shape of the trace and the

trace delay might be restricted by the available space on the board

and the component location.While routing the traces, the clock

signal traces should be routed first and should be locked prior to

routing other signal traces.

CRYSTAL

The crystal X1 should be located as close as possible to the pins

4 (XTAL_IN) and 5 (XTAL_IN).The trace length between the X1

and U1 should be kept to a minimum to avoid unwanted parasitic

inductance and capacitance. Other signal traces should not be

routed near the crystal traces.

X1

U1

GND

VCC

PIN 2

C16

C11

R7

VCCA

VIA

PIN 1

VCCA

Signals

Traces

C1

C2

50 Ohm

Traces

FIGURE 6B. PCB BOARD LAYOUT FOR ICS84329

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

12

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the ICS84329.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS84329 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_CC= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core)_MAX= V_{CC_MAX}* I_{EE_MAX}= 3.465V * 140mA = 485mW

Power (outputs)_MAX= 30.2mW/Loaded Output pair

If all outputs are loaded, the total power is 1 * 30.2mW = 30.2mW

Total Power_{_MAX}(3.465V, with all outputs switching) = 485mW + 30.2mW = 515.2mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device.The maximum recommended junction temperature for HiPerClockS^TMdevices is 125°C.

The equation for Tj is as follows: Tj = θ_JA* Pd_total + T_A

Tj = JunctionTemperature

θ_JA= Junction-to-AmbientThermal Resistance

Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)

T_A= AmbientTemperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JAmust be used. Assuming a

moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W perTable 8A below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.515W * 31.1°C/W = 86°C. This is well below the limit of 125°C.

This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,

and the type of board (single layer or multi-layer).

TABLE 8A. THERMAL RESISTANCE θ_JAFOR 28-PIN PLCC, FORCED CONVECTION

θ_JAbyVelocity (Linear Feet per Minute)

0

200

500

Multi-Layer PCB, JEDEC Standard Test Boards

37.8°C/W

31.1°C/W

28.3°C/W

NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.

TABLE 8B. THERMAL R^ESISTANCEθ_JAFOR 32-PIN LQFP, FORCED CONVECTION

θ_JAbyVelocity (Linear Feet per Minute)

0

200

500

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

67.8°C/W

55.9°C/W

50.1°C/W

47.9°C/W

42.1°C/W

39.4°C/W

NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

13

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

3. Calculations and Equations.

The purpose of this section is to derive the power dissipated into the load.

LVPECL output driver circuit and termination are shown in the Figure 7.

V_CC

Q1

V_OUT

RL

50

V_CC- 2V

FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination

voltage ofV - 2V.

CC

•

For logic high, V_OUT= V

= V

– 1.0V

OH_MAX

CC_MAX

)

= 1.0V

OH_MAX

(V

- V

CC_MAX

For logic low, V_OUT= V

= V

– 1.7V

OL_MAX

CC_MAX

)

= 1.7V

OL_MAX

(V

- V

CC_MAX

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

))

Pd_H = [(V

– (V

- 2V))/R ] * (V

- V

) = [(2V - (V

- V

/R ] * (V

- V

) =

OH_MAX

CC_MAX

OH_MAX

_MAX

OH_MAX

CC_MAX

OH_MAX

L

CC

L

[(2V - 1V)/50Ω] * 1V = 20.0mW

Pd_L = [(V – (V - 2V))/R ] * (V

))

- V

) = [(2V - (V

- V

/R ] * (V

- V

) =

OL_MAX

CC_MAX

OL_MAX

_MAX

OL_MAX

CC_MAX

OL_MAX

L

CC

L

[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

14

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

RELIABILITY INFORMATION

TABLE 9A. θ_JAVS. AIR FLOW TABLE FOR 28 LEAD PLCC

θ_JAbyVelocity (Linear Feet per Minute)

0

200

500

Multi-Layer PCB, JEDEC Standard Test Boards

37.8°C/W

31.1°C/W

28.3°C/W

NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.

TABLE 9B. θ_JAVS. AIR FLOW TABLE FOR 32 LEAD LQFP

θ_JAbyVelocity (Linear Feet per Minute)

0

200

55.9°C/W

42.1°C/W

500

50.1°C/W

39.4°C/W

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

67.8°C/W

47.9°C/W

NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for ICS84329 is: 4408

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

15

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC

TABLE 10A. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

SYMBOL

MINIMUM

MAXIMUM

N

A

28

4.19

2.29

4.57

3.05

A1

A2

b

1.57

2.11

0.33

0.53

c

0.19

0.32

D

12.32

11.43

4.85

12.57

11.58

5.56

D1

D2

E

12.32

11.43

4.85

12.57

11.58

5.56

E1

E2

Reference Document: JEDEC Publication 95, MS-018

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

16

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP

TABLE 10B. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

BBA

SYMBOL

MINIMUM

NOMINAL

MAXIMUM

N

A

32

--

1.60

0.15

1.45

0.45

0.20

A1

A2

b

0.05

1.35

0.30

0.09

1.40

0.37

c

--

D

9.00 BASIC

7.00 BASIC

5.60 Ref.

9.00 BASIC

7.00 BASIC

5.60 Ref.

0.80 BASIC

0.60

D1

D2

E

E1

E2

e

L

0.45

0.75

θ

--

0°

7°

ccc

--

0.10

Reference Document: JEDEC Publication 95, MS-026

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

17

ICS84329

Integrated

Circuit

Systems, Inc.

700MH

Z

, LOW

J

ITTER, CRYSTAL

-TO-3.3V

D

IFFERENTIAL LVPECL FREQUENCY YNTHESIZER

S

TABLE 11. ORDERING INFORMATION

Part/Order Number

ICS84329AV

Marking

Package

Count

38 per Tube

500

Temperature

0°C to 70°C

ICS84329AV

28 Lead PLCC

ICS84329AVT

ICS84329AVLF

ICS84329AVLFT

ICS84329AY

28 Lead PLCC on Tape and Reel

28 Lead "Lead Free" PLCC

ICS84329AVLF

38 per Tube

500

ICS84329AVLF 28 Lead "Lead Free" PLCC on Tape and Reel

ICS84329AY

32 Lead LQFP

250 per Tray

1000

ICS84329AYT

32 Lead LQFP on Tape and Reel

The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are

not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS

product for use in life support devices or critical medical instruments.

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

18

ICS84329

Integrated

Circuit

Systems, Inc.

700MH , LOW JITTER, CRYSTAL-TO-3.3V

Z

D

IFFERENTIAL LVPECL FREQUENCY

SYNTHESIZER

REVISION HISTORY SHEET

Description of Change

Rev

Table

Page

12

2

Date

A

Added Crystal Input and Oscillator Interface section.

Updated Parallel & Serial Load Operations diagram.

Changed V_CCand crystal descriptions.

03/15/02

A

B

T1

3

12/18/02

1/24/03

Updated format.

Figure 1 - switched S_CLOCK and S_DATA labels.

2

5

T4A

Power Supply Table - changed I_EEPower Supply Current, 110mA Max. to

I_CCPower Supply Current, 125mA Max.

Power Considerations - changed I_{EE_MAX}110mA to 140mA to correspond with

Table 4A Power Supply Table.

Pin Description Table - added description to OE pin.

Added LVCMOS/LVTTL... to S_DATA pin description.

Block Diagram, replaced ÷N with dividers.

13

3

T1

T6

B

C

1/29/03

4/3/03

1

6

Changed 25MHz max. limit to 17MHz max.

Added extra XTAL line with limits of 17MHz min. to 25MHz max.

Added Note 2.

10

Crystal Input & Oscillator Interface section, added same crystal frequency note.

Changed XTAL1 to XTAL_IN and XTAL2 to XTAL_OUT throughout the data

sheet.

T1

3

5

Pin Characteristics Table - changed C_INfrom 4pF max. to 4pF typical.

Absolute Maximum Ratings - revised Outputs rating.

Updated LVPECL Output Termination drawings.

D

6/15/04

8

11

18

1

Updated Schematic Layout.

Ordering Information Table - add "Lead Free" part numbers.

Features Section - added "Series resonant" to crystal bullet.

12/15/04

84329AV

www.icst.com/products/hiperclocks.html

REV. D DECEMBER 15, 2004

19


型号：	84329AVT
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Clock Generator, PQCC28
文件：	总19页 (文件大小：279K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

84329AVT [IDT]

相关型号：

84329AY

84329BM-01

84329BM-01LF

84329BM-01LFT

84329BM-01T

84329BV

84329BV-01

84329BV-01LF

84329BV-01LFT

84329BV-01T

84329BVLF

84329BVLFT