844004AGT [IDT]
Clock Generator;
| 型号： | 844004AGT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator |
| 文件： | 总13页 (文件大小：1037K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
ICS844004
GENERAL DESCRIPTION
FEATURES
The ICS844004 is a 4 output LVDS Synthesizer
• Four LVDS outputs
ICS
HiPerClockS™
optimized to generate Fibre Channel reference
clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from IDT. Using a 26.5625MHz 18pF
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz,
53.125MHz
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz
and 53.125MHz. The ICS844004 uses IDT’s 3rd generation
low phase noise VCO technology and can achieve <1ps typical
rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS844004 is packaged in a small 24-pin
TSSOP package.
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.65ps (typical)
• Full 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
FREQUENCY SELECT FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Output
Frequency
(MHz)
nQ1
Q1
1
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Input
M Divider N Divider M/N Divider
Value
2
Q2
Frequency F_SEL1 F_SEL0
(MHz)
3
4
VDDo
Q0
VDDO
Q3
Value
Value
26.5625
26.5625
26.5625
26.5625
26.04166
23.4375
0
0
1
1
0
0
0
1
0
1
1
0
24
24
24
24
24
24
3
4
8
6
4
2
6
8
212.5
159.375
106.25
53.125
156.25
187.5
5
6
7
8
nQ0
MR
nPLL_SEL
nc
nQ3
GND
nc
6
nXTAL_SEL
9
VDDA
TEST_CLK
GND
XTAL_IN
XTAL_OUT
12
4
10
11
12
F_SEL0
VDD
F_SEL1
3
ICS844004
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
BLOCK DIAGRAM
Pulldown
2
F_SEL[1:0]
G Package
Top View
Pulldown
nPLL_SEL
Q0
F_SEL[1:0]
0 0 ÷3
nQ0
Pulldown
TEST_CLK
1
0
1
0
0 1 ÷4
Q1
26.5625MHz
XTAL_IN
1 0 ÷6
VCO
637.5MHz
(w/26.5625MHz
Reference)
1 1 ÷12
nQ1
Phase
Detector
OSC
XTAL_OUT
Q2
Pulldown
nXTAL_SEL
nQ2
M = 24 (fixed)
Q3
nQ3
Pulldown
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product
characterization.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844004AG REV AAUGUST 8, 2006
ICS844004
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQ1, Q1
VDDO
Type
Output
Description
Differential output pair. LVDS interface levels.
Output supply pins.
3, 22
4, 5
Power
Ouput
Q0, nQ0
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
6
MR
Input
Pulldown
Selects between the PLL and TEST_CLK as input to the dividers. When
7
nPLL_SEL
Input
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
8, 18
9
nc
Unused
Power
No connect.
VDDA
Analog supply pin.
F_SEL0,
F_SEL1
10, 12
11
Input
Power
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
VDD
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
13, 14
15, 19
16
GND
Power
Input
Power supply ground.
TEST_CLK
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
17
nXTAL_SEL
Input
20, 21
23, 24
nQ3, Q3
Q2, nQ2
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
RPULLDOWN Input Pulldown Resistor
51
kΩ
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844004AG REV AAUGUST 8, 2006
ICS844004
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA 70°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.465
VDD
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.3
3.465
V
TBD
TBD
TBD
mA
mA
mA
IDDA
IDDO
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.375
2.375
2.375
2.5
2.5
2.625
VDD
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
2.5
2.625
V
TBD
TBD
TBD
mA
mA
mA
IDDA
IDDO
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
VDD = 2.5V
1.7
-0.3
-0.3
V
DD = 3.3V
VDD = 2.5V
0.7
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
Input
High Current
IIH
VDD = VIN = 3.465 or 2.625V
150
µA
µA
TEST_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL
VDD = 3.465V or 2.625V,
VIN = 0V
Input
Low Current
IIL
-150
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
350
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
1.45
50
∆ VOS
VOS Magnitude Change
mV
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
350
40
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.2
∆ VOS
VOS Magnitude Change
50
mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
26.5625
Mode of Oscillation
Frequency
23.33
28.33
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum Typical Maximum Units
186.67
140
226.66
170
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
93.33
46.67
113.33
56.66
tsk(o)
Output Skew; NOTE 1, 2
TBD
0.65
0.61
0.74
0.64
0.80
400
50
212.5MHz, (637kHz - 10MHz)
159.375MHz, (637kHz - 10MHz)
156.25MHz, (637kHz - 10MHz))
106.25MHz, (637kHz -10MHz)
53.125MHz, (637kHz - 10MHz)
20ꢀ to 80ꢀ
ps
ps
RMS Phase Jitter (Random);
NOTE 3
tjit(Ø)
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
F_SEL[1:0] = 11
Minimum Typical Maximum Units
186.67
140
226.66
170
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency
93.33
46.67
113.33
56.66
tsk(o)
Output Skew; NOTE 1, 2
TBD
0.65
0.61
0.74
0.64
0.80
430
50
212.5MHz, (637kHz - 10MHz)
159.375MHz, (637kHz - 10MHz)
156.25MHz, (637kHz - 10MHz))
106.25MHz, (637kHz -10MHz)
53.125MHz, (637kHz - 10MHz)
20ꢀ to 80ꢀ
ps
ps
RMS Phase Jitter (Random);
NOTE 3
tjit(Ø)
ps
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844004
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
SCOPE
SCOPE
Qx
Qx
2.5V 5ꢀ
POWER SUPPLY
3.3V 5ꢀ
POWER SUPPLY
+
Float GND –
+
Float GND –
LVDS
LVDS
nQx
nQx
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
Qx
TEST_CLK
nQ0:nQ3
nQy
Q0:Q3
Qy
tPD
tsk(o)
OUTPUT SKEW
PROPAGATION DELAY
Phase Noise Plot
nQ0:nQ3
Q0:Q3
tPW
tPERIOD
Phase Noise Mask
tPW
odc =
x 100ꢀ
tPERIOD
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844004AG REV AAUGUST 8, 2006
ICS844004
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
VDD
out
out
80ꢀ
tF
80ꢀ
tR
➤
DC Input
LVDS
VSWING
20ꢀ
Clock
Outputs
20ꢀ
VOS/∆ VOS
➤
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VDD
➤
out
out
LVDS
DC Input
100
V
OD/∆ VOD
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844004
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS844004 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin.To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
3.3V or 2.5V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844004 has been characterized with 18pF parallel
resonant crystals.The capacitor values shown in Figure 2 below
were determined using a 26.5625MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error.
XTAL_OUT
XTAL_IN
C1
33p
X1
18pF Parallel Crystal
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844004
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
2.5V or 3.3V
VDD
LVDS_Driv er
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844004AG REV AAUGUST 8, 2006
ICS844004
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 6. θ VS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS844004 is: 2914
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844004AG REV AAUGUST 8, 2006
ICS844004
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844004AG REV AAUGUST 8, 2006
ICS844004
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS844004AG
Marking
ICS844004AG
ICS844004AG
TBD
Package
Shipping Packaging
tube
Temperature
24 Lead TSSOP
24 Lead TSSOP
24 Lead TSSOP
24 Lead TSSOP
0°C to 70°C
0°C to 70C
0°C to 70°C
0°C to 70C
ICS844004AGT
ICS844004AGLF
ICS844004AGLFT
2500 tape & reel
tube
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844004AG REV AAUGUST 8, 2006
ICS844004
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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