8440259AK-45 [IDT]
Clock Generator, 156.25MHz, 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32;
| 型号： | 8440259AK-45 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 156.25MHz, 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32 |
| 文件： | 总19页 (文件大小：592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-
LVDS/LVCMOS FREQUENCY SYNTHESIZER
ICS8440259-45
GENERAL DESCRIPTION
ICS
FEATURES
• One differential LVDS output at 156.25MHz or 125MHz
The ICS8440259-45 is a 9 output synthesizer
optimized to generate Gigabit and 10 Gigabit
Ethernet clocks and is member of the
Four differential LVDS outputs at 125MHz
Three LVCMOS/LVTTL single-ended outputs at 125MHz
One LVCMOS/LVTTL single-ended output at 3.90625MHz
HiPerClockS™
a
HiPerClockS™family of high performance clock
solutions from IDT. Using a 25MHz, 18pF parallel
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input and PLL bypass from a single select pin
resonant crystal, the device will generate both 156.25MHz,
125MHz and 3.90625MHz clocks with mixed LVDS and
LVCMOS/LVTTL output levels. The ICS8440259-45 uses IDT’s
3rd generation low phase noise VCO technology and can
achieve <1ps typical rms phase jitter, easily meeting Ethernet
jitter requirements. The ICS8440259-45 is packaged in a small,
5mm x 5mm VFQFN package that is optimum for applications
with space limitations.
• VCO range: 490MHz - 680MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical), LVDS output
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical), LVDS output
• LVDS supply voltage modes: full 3.3V and full 2.5V
• LVCMOS supply voltage modes:
Core/Output Core/Output
3.3V/3.3V 3.3V/2.5V
Core/Output
2.5V/2.5V
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS6)
packages
BLOCK DIAGRAM
Pullup
nPLL_BYPASS
Pulldown
F_SEL
Q0
0
1
Pulldown
REF_CLK
0
nQ0
÷5
÷4
25MHz
VCO
490-680MHz
Phase
Detector
XTAL_IN
1
OSC
Q1
0
1
XTAL_OUT
nQ1
÷5
PIN ASSIGNMENT
Q2
÷25
nQ2
Q3
nQ3
Q4
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
Q0
nQ0
Q8
1
2
3
4
5
6
7
8
VDDO_LVCMOS
nQ4
Q5
ICS8440259-45
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
Q7
GND
Q1
GND
nQ1
Q6
VDDO_LVDS
VDDO_LVCMOS
K Package
Top View
Q6
Q7
Q2
Q5
nQ2
GND
9
10 11 12 13 14 15 16
Q8
÷32
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
1
ICS8440259AK-45 REV. B JULY 30, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2
Q0, nQ0
Output
Differential clock outputs. LVDS interface levels.
3, 9, 15,
17, 21, 32
GND
Power
Power supply ground.
4, 5
6, 12
7, 8
Q1, nQ1
VDDO_LVDS
Q2, nQ2
Q3, nQ3
Q4, nQ4
VDD
Output
Power
Output
Output
Output
Power
Differential clock outputs. LVDS interface levels.
Output supply pins for Qx/nQx LVDS outputs.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Core supply pins.
10, 11
13, 14
16, 27
18, 20,
22, 24
Q5, Q6,
Q7, Q8
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
19, 23
25
VDDO_LVCMOS
VDDA
Power
Power
Output supply pins for Q5:Q8 LVCMOS outputs.
Analog supply pin.
Input select and PLL bypass control pin. See Table 3B.
LVCMOS/LVTTL interface levels.
26
nPLL_BYPASS
Input
Pullup
28
29
F_SEL
Input
Input
Pulldown Frequency select pin. See Table 3A. LVCMOS/LVTTL interface levels.
Pulldown Single-ended LVCMOS/LVTTL reference clock input.
REF_CLK
30,
31
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
pF
kΩ
Ω
VDD,VDDO_LVCMOS = 3.465V
15
15
15
51
25
Power Dissipation
Capacitance
CPD
VDD, VDDO_LVCMOS = 2.625V
V
DD = 3.465, VDDO_LVCMOS = 2.625V
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance Q5:Q8
TABLE 3A. FREQUENCY SELECT FUNCTION TABLE
Outputs
Input
Output Divider Q0/nQ0 Frequency
F_SEL
0
1
÷5
÷4
125MHz (default)
156.25MHz
TABLE 3B. PLL BYPASS AND INPUT SELECT FUNCTION TABLE
Inputs
nPLL_BYPASS
PLL Bypass
PLL Bypassed
PLL Enabled
Input Selected
REF_CLK
0
1
XTAL_IN/XTAL_OUT (default)
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
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ICS8440259AK-45 REV. B JULY 30, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the DC Characteristics or AC Characteristics is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
-0.5V to VDDO_LVCMOS + 0.5V
Outputs, IO (LVCMOS)
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Operating Temperature Range, TA
Storage Temperature, TSTG
-40°C to +85°C
-65°C to 150°C
Package Thermal Impedance, θJA
37°C/W (0 mps)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_LVCMOS = VDDO_LVDS = 3.3V 5ꢀ,TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
Core Supply Voltage
3.135
3.3
3.465
VDD
V
V
VDDA
Analog Supply Voltage
VDD – 0.17
3.3
VDDO_LVCMOS,
VDDO_LVDS
Output Supply Voltage
3.135
2.5
3.465
V
IDD
Power Supply Current
116
17
mA
mA
mA
IDDA
Analog Supply Current
IDDO_LVCMOS
LVCMOS Output Supply Current
50
IDDO_LVDS
LVDS Output Supply Current
145
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_LVDS = 3.3V 5ꢀ, VDDO_LVCMOS = 2.5V 5ꢀ,TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
Core Supply Voltage
3.135
3.3
3.465
VDD
V
V
VDDA
Analog Supply Voltage
VDD – 0.17
3.3
VDDO_LVCMOS,
VDDO_LVDS
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
116
17
mA
mA
mA
IDDA
Analog Supply Current
IDDO_LVCMOS
LVCMOS Output Supply Current
35
IDDO_LVDS
LVDS Output Supply Current
145
mA
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
3
ICS8440259AK-45 REV. B JULY 30, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_LVCMOS = VDDO_LVDS = 2.5V 5ꢀ%TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
Core Supply Voltage
2.375
2.5
2.625
VDD
V
V
VDDA
Analog Supply Voltage
VDD – 0.16
3.3
VDDO_LVCMOS%
VDDO_LVDS
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
105
16
mA
mA
mA
IDDA
Analog Supply Current
IDDO_LVCMOS
LVCMOS Output Supply Current
35
IDDO_LVDS
LVDS Output Supply Current
145
mA
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD = 3.3V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
VIH
Input High Voltage
VDD = 2.5V
VDD = 3.3V
1.7
-0.3
-0.3
VIL
IIH
Input Low Voltage
VDD = 2.5V
0.7
150
5
V
REF_CLK (PD)
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V%
VIN = 0V
µA
µA
Input
High Current
nPLL_BYPASS (PU)
REF_CLK (PD)
-5
µA
µA
Input
IIL
Low Current
VDD = 3.465V or 2.625V%
VIN = 0V
nPLL_BYPASS (PU)
-150
Output
High Voltage;
NOTE 1
Q5:Q8
Q5:Q8
2.1
V
V
VDDO_LVCMOS = 3.3V 5ꢀ
VDDO_LVCMOS = 2.5V 5ꢀ
VOH
1.75
Output
VOL
Low Voltage; Q5:Q8
NOTE 1
0.7
V
VDDO_LVCMOS = 3.3V or 2.5V 5ꢀ
NOTE 1: Outputs terminated with 50Ω to VDDO_LVCMOS/2. See Parameter Measurement Information%
Output Load Test Circuit diagram.
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = VDDO_LVDS = 3.3V 5ꢀ%TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
300
400
545
50
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.25
1.35
1.5
50
Δ VOS
VOS Magnitude Change
mV
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
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ICS8440259AK-45 REV. B JULY 30, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 4F. LVDS DC CHARACTERISTICS, VDD = VDDO_LVDS = 2.5V 5ꢀ%TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
300
400
545
50
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.25
1.35
1.5
50
Δ VOS
VOS Magnitude Change
mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
25
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6A. AC CHARACTERISTICS, VDD = VDDO_LVCMOS = VDDO_LVDS = 3.3V 5ꢀ%TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Q0/nQ0:Q4/nQ4
Q5:Q7
125
125
MHz
MHz
MHz
MHz
ps
Output
fOUT
Frequency
Q8
3.90625
156.25
0.41
Q0/nQ0
Q0:4/nQ0:4
125MHz% (1.875MHz - 20MHz)
RMS Phase Jitter
(Random);
156.25MHz%
(1.875MHz - 20MHz)
tjit(Ø)
Q0/nQ0
0.41
0.45
ps
ps
ns
NOTE 1
Q5:Q7
125MHz% (1.875MHz - 20MHz)
Q0/nQ0:Q4/nQ4
(NOTE 2)
125MHz% 20ꢀ to 80ꢀ
0.5
1.2
Q0/nQ0:Q4/nQ4
Q0/nQ0
125MHz% 20ꢀ to 80ꢀ
156.25MHz% 20ꢀ to 80ꢀ
125MHz% 20ꢀ to 80ꢀ
3.90625MHz% 20ꢀ to 80ꢀ
125MHz
0.4
0.325
0.35
1
0.65
0.65
1.2
1.65
55
ns
ns
ns
ns
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Output
Rise/Fall Time
tR / tF
Q5:Q7
Q8 (NOTE 2)
Q0/nQ0:Q4/nQ4
Q0/nQ0
45
156.25MHz
47
53
Output
Duty Cycle
odc
odc
Q5:Q7
125MHz
42
58
Q8
3.90625MHz
49
51
Q0/nQ0:Q4/nQ4
Q0/nQ0
125MHz
47
53
Output
Duty Cycle%
BYPASS Mode
156.25MHz
47
53
Q5:Q7
125MHz
43
57
Q8
3.90625MHz
49
51
NOTE 1: Please refer to the Phase Noise Plots.
NOTE 2: Output loaded with 15pF.
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
5
ICS8440259AK-45 REV. B JULY 30, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
TABLE 6B. AC CHARACTERISTICS, VDD = VDDO_LVCMOS = VDDO_LVDS = 2.5V 5ꢀ,TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Q0/nQ0:Q4/nQ4
Q5:Q7
125
125
MHz
MHz
MHz
MHz
ps
Output
fOUT
Frequency
Q8
3.90625
156.25
0.41
Q0/nQ0
Q0:4/nQ0:4
125MHz, (1.875MHz - 20MHz)
RMS Phase Jitter
(Random);
156.25MHz,
(1.875MHz - 20MHz)
tjit(Ø)
Q0/nQ0
0.43
0.44
ps
NOTE 1
Q5:Q7
125MHz, (1.875MHz - 20MHz)
125MHz, 20ꢀ to 80ꢀ
156.25MHz, 20ꢀ to 80ꢀ
125MHz, 20ꢀ to 80ꢀ
3.90625MHz, 20ꢀ to 80ꢀ
125MHz
ps
ns
ns
ns
ns
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Q0/nQ0:Q4/nQ4
Q0/nQ0
0.3
0.3
0.6
1.5
45
47
43
49
47
43
44
49
0.85
0.85
1.65
2.65
55
Output
Rise/Fall Time
tR / tF
Q5:Q7
Q8 (NOTE 2)
Q0/nQ0:Q4/nQ4
Q0/nQ0
156.25MHz
53
Output
Duty Cycle
odc
odc
Q5:Q7
125MHz
57
Q8
3.90625MHz
51
Q0/nQ0:Q4/nQ4
Q0/nQ0
125MHz
53
Output
Duty Cycle,
BYPASS Mode
156.25MHz
57
Q5:Q7
125MHz
56
Q8
3.90625MHz
51
NOTE 1: Please refer to the Phase Noise Plots.
NOTE 2: Output loaded with 15pF.
TABLE 6C. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO_LVCMOS = 2.5V 5ꢀ,TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Q5:Q7
Q8
125
MHz
MHz
Output
fOUT
Frequency
3.90625
RMS Phase Jitter
(Random)
tjit(Ø)
Q5:Q7
125MHz
0.496
ps
Q5:Q7
125MHz, 20ꢀ to 80ꢀ
3.90625MHz, 20ꢀ to 80ꢀ
125MHz
0.2
1.5
42
1.65
2.65
58
ns
ns
ꢀ
ꢀ
Output
Rise/Fall Time
tR / tF
Q8 (NOTE 1)
Q5:Q7
Output
Duty Cycle
odc
odc
Q8
3.90625MHz
49
51
Output
Duty Cycle,
BYPASS Mode
Q5:Q7
Q8
125MHz
43
49
57
51
ꢀ
ꢀ
3.90625MHz
NOTE 1: Output loaded with 15pF.
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
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ICS8440259AK-45 REV. B JULY 30, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
TYPICAL PHASE NOISE AT 125MHZ (LVCMOS @ 2.5V)
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.44ps (typical)
Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 156.25MHZ (LVDS @ 2.5V)
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.43ps (typical)
Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
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ICS8440259AK-45 REV. B JULY 30, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
TYPICAL PHASE NOISE AT 125MHZ (LVDS @ 3.3V)
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.41ps (typical)
Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 156.25MHZ (LVDS @ 3.3V)
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.41ps (typical)
Ethernet Filter
Raw Phase Noise Data
Phase Noise Result by adding
Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
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ICS8440259AK-45 REV. B JULY 30, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
SCOPE
SCOPE
VDD,
VDDO_LVDS
Qx
VDD,
VDDO_LVDS
Qx
2.5V 5ꢀ
POWER SUPPLY
3.3V 5ꢀ
POWER SUPPLY
VDDA
VDDA
+
Float GND –
LVDS
+
Float GND –
LVDS
nQx
nQx
3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT
2.5V LVDS OUTPUT LOAD AC TEST CIRCUIT
2.05V 5ꢀ
1.25V 5ꢀ
1.65V 5ꢀ
1.65V 5ꢀ
2.05V 5ꢀ
,
SCOPE
VDD
VDD
SCOPE
V
DDO_LVCMOS
VDDA
V
DDO_LVCMOS
Qx
Qx
VDDA
LVCMOS
GND
LVCMOS
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
1.25V 5ꢀ
Phase Noise Plot
,
SCOPE
VDD
V
DDO_LVCMOS
VDDA
Phase Noise Mask
Qx
LVCMOS
GND
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.25V 5ꢀ
2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
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ICS8440259AK-45 REV. B JULY 30, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
nQ0:nQ4
VDDO
2
Q0:Q4
Q5:Q8
tPW
tPW
tPERIOD
tPERIOD
tPW
odc =
x 100ꢀ
tPW
x 100ꢀ
odc =
tPERIOD
tPERIOD
LVDS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80ꢀ
tF
80ꢀ
tR
80ꢀ
tF
80ꢀ
tR
VOD
20ꢀ
20ꢀ
Clock
Outputs
20ꢀ
20ꢀ
Clock
Outputs
LVDS OUTPUT RISE/FALL TIME
LVCMOS OUTPUT RISE/FALL TIME
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
➤
out
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
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ICS8440259AK-45 REV. B JULY 30, 2007
ICS8440259-45
FEMTOCLOCK™ CRYSTAL/LVCMOS-TO-LVDS/ LVCMOS FREQUENCY SYNTHESIZER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8440259-45 provides
3.3V or 2.5V
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VDD, VDDA, VDDO_LVDS and
VDDO_LVCMOS should be individually connected to the power sup-
ply plane through vias, and bypass capacitors should be used
for each pin. To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how a 10Ω re-
sistor along with a 10µF and a .01μF bypass capacitor should
VDD
.01μF
10Ω
VDDA
.01μF
10μF
be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS8440259-45 has been characterized with 18pF parallel
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
resonant crystals. The capacitor values shown in Figure 2 below
C2
33p
XTAL_OUT
XTAL_IN
X1
18pF Parallel Crystal
C1
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
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PRELIMINARY
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can be left
floating. The input edge rate can be as slow as 10ns. For
LVCMOS inputs, it is recommended that the amplitude be
reduced from full swing to half swing in order to prevent signal
interference with the power rail and to reduce noise. This
configuration requires that the output impedance of the driver
(Ro) plus the series resistance (Rs) equals the transmission
line impedance. In addition, matched termination at the crystal
input will attenuate the signal in half. This can be done in one
of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by
removing R1 and making R2 50Ω.
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
INPUTS:
LVCMOS OUTPUTS
CRYSTAL INPUTS
All unused LVCMOS output can be left floating. There should be
no trace attached.
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kW resistor can be tied
from XTAL_IN to ground.
LVDS OUTPUTS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
REF_CLK INPUT
For applications not requiring the use of the reference clock, it
can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-downs; additional resistance is
not required but can be added for additional protection. A 1kΩ
resistor can be used.
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PRELIMINARY
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
2.5V or 3.3V
VDD
LVDS_Driver
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
EPADTHERMAL RELEASE PATH
The EPAD provides heat transfer from the device to the P.C.board.
The exposed metal pad on the PCB is connected to the ground
plane through thermal vias. To guarantee the device’s electrical
and thermal performance, EPAD must be soldered to the exposed
metal pad on the PCB, as shown in Figure 5. For further infor-
mation, please refer to the Application Note on Surface Mount
Assembly of Amkor’s Thermally /Electrically Enhance Leadframe
Base Package, Amkor Technology.
SOLDER
SOLDER
PIN
PIN
EPAD
PIN PAD
GROUND PLANE
EXPOSED METAL PAD
(GROUND PAD)
PIN PAD
THERMAL VIA
FIGURE 5. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
IDT™ / ICS™ LVDS/LVCMOS FREQUENCY SYNTHESIZER
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PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8440259-45.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS840259-45 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
DD
Core and LVDS Output Power Dissipation
•
Power (core, LVDS) = V
* (I + I
+ I ) = 3.465V * (116mA + 145mA + 17mA) = 963.27mW
DDO_LVDS DDA
DD_MAX
DD
LVCMOS Output Power Dissipation
•
Output Impedance R Power Dissipation due to Loading 50Ω to V /2
OUT
DDO
Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 25Ω)] = 23.1mA
•
•
•
Power Dissipation on the ROUT per LVCMOS output
2
Power (ROUT) = ROUT * (IOUT
)
= 25Ω * (23.1mA)2 = 13.3mW per output
Total Power Dissipation on the ROUT
Total Power (ROUT) = 13.3mW * 4 = 53.2mW
Dynamic Power Dissipation at 125MHz
2
Power (125MHz) = CPD * Frequency * (VDDO
)
= 15pF * 125MHz * (3.465V)2 = 22.5mW per output
Total Power (125MHz) = 22.5mW * 3 = 67.5mW
•
Dynamic Power Dissipation at 25MHz
2
Power (25MHz) = CPD * frequency * (VDDO
)
= 15pF * 3.90625MHz * (3.465V)2 = 0.7 mW per output
Total Power Dissipation
Total Power
•
= Power (core, LVDS) + Total Power (ROUT) + Total Power (125MHz) + Total Power (25MHz)
= 1136.5mW + 53.2mW + 67.5mW + 0.7mW
= 1258mW
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PRELIMINARY
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the
TM
reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming no air flow and a multi-layer board, the appropriate value is 37°C/W per Table 7.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 1.258W * 37°C/W = 116.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 32-LEAD VFQFN, FORCED CONVECTION
JA
θ vs. Air Flow (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
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PRELIMINARY
RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 32 LEAD VFQFN
JA
θ vs. Air Flow (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
TRANSISTOR COUNT
The transistor count for ICS8440259-45 is: 2975
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PRELIMINARY
PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page.
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
0.80
0
1.00
0.05
A1
A3
b
--
0.25 Ref.
0.25
0.18
0.30
8
ND
NE
D
8
5.00 BASIC
2.25
D2
E
1.25
1.25
0.30
3.25
3.25
0.50
5.00 BASIC
2.25
E2
e
0.50 BASIC
0.40
L
Reference Document: JEDEC Publication 95, MO-220
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TABLE 10. ORDERING INFORMATION
Part/Order Number
8440259AK-45
Marking
Package
Shipping Packaging
Tray
Temperature
ICS40259A45
ICS40259A45
ICS0259A45L
ICS0259A45L
32 Lead VFQFN
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
8440259AK-45T
8440259AK-45LF
8440259AK-45LFT
32 Lead VFQFN
1000 Tape & Reel
Tray
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
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PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
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For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
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Europe
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+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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