844251BG-14 [IDT]
FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR; FEMTOCLOCK ™ CRYSTAL - TO- LVDS时钟发生器
| 型号： | 844251BG-14 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FEMTOCLOCK™ CRYSTAL-TO-LVDS CLOCK GENERATOR |
| 文件： | 总16页 (文件大小：801K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEMTOCLOCK™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
ICS844251-14
General Description
Features
The ICS844251-14 is an Ethernet Clock Generator
• One differential LVDS output pair
and a member of the HiPerClocksTM family of high
performance devices from IDT. The ICS844251-14
uses an 18pF parallel resonant crystal over the
range of 23.2MHz – 30MHz. For Ethernet
S
IC
• Crystal oscillator interface designed for 18pF, parallel resonant
HiPerClockS™
crystal (23.2MHz – 30MHz)
• Output frequency ranges: 145MHz – 187.5MHz and
580MHz – 750MHz
applications, a 25MHz crystal is used. The device has excellent
<1ps phase jitter performance, over the 1.875MHz – 20MHz
integration range. The ICS844251-14 is packaged in a small 8-pin
TSSOP, making it ideal for use in systems with limited board
space.
• VCO range: 580MHz – 750MHz
• RMS phase jitter at 156.25MHz, using a 25MHz crystal
(1.875MHz – 20MHz): 0.53ps (typical)
• Full 3.3V or 2.5V output supply modes
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Common Configuration Table
Inputs
Output Frequency Range
Crystal Frequency (MHz)
FREQ_SEL
M
25
25
25
N
1
1
4
Multiplication Value M/N
(MHz)
25
1
1
0
25
25
625
26.67
666.67
156.25
25 (default)
6.25
Pin Assignment
Block Diagram
Pulldown
FREQ_SEL
1
2
3
4
8
7
6
5
VDDA
GND
VDD
Q
nQ
XTAL_OUT
XTAL_IN
FREQ_SEL
0 (default)
1
N
÷4
÷1
XTAL_IN
OSC
XTAL_OUT
FREQ_SEL
Q
nQ
VCO
Phase
Detector
580MHz - 750MHz
ICS844251-14
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
M = ÷25 (fixed)
G Package
Top View
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FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Table 1. Pin Descriptions
Number
Name
VDDA
GND
Type
Description
1
2
Output
Power
Analog supply pin.
Power supply ground.
3,
4
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
5
6, 7
8
FREQ_SEL
nQ, Q
Input
Output
Power
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Core supply pin.
VDD
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
4
RPULLdown Input Pulldown Resistor
51
kΩ
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
129.5°C/W (0 mps)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
VDD
Units
V
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
VDDA
IDD
VDD – 0.10
3.3
V
100
mA
mA
IDDA
10
Table 3B. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
VDD
Units
V
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
VDDA
IDD
VDD – 0.10
2.5
V
95
mA
mA
IDDA
10
Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
VDD = 3.465V
VDD = 2.625V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
V
2
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
V
DD = 3.465V
DD = 2.625V
V
Input Low Voltage
V
0.7
V
IIH
IIL
Input High Current
Input Low Current
VDD = VIN = 3.465V or 2.625V
150
µA
µA
VDD = 3.465V or 2.625V, VIN = 0V
-5
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Table 3D. LVDS DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
454
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
∆VOD
VOS
50
1.275
1.525
50
∆VOS
VOS Magnitude Change
mV
Table 3E. LVDS DC Characteristics, VDD = VDDA = 2.5V 5%, TA = 0°C to 70°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
454
50
∆VOD
VOS
1.0
1.4
50
∆VOS
VOS Magnitude Change
mV
Table 4. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
23.2
30
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
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AC Electrical Characteristics
Table 5A. AC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Parameter Symbol
Test Conditions
FREQ_SEL = 0
FREQ_SEL = 1
Minimum Typical Maximum Units
145
580
187.5
750
MHz
MHz
fOUT
Output Frequency
156.25MHz,
Integration Range: 1.875MHz – 20MHz
0.53
0.45
ps
ps
RMS Phase Jitter, Random;
NOTE 1
tjit(Ø)
625MHz,
Integration Range: 1.875MHz – 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
FREQ_SEL = 0
FREQ_SEL = 1
70
48
46
550
52
ps
%
%
54
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Please refer to Phase Noise Plots.
Table 5B. AC Characteristics, VDD = 2.5V 5%, TA = 0°C to 70°C
Parameter Symbol
Test Conditions
FREQ_SEL = 0
FREQ_SEL = 1
Minimum Typical Maximum Units
145
580
187.5
750
MHz
MHz
fOUT
Output Frequency
156.25MHz,
Integration Range: 1.875MHz – 20MHz
0.54
0.45
ps
ps
RMS Phase Jitter, Random;
NOTE 1
tjit(Ø)
625MHz,
Integration Range: 1.875MHz – 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
FREQ_SEL = 0
FREQ_SEL = 1
70
48
46
550
52
ps
%
%
54
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Please refer to Phase Noise Plots.
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Typical Phase Noise at 156.25MHz (3.3V)
Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.53ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
Ethernet filter to raw data
Offset Frequency (Hz)
Typical Phase Noise at 625MHz (3.3V)
Ethernet Filter
625MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.45ps
Raw Phase Noise Data
Phase Noise Result by adding a
Ethernet filter to raw data
Offset Frequency (Hz)
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Parameter Measurement Information
SCOPE
SCOPE
Qx
Qx
VDD
VDD
3.3V 5%
POWER SUPPLY
2.5V 5%
POWER SUPPLY
VDDA
VDDA
+
Float GND –
+
Float GND
–
LVDS
LVDS
nQx
nQx
3.3V LVDS Output Load AC Test Circuit
2.5V LVDS Output Load AC Test Circuit
nQ
nQ
Q
80%
80%
tR
tPW
tPERIOD
VOD
20%
20%
Q
tPW
tF
odc =
x 100%
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
Phase Noise Plot
VDD
out
➤
DC Input
Phase Noise Mask
LVDS
out
VOS/∆ VOS
Offset Frequency
➤
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OFFSET VOLTAGE SETUP
RMS Phase Jitter
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Parameter Measurement Information, continued
VDD
➤
out
LVDS
DC Input
100
V
OD/∆ VOD
➤
out
-
DIFFERENTIAL OUTPUT VOLTAGE SETUP
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS844251-14
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD and VDDA should
be individually connected to the power supply plane through vias,
and 0.01µF bypass capacitors should be used for each pin. Figure
1 illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VDDA pin.
3.3V or 2.5V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
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Crystal Input Interface
The ICS844251-14 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
VDD
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
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FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
3.3V, 2.5V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
matched load termination of 100Ω across near the receiver input.
differential transmission line environment, LVDS drivers require a
3.3V or 2.5V
VDD
50Ω
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
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Schematic Example
Figure 5 shows an example of ICS844251-14 application
schematic. In this example, the device is operated at VDD = 3.3V.
The decoupling capacitor should be located as close as possible
to the power pin. The 18pF parallel resonant 25MHz crystal is
used. The C1 = 27pF and C2 = 27pF are recommended for
frequency accuracy. For different board layouts, the C1 and C2
may be slightly adjusted for optimizing frequency accuracy. For the
LVDS output drivers, place a 100Ω resistor as close to the receiver
as possible.
VDD
C5
0.01u
VDD
R1
VDDA
10
C3
U1
Zo = 50 Ohm
Q
0.1u
C4
10u
1
8
VDDA
VDD
2
3
4
7
6
5
GND
Q
nQ
+
-
R2
XTAL_OUT
XTAL_IN
FREQ_SEL
100
FREQ_SEL
25 MHz
18pF
Zo = 50 Ohm
nQ
C1
27pF
X1
C2
27pF
Zo = 50 Ohm
Q
Logic Input Pin Examples
Set Logic
R3
50
Set Logic
Input to
'0'
VDD
VDD
+
-
Input to
'1'
RU1
1K
RU2
Not Install
C7
0.1uF
R4
50
Zo = 50 Ohm
To Logic
Input
To Logic
nQ
Input
pins
pins
RD1
RD2
1K
Not Install
Alternate
LVDS
Termination
Figure 5. ICS844251-14 Schematic Example
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844251-14.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844251-14 is the sum of the core power plus the analog power plus the power dissipated in the
load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (100mA + 10mA) = 381.15mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 129.5.°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.381W *129.5°C/W = 119.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 8 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
125.5°C/W
123.5°C/W
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Reliability Information
Table 7. θJA vs. Air Flow Table for a 8 Lead TSSOP
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
125.5°C/W
123.5°C/W
Transistor Count
The transistor count for ICS844251-14 is: 2401
Package Outline and Package Dimensions
Table 8. Package Dimensions
Package Outline - G Suffix for 8 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
8
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.5
0.80
0.19
0.09
2.90
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number
844251BG-14
844251BG-14T
844251BG-14LF
844251BG-14LFT
Marking
51B14
51B14
1B14L
1B14L
Package
8 Lead TSSOP
8 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
“Lead-Free” 8 Lead TSSOP
“Lead-Free” 8 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev
Table
Page
Description of Change
Date
A
11
Added schematic layout.
5/1/09
IDT™ / ICS™ LVDS CLOCK GENERATOR
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Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contact IDT
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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