844441AMI-300LF [IDT]
Clock Generator, 300MHz, PDSO8, 3.90 X 4.90 MM, 1.375 MM HEIGHT, ROHS COMPLIANT, MS-012, SOIC-8;
| 型号： | 844441AMI-300LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 300MHz, PDSO8, 3.90 X 4.90 MM, 1.375 MM HEIGHT, ROHS COMPLIANT, MS-012, SOIC-8 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总13页 (文件大小：867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
TM
FEMTOCLOCKS
ICS844441I
SAS/SATA CLOCK GENERATOR
General Description
Features
The ICS844441I is a low jitter, high performance
• Designed for use in SAS, SAS-2, and SATA systems
• Center ( 0.25%) Spread Spectrum Clocking (SSC)
• Down (-0.23% or -0.5%) SSC
S
IC
clock generator and a member of the FemtoClocks™
family of silicon timing products. The ICS844441I is
designed for use in applications using the SAS and
SATA interconnect. The ICS844441I uses an
HiPerClockS™
• Better frequency stability than SAW oscillators
• One differential 2.5V LVDS output
external, 25MHz, parallel resonant crystal to generate four
selectable output frequencies: 75MHz, 100MHz, 150MHz, and
300MHz. This silicon based approach provides excellent
frequency stability and reliability. The ICS844441I features down
and center spread spectrum (SSC) clocking techniques.
• Crystal oscillator interface designed for 25MHz
(CL = 18pF) frequency
• External fundamental crystal frequency ensures high reliability
and low aging
• Selectable output frequencies: 75MHz, 100MHz, 150MHz,
Applications
300MHz
• SAS/SATA Host Bus Adapters
• Output frequency is tunable with external capacitors
• RMS phase jitter: 1.33ps (typical)
• SATA Port Multipliers
• SAS I/O Controllers
• 2.5V operating supply
• TapeDrive and HDD Array Controllers
• SAS Edge and Fanout Expanders
• HDDs and TapeDrives
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
• Disk Storage Enterprise
Pin Assignment
1
2
3
4
8
7
6
5
XTAL_OUT
XTAL_IN
SSC_SEL0
SSC_SEL1
GND
nQ
Q
VDD
Block Diagrams
ICS844441I
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.375mm package body
M Package
XTAL_IN
25MHz
XTAL
00 = SSC Off
FemtoClock™
OSC
01 = 0.5% Down-spread
10 = 0.23% Down-spread
11 = 0.5% Center-spread
Q
PLL
nQ
XTAL_OUT
Top View
SSC Output
Control Logic
Pulldown:Pulldown
SSC_SEL(1:0)
nPLL_SEL
8-Lead SOIC
GND
16
15
14
13
12
11
10
9
F_SEL1
GND
nPLL_SEL
nQ
Q
VDD
1
2
3
4
5
6
7
8
XTAL_OUT
XTAL_IN
Pulldown
SSC_SEL0
nc
nc
nc
XTAL_IN
FemtoClock™
PLL
25MHz
XTAL
OSC
F_SEL0
VDD
0
1
00 = 75MHz
SSC_SEL1
01 = 100MHz
Q
XTAL_OUT
10 = 150MHz (default)
11 = 300MHz
nQ
ICS844441I
Pullup:Pulldown
F_SEL(1:0)
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Clock Output
Control Logic
Pulldown:Pulldown
SSC_SEL(1:0)
16-Lead TSSOP
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ SAS/SATA CLOCK GENERATOR
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ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Table 1. Pin Descriptions
Name
Type
Description
XTAL_OUT,
XTAL_IN
Input
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
SSC_SEL0,
SSC_SEL1
Pulldown SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
F_SEL0
F_SEL1
nPLL_SEL
Q, nQ
GND
Input
Input
Pulldown Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
Pullup Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
Input
Pulldown PLL Bypass pin. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
Power supply ground.
Output
Power
Power
Unused
VDD
Power supply pin.
nc
No connect.
NOTE: Pullup/Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
4
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pullup Resistor
51
51
kΩ
kΩ
Function Tables
Table 3A. SSC_SEL[1:0] Function Table
Inputs
Table 3B. F_SEL[1:0] Function Table
Inputs
Output Frequency
(MHz)
SSC_SEL1
SSC_SEL0
Mode
F_SEL1
F_SEL0
0 (default)
0 (default)
SSC Off
0
0
75
0
1
1
1
0
1
0.5% Down-spread
0.23% Down-spread
0.5% Center-spread
0
1 (default)
1
1
0 (default)
1
100
150
300
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FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
16 Lead TSSOP
8 Lead SOIC
92.4°C/W (0 mps)
96.0°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
2.5
Maximum
Units
V
Power Supply Voltage
Power Supply Current
2.375
2.625
IDD
45
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
1.7
Typical
Maximum
Units
V
VIH
VIL
Input High Voltage
Input Low Voltage
VDD + 0.3
-0.3
0.7
5
V
F_SEL1
VDD = VIN = 2.5V
µA
Input
High Current
IIH
SSC_SEL[0:1],
F_SEL0, nPLL_SEL
VDD = VIN = 2.5V
VDD = 2.5V, VIN = 0V
VDD = 2.5V, VIN = 0V
150
µA
µA
µA
F_SEL1
-150
-5
Input
Low Current
IIL
SSC_SEL[0:1],
F_SEL0, nPLL_SEL
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FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Table 4C. LVDS DC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
350
∆VOD
VOS
50
50
1.25
∆VOS
VOS Magnitude Change
mV
Table 4D. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
MHz
Ohm
pF
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 2.5V 5%, TA = -40°C to 85°C
Parameter
Symbol
Test Conditions
F_SEL(1:0) = 00
F_SEL(1:0) = 01
F_SEL(1:0) = 10
F_SEL(1:0) = 11
Minimum
Typical
75
Maximum
Units
MHz
MHz
MHz
MHz
100
fOUT
Output Frequency
150
300
75MHz,
1.33
1.53
ps
ps
ps
ps
Integration Range: 12kHz – 20MHz
100MHz,
Integration Range: 12kHz – 20MHz
RMS Phase Jitter
(Random); NOTE 1
tjit(Ø)
150MHz,
Integration Range: 12kHz – 20MHz
300MHz,
Integration Range: 12kHz – 20MHz
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
400
50
ps
%
Using a 25MHz, 18pF quartz crystal.
NOTE 1: Please refer to the Phase Noise plot.
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ICS844441I
FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Typical Phase Noise at 100MHz
100MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 1.53ps (typical)
Raw Phase Noise Data
Offset Frequency (Hz)
NOTE: Measured on Aeroflex PN9000
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FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Parameter Measurement Information
Phase Noise Plot
SCOPE
Qx
V
DD
2.5V 5%
POWER SUPPLY
Phase Noise Mask
+
Float GND –
LVDS
nQx
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
2.5V LVDS Output Load AC Test Circuit
RMS Phase Jitter
nQ
Q
nQ
80%
tF
80%
tR
tPW
VOD
tPERIOD
20%
20%
Q
tPW
VOS
GND
odc =
x 100%
tPERIOD
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
V
OD/∆ VOD
DC Input
100
out
➤
VOS/∆ VOS
➤
Offset Voltage Setup
Differential Output Voltage Setup
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FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Application Information
Crystal Input Interface
The ICS844441I has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
Figure 1. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 2. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VCC
VCC
R1
0.1µf
50Ω
Ro
Rs
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
Figure 2. General Diagram for LVCMOS Driver to XTAL Input Interface
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FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Recommendations for Unused Input Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pull-ups; additional resistance is not
required but can be added for additional protection. A 1kΩ resistor
can be used.
2.5V LVDS Driver Termination
Figure 3 shows a typical termination for LVDS driver in
characteristic impedance of 100Ω differential (50Ω single)
transmission line environment. For buffer with multiple LVDS driver,
it is recommended to terminate the unused outputs.
2.5V
50Ω
2.5V
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 3. Typical LVDS Driver Termination
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FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS844441I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844441I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
Total Power MAX = VDD_MAX * IDD_MAX = 2.625V * 45mA = 118.125mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 96°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.118W * 96°C/W = 96.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the supply voltage, air flow and the type of board (single layer or
multi-layer).
Table 6A. Thermal Resistance θJA for 16 Lead TSSOP, Forced Convection
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92.4°C/W
88.0°C/W
85.9°C/W
Table 6B. Thermal Resistance θJA for 8 Lead SOIC, Forced Convection
θJA vs. Air Flow
Linear Feet per Second
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
96°C/W
87°C/W
82°C/W
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FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Reliability Information
Table 7A. θJA vs. Air Flow Table for a 16 Lead TSSOP
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
92.4°C/W
88.0°C/W
85.9°C/W
Table 7B. θJA vs. Air Flow Table for a 8 Lead SOIC
θJA vs. Air Flow
Linear Feet per Second
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
96°C/W
87°C/W
82°C/W
Transistor Count
The transistor count for ICS844441I is: 6431
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FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Package Outline and Package Dimensions
Package Outline - G Suffix for 16-Lead TSSOP
Package Outline - M Suffix for 8 Lead SOIC
Table 8B. Package Dimensions for 8 Lead SOIC
All Dimensions in Millimeters
Table 8A. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
Symbol
Minimum
Maximum
N
A
A1
B
C
D
E
8
N
A
16
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
e
1.27 Basic
E
6.40 Basic
H
h
L
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
E1
e
L
4.30
4.50
0.65 Basic
0.45
0°
0.75
8°
α
α
aaa
0.10
Reference Document: JEDEC Publication 95, MS-012
Reference Document: JEDEC Publication 95, MO-153
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FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Ordering Information
Table 9. Ordering Information
Part/Order Number
844441AGI
844441AGIT
844441AGILF
844441AGILFT
Marking
TBD
TBD
44441AIL
44441AIL
TBD
Package
16 Lead TSSOP
16 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
16 Lead “Lead-Free” TSSOP
16 Lead “Lead-Free” TSSOP
8 Lead SOIC
844441AMI-75
844441AMI-75T
844441AMI-75LF
844441AMI-75LFT
844441AMI-100
844441AMI-100T
844441AMI-100LF
844441AMI-100LFT
844441AMI-150
844441AMI-150T
844441AMI-150LF
844441AMI-150LFT
844441AMI-300
844441AMI-300T
844441AMI-300LF
844441AMI-300LFT
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
8 Lead SOIC
8 Lead “Lead-Free” SOIC
8 Lead “Lead-Free” SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead “Lead-Free” SOIC
8 Lead “Lead-Free” SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead “Lead-Free” SOIC
8 Lead “Lead-Free” SOIC
8 Lead SOIC
8 Lead SOIC
8 Lead “Lead-Free” SOIC
8 Lead “Lead-Free” SOIC
2500 Tape & Reel
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
Table 10. Additional Ordering Information
Part/Order Number
844441AGI
844441AMI-75
844441AMI-100
844441AMI-150
844441AMI-300
Package
16 TSSOP
8 SOIC
8 SOIC
8 SOIC
Output Frequency (MHz)
75, 100, 150, 300
75
100
150
300
8 SOIC
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
IDT™ / ICS™ SAS/SATA CLOCK GENERATOR
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FEMTOCLOCKTM SAS/SATA CLOCK GENERATOR
PRELIMINARY
Contact Information:
www.IDT.com
Corporate Headquarters
Sales
Technical Support
Integrated Device Technology, Inc.
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
www.IDT.com/go/contactIDT
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
www.IDT.com
Printed in USA
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