844S012AKILF [IDT]
Clock Generator, 250MHz, CMOS, 8 X 8 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-56;
| 型号： | 844S012AKILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 250MHz, CMOS, 8 X 8 MM, 0.90 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-56 时钟 外围集成电路 晶体 |
| 文件： | 总23页 (文件大小：877K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Crystal-to-LVDS/LVCMOS
Frequency Synthesizer
ICS844S012I
DATA SHEET
General Description
Features
The ICS844S012I is an optimized PCIe, sRIO and
Gigabit Ethernet Frequency Synthesizer. The
ICS844S012I uses a 25MHz parallel resonant crystal
to generate 33.33MHz - 200MHz clock signals,
replacing solutions requiring multiple oscillator and
• Two differential LVDS outputs (Bank A), configurable for PCIe
(100MHz or 250MHz) and sRIO (100MHz or 125MHz) clock
signals
S
IC
HiPerClockS™
• Eight LVCMOS/LVTTL outputs (Bank B/C), 18Ω typical output
impedance
fanout buffer solution. The device supports 0.25% center-spread,
and -0.6% down-spread clocking with two spread select pins
(SSC[1:0]). The VCO operates at frequency of 2GHz. The device has
three output banks: Bank A with two LVDS outputs, 100MHz –
250MHz; Bank B with seven 33.33MHz – 200MHz LVCMOS/ LVTTL
outputs; and Bank C with one 33.33MHz – 200MHz LVCMOS/LVTTL
output.
• Two REF_OUT LVCMOS/LVTTL clock outputs 23Ω typical output
impedance
• Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or one LVCMOS/LVTTL single-ended reference
clock input
• Supports the following output frequencies:
LVDS Bank A: 100MHz, 125MHz, 200MHz and 250MHz
LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz,
100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz
All Banks A, B and C have their own dedicated frequency select pins
and can be independently set for the frequencies mentioned above.
The low jitter characteristic of the ICS844S012I makes it an ideal
clock source for PCIe, sRIO and Gigabit Ethernet applications.
Designed for networking and industrial applications, the
• VCO: 2GHz
• Spread spectrum clock: 0.25% center-spread, and
-0.6% down-spread
• PLL bypass and output enable
ICS844S012I can also drive the high-speed clock inputs of
communication processors, DSPs, switches and bridges.
• RMS period jitter: 17ps (maximum), QB outputs
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in a lead-free (RoHS 6) compliant package
Pin Assignment
56 55 54 53 52 51 50 49 48 47 46 45 44 43
42
41
VDD
1
VDDOC
QC
REF_OUT0
2
GND
QBC_OE
VDDA
VDDA
GND
GND
GND
QA0
3
40
39
38
37
36
35
34
33
32
31
30
29
REF_OUT1
GND
4
5
ICS844S012I
56-Lead VFQFN
8mm x 8mm x 0.925mm
package body
K Package
GND
6
REF_IN
VDD
7
REF_SEL
XTAL_IN
XTAL_OUT
BYPASS
8
9
10
11
12
13
14
Top View
nQA0
QA1
nQA1
REF_OE
nMR
VDD
VDD
15 16 17 18 19 20 21 22 23 24 25 26 27 28
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Block Diagram
Pullup
QA_OE
2
Pulldown
F_SELA[1:0]
QA0
nQA0
QA1
Pulldown
BYPASS
÷NA
25MHz
XTAL_IN
nQA1
1
0
OSC
0
1
XTAL_OUT
PLL
VCO
2GHz
QB0
Pulldown
REF_IN
QB1
QB2
Pulldown
REF_SEL
M = ÷80
QB3
QB4
÷NB
3
Pulldown
F_SELB[2:0]
QB5
QB6
QC
÷NC
3
2
Pulldown
F_SELC[2:0]
Pullup
nMR
Pullup
QBC_OE
Spread
Spectrum
Pullup
SSC[1:0]
REF_OUT0
REF_OUT1
Pulldown
REF_OE
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 7, 14, 28, 29
VDD
Power
Output
Core supply pins.
2,
3
REF_OUT0,
REF_OUT1
Single-ended reference clock outputs. 23Ω typical output
impedance. LVCMOS/LVTTL interface levels.
4, 5, 15,
27, 34, 35, 36,
40, 46, 50, 54
GND
Power
Power supply ground.
Single-ended reference clock input. LVCMOS/LVTTL interface
levels.
6
8
REF_IN
Input
Input
Input
Input
Input
Pulldown
Reference select pin. When HIGH selects REF_IN. When LOW,
selects crystal. See Table 3E. LVCMOS/LVTTL interface levels.
REF_SEL
Pulldown
9,
10
XTAL_IN
XTAL_OUT
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
PLL bypass. When HIGH, bypasses PLL. When LOW, selects PLL.
See Table 3J. LVCMOS/LVTTL interface levels.
11
12
BYPASS
REF_OE
Pulldown
Pulldown
Active HIGH REF_OUT enable/disable pin. See Table 3F.
LVCMOS/LVTTL interface levels.
Active LOW Master Reset. When logic LOW, the internal dividers
are reset. When logic HIGH, the internal dividers are enabled. This
device requires a reset signal after powerup. See Table 3G.
LVCMOS/LVTTL interface levels.
13
nMR
Input
Pullup
16, 17
SSC1, SSC0
Input
Input
Pullup
SSC control pins. See Table 3D. LVCMOS/LVTTL interface levels.
18,
19, 20
F_SELB2,
F_SELB1, F_SELB0
Frequency select pins for QBx outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
Pulldown
21,
22, 23
F_SELC2,
F_SELC1, F_SELC0
Frequency select pins for QC output. See Table 3C.
LVCMOS/LVTTL interface levels.
Input
Input
Input
Pulldown
Pulldown
Pullup
Frequency select pins for QAx/nQAx outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
24, 25
26
F_SELA1, F_SELA0
QA_OE
Output enable pin for Bank A outputs. See Table 3H.
LVCMOS/LVTTL interface levels.
30, 31
32, 33
nQA1, QA1
nQA0, QA0
Output
Power
Input
Differential Bank A clock output pairs. LVDS interface levels.
Analog supply pins.
37, 38
VDDA
Output enable pin for Bank B and Bank C outputs. See Table 3I.
LVCMOS/LVTTL Interface levels.
39
QBC_OE
Pullup
Single-ended Bank C clock output. LVCMOS/LVTTL interface
levels. 18Ω typical output impedance.
41
QC
Output
42
VDDOC
VDDOB
Power
Power
Output supply pin for QC LVCMOS output.
Output supply pins for QBx LVCMOS outputs.
43, 48, 52, 56
44, 45, 47,
49, 51, 53, 55
QB0, QB1, QB2,
QB3, QB4, QB5, QB6
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface
levels. 18Ω typical output impedance.
Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
2
pF
Power Dissipation
Capacitance
CPD
QB[0:6], QC
VDDOB, VDDOC = 3.465V
4
pF
RPULLUP
Input Pullup Resistor
51
51
18
23
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
QB[0:6], QC
VDDOB, VDDOC = 3.3V
VDDOB, VDDOC = 3.3V
ROUT
Output Impedance
REF_OUT[0:1]
Ω
Function Tables
Table 3A. F_SELA[1:0] Frequency Select Function Table
Inputs
Output Frequency (25MHz Reference)
F_SELA1
F_SELA0
M Divider Value
NA Divider Value
QA[0:1], nQA[0:1] – (MHz)
0
0
1
1
0
1
0
1
80
80
80
80
20
16
10
8
100 (default)
125
200
250
Table 3B. F_SELB[2:0] Frequency Select Function Table
Inputs
Output Frequency (25MHz Reference)
F_SELB2
F_SELB1
F_SELB0
M Divider Value
NB Divider Value
QB[0:6] – (MHz)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
80
80
80
80
80
80
80
80
60
40
30
20
16
15
12
10
33.33 (default)
50
66.67
100
125
133.33
166.67
200
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 3C. F_SELC[2:0] Frequency Select Function Table
Inputs
Output Frequency (25MHz Reference)
F_SELC2
F_SELC1
F_SELC0
M Divider Value
NC Divider Value
QC – (MHz)
33.33 (default)
50
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
80
80
80
80
80
80
80
80
60
40
30
20
16
15
12
10
66.67
100
125
133.33
166.67
200
Table 3D. SSC_SEL[1:0] Function Table
Inputs
SSC1
SSC0
Mode
0
0
1
1
0
1
0
1
0 to -0.6% Down-spread
0.25% Center-spread
0.25% Center-spread
SSC Off (default)
Table 3E. REF_SEL Function Table
Input
REF_SEL
0 (default)
1
Input Reference
XTAL
REF_IN
Table 3F. REF_OE Function Table
Input
REF_OE
0 (default)
1
Function
REF_OUT[0:1] - Disabled (High-Impedance)
REF_OUT[0:1] - Enabled
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 3G. nMR Function Table
Input
nMR
0
Function
Device reset, output divider - Disabled
Output - Enabled
1 (default)
NOTE: This device requires a reset signal after power-up to function properly.
Table 3H. QA_OE Function Table
Input
QA_OE
0
Function
QA[0:1], nQA[0:1] - Disabled (High-Impedance)
QA[0:1], nQA[0:1] - Enabled
1 (default)
Table 3I. QBC_OE Function Table
Input
QBC_OE
0
Function
QB[0:6] and QC - Disabled (High-Impedance)
QB[0:6] and QC - Enabled
1 (default)
Table 3J. BYPASS Function Table
Input
BYPASS
0 (default)
1
Function
PLL
Bypass (reference ÷N)
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
0V to VDD
Other Inputs
-0.5V to VDDOx + 0.5V
Outputs, VO (LVCMOS)
-0.5V to VDDOx + 0.5V
Outputs, IO (LVDS)
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
31.4°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDOB = VDDOC = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
Units
VDD
Core Supply Voltage
V
V
VDDA
Analog Supply Voltage
Output Supply Voltage
VDD – 0.20
3.3
VDD
VDDOB,
VDDOC
3.135
3.3
3.465
V
IDD
Power Supply Current
Analog Supply Current
285
20
mA
mA
IDDA
IDDOA
IDDOB
+
Output Supply Current
1
mA
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDOB = VDDOC = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.2
Typical
Maximum
VDD + 0.3
0.8
Units
VIH
VIL
Input High Voltage
Input Low Voltage
nMR, SSC[1:0],
V
V
-0.3
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
10
µA
µA
µA
µA
QA_OE, QBC_OE
Input
High Current
REF_IN, REF_SEL,
BYPASS, REF_OE,
F_SELA[1:0], F_SELB[2:0],
F_SELC[2:0]
IIH
150
nMR, SSC[1:0],
QA_OE, QBC_OE
V
-150
-10
Input
Low Current
REF_IN, REF_SEL,
BYPASS, REF_OE,
F_SELA[1:0], F_SELB[2:0],
F_SELC[2:0]
IIL
VDD = 3.465V, VIN = 0V
VDDOB, VDDOC, VDDO_REF
IOH = -2mA
=
=
Output
High Voltage
VOH
QBx, QC, REF_OUTx
QBx, QC, REF_OUTx
2.6
V
V
VDDOB, VDDOC, VDDO_REF
IOH = 2mA
Output
Low Voltage
VOL
0.5
Table 4C. LVDS DC Characteristics, VDD = 3.3V 5ꢀ, TA = -40°C to 85°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
454
Units
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
247
∆VOD
VOS
50
mV
V
1.125
1.375
50
∆VOS
VOS Magnitude Change
mV
Table 5. Crystal Characteristics
Parameter
Test Conditions
Minimum
Typical
Fundamental
25
Maximum
Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
50
7
pF
NOTE: Characterized using an 18pF parallel resonant crystal.
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = VDDOB = VDDOC = TA = -40°C to +85°C
Symbol Parameter
Test Conditions
Minimum
100
Typical
Maximum
250
Units
MHz
MHz
MHz
ps
QA[0:1], nQA[0:1]
QB[0:6]
Output
fOUT
33.33
200
Frequency
QC
33.33
200
QB[0:6]
60
Bank Skew
tsk(b)
NOTE 1, 2
QA[0:1], nQA[0:1]
LVCMOS Outputs off
10
ps
Across Banks B and C
at Same Frequency
tsk(o)
Output Skew; NOTE 2, 3
620
55
80
50
9
ps
ps
ps
ps
ps
All Outputs at the Same Frequency,
REF_OE = 0
QA[0:1], nQA[0:1]
QB[0:6]
Cycle-to-Cycle
Jitter; NOTE 2
All Outputs at the Same Frequency,
REF_OE = 0
tjit(cc)
All Outputs at the Same Frequency,
REF_OE = 0
QC
All Outputs at the Same Frequency,
REF_OE = 0
QA[0:1], nQA[0:1]
QBx, QC = 33.33MHz,
QAx, nQAx = 100MHz,
REF_OE = 0
RMS
Period Jitter
tjit(per)
17
ps
QB[0:6], QC
All Outputs at the same Frequency,
REF_OE = 0
11
ps
SSC Modulation QA[0:1], nQA[0:1]
FM
tL
29
33.33
kHz
Frequency
QB[0:6], QC
SSC off
SSC on
100
2.1
450
250
52
ms
s
PLL Lock Time
QB[0:6], QC
20% to 80%
150
65
ps
ps
%
%
%
Output
tR / tF
odc
Rise/Fall Time
QA[0:1], nQA[0:1]
QA[0:1], nQA[0:1]
QB[0:6], QC
20% to 80%
LVCMOS Outputs OFF
Output Frequency ≤ 133.33MHz
Output Frequency > 133.33MHz
48
Output
Duty Cycle
48
52
QB[0:6], QC
46
54
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOB/2.
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information
1.65V 5%
1.65V 5%
SCOPE
SCOPE
V
DD,
V
DD
Qx
V
3.3V 5%
POWER SUPPLY
DDOB,
DDOC
V
V
Qx
V
DDA
DDA
LVCMOS
+
Float GND –
LVDS
nQx
GND
-1.65V 5%
3.3V LVDS Output Load AC Test Circuit
3.3V LVCMOS Output Load AC Test Circuit
nQAx
QAx
VDDOX
2
QBx
QBy
nQAy
VDDOX
2
QAy
tsk(b)
tsk(b)
LVDS Bank Skew
LVCMOS Bank Skew
QB[0:6],
QC,
REF_OUT0,
nQA[0:1]
VDDOX
2
VDDOX
2
VDDOX
2
REF_OUT1
QA[0:1]
➤
➤
➤
➤
tcycle n
tcycle n+1
➤
➤
tcycle n
tcycle n+1
➤
➤
tjit(cc) = tcycle n – tcycle n+1
|
|
tjit(cc) = tcycle n – tcycle n+1
|
|
1000 Cycles
1000 Cycles
LVCMOS Cycle-to-Cycle Jitter
LVDS Cycle-to-Cycle Jitter
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
VOH
VDDOX
VREF
Qx
Qy
2
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
VDDOX
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
2
tsk(o)
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
LVCMOS Output Skew
RMS Period Jitter
nQA[0:1]
QA[0:1]
80%
tF
80%
80%
80%
tR
QB[0:6],
QC,
REF_OUT0,
VOD
20%
20%
20%
20%
REF_OUT1
tR
tF
LVCMOS Rise/Fall Time
LVDS Output Rise/Fall Time
VDDOX
2
nQA[0:1]
QB[0:6],
QC,
REF_OUT0,
QA[0:1]
tPW
tPW
tPERIOD
tPERIOD
REF_OUT1
tPW
tPW
odc =
x 100%
x 100%
odc =
tPERIOD
tPERIOD
LVCMOS Output Duty Cycle/Pulse Width/Period
LVDS Output Duty Cycle/Pulse Width/Period
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Parameter Measurement Information, continued
VDD
VDD
out
➤
out
➤
DC Input
LVDS
LVDS
V
OD/∆ VOD
DC Input
100
out
➤
VOS/∆ VOS
out
➤
Offset Voltage Setup
Differential Output Voltage Setup
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVCMOS Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
All unused LVCMOS output can be left floating. We recommend that
there is no trace attached.
LVDS Outputs
Crystal Inputs
All unused LVDS outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied from
XTAL_IN to ground.
REF_IN Input
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the REF_IN to ground.
ICS844S012AKI REVISION A APRIL 2, 2010
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©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS844S012I provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA, VDDOB and VDDO should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10Ω resistor along with a 10µF bypass
capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 2. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 2. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS844S012AKI REVISION A APRIL 2, 2010
13
©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Crystal Input Interface
The ICS844S012I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 3 below
were determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
XTAL_IN
C1
18pF
X1
18pF Parallel Crystal
XTAL_OUT
C2
18pF
Figure 3. Crystal Input Interface
Overdriving the XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4A. The XTAL_OUT pin can be left floating. The
maximum amplitude of the input signal should not exceed 2V and the
input edge rate can be as slow as 10ns. This configuration requires
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the signal in
half. This can be done in one of two ways. First, R1 and R2 in parallel
should equal the transmission line impedance. For most 50Ω
applications, R1 and R2 can be 100Ω. This can also be accomplished
by removing R1 and making R2 50Ω. By overdriving the crystal
oscillator, the device will be functional, but note, the device
performance is guaranteed by using a quartz crystal.
3.3V
3.3V
R1
100
C1
Ro
~ 7 Ohm
Zo = 50 Ohm
XTAL_I N
RS
43
0.1uF
R2
Driver_LVCMOS
100
XTAL_OU T
Crystal Input Interf ace
Figure 4A. General Diagram for LVCMOS Driver to XTAL Input Interface
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
0.1uF
R1
Zo = 50 Ohm
50
XTAL_OUT
LVPECL
Cry stal Input Interface
R2
50
R3
50
Figure 4B. General Diagram for LVPECL Driver to XTAL Input Interface
ICS844S012AKI REVISION A APRIL 2, 2010
14
©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. Standard termination
for LVDS type output structure requires both a 100Ω parallel resistor
at the receiver and a 100Ω differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100Ω
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 4 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the input receivers amplitude and
common mode input range should be verified for compatibility with
the output.
+
LVDS
Receiver
–
LVDS Driver
100Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
ICS844S012AKI REVISION A APRIL 2, 2010
15
©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Schematic Example
Figure 6 shows an example of ICS844S012I application schematic.
optimizing frequency accuracy. Two examples of LVDS terminations
and one example of an LVCMOS termination are shown in this
schematic. The decoupling capacitors should be located as close as
possible to the power pin.
In this example, the device is operated at VDD = VDDOB = VDDOC
=
3.3V. The 18pF parallel resonant 25MHz crystal is used. The C1 and
C2 = 18pF and are recommended for frequency accuracy. For
different board layouts, the C1 and C2 may be slightly adjusted for
Logic Control Input Examples
R1
R3
35
30
Zo = 50
QB0
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
VDD
R2
10
LVCMOS
LVCMOS
VDDA
RU1
1K
RU2
Not Install
VDDO
C5
10u
C6
0.01u
VDD
Zo = 50
To Logic
Input
To Logic
Input
pins
REF_OUT1
pins
RD1
RD2
1K
VDD
Not Install
VDDO
R4
10
VDDA
U1
C3
C4
10u
VDD
0.01u
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD
VDDOC
QC
2
3
REF_OUT0
REF_OUT1
Q1
REF_OUT0
REF_OUT1
GND
Zo = 50 Ohm
Zo = 50 Ohm
GND
4
Ro
~
7
Ohm
QA0
R5
Zo = 50 Ohm
QBC_OE
VDDA
VDDA
GND
5
REF_IN
XTAL_IN
GND
6
REF_IN
VDD
+
-
7
43
R6
8
REF_SEL
100
REF_SEL
XTAL_IN
XTAL_OUT
BYPASS
REF_OE
nMR
GND
9
Driv er_LVCMOS
25MHz, CL=18pF
GND
10
11
12
13
14
QA0
QA0
BYPASS
REF_OE
nMR
nQA0
QA1
C2
nQA0
QA1
nQA0
18pF
X1
nQA1
nQA1
VDD
VDD
XTAL_OUT
C1
VDD=3.3V
VDDOB=3.3V
VDDOC=3.3V
18pF
LVDS Termination
Note: This device requires a
reset signal at nMR after
power-up to function properly.
Zo = 50 Ohm
QA1
R7
50
+
-
VDDO
VDD
VDDO
VDD
(U1, 42)
(U1, 43)
(U1, 48)
(U1, 52)
(U1, 56)
(U1, 1)
(U1, 7) (U1, 14)
(U1, 28)
(U1, 29)
C7
0.1uF
R8
50
C8
0.1u
C9
C10
0.1u
C11
0.1u
C12
C13
0.1u
C14
0.1u
C15
0.1u
C16
C17
0.1u
Zo = 50 Ohm
nQA1
0.1u
0.1u
0.1u
Alternate
LVDS
Termination
Figure 6. ICS844S012I Schematic Example
ICS844S012AKI REVISION A APRIL 2, 2010
16
©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Spread Spectrum
Spread-spectrum clocking is a frequency modulation technique for
EMI reduction. When spread-spectrum is enabled, a 32kHz triangle
waveform is used with 0.6% down-spread (+0.0% / -0.6%) from the
nominal output frequency. An example of a triangle frequency
modulation profile is shown in Figure 7A below. The ramp profile can
be expressed as:
The ICS844S012I triangle modulation frequency deviation will not
exceed 0.7% down-spread from the nominal clock frequency (+0.0%
/ -0.6%). An example of the amount of down spread relative to the
nominal clock frequency can be seen in the frequency domain, as
shown in Figure 7B. The ratio of this width to the fundamental
frequency is typically 0.4%, and will not exceed 0.7%. The resulting
spectral reduction will be greater than 5dB, as shown in Figure 7B. It
is important to note the ICS844S012I 5dB minimum spectral
reduction is the component-specific EMI reduction, and will not
necessarily be the same as the system EMI reduction.
Fnom = Nominal Clock Frequency in Spread Off mode
Fm = Nominal Modulation Frequency (30kHz)
δ = Modulation Factor (0.6% down spread)
1
----------- ,
2Fm
(1 – δ)Fnom + 2Fm × δ × Fnom × t when0< t <
1
1
-----------
2Fm
-------
Fm
(1 – δ)Fnom–2Fm × δ × Fnom × t when
< t <
Fnom
∆ – 10 dBm
A
B
(1 - δ) Fnom
➔
δ = 0.6% ➔
➤
0.5/fm
Time
1/fm
Figure 7A. Triangle Frequency Modulation
Figure 7B. 200MHz Clock Output In Frequency Domain
(A) Spread-Spectrum OFF
(B) Spread-Spectrum ON
ICS844S012AKI REVISION A APRIL 2, 2010
17
©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS44S012I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS44S012I is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
The maximum current at 85° is as follows:
IDD_MAX = 270mA
IDDA_MAX = 20mA
I
DDO_MAX = 1mA
Core and LVDS Output Power Dissipation
Power (core, LVDS) = VDD_MAX * (IDD + IDDA + IDDO) = 3.465V * (270mA + 20mA + 1mA) = 1008.315mW
LVCMOS Output Power Dissipation
•
•
Dynamic Power Dissipation at 200MHz, (QB, QC)
Power (200MHz) = CPD * Frequency * (VDDO)2 = 4pF * 200MHz * (3.465V)2 = 9.6mW per output
Total Power (200MHz) = 9.6mW * 8 = 76.7mW
•
Dynamic Power Dissipation at 25MHz
Power (25MHz) = CPD * Frequency * (VDDO)2 = 4pF * 25MHz * (3.465V)2 = 1.2mW per output
Total Power (25MHz) = 1.2mW * 2 = 2.4mW
Total Power Dissipation
•
Total Power
= Power (core, LVDS) + Total Power (200MHz) + Total Power (25MHz)
= 1008.315mW + 76.7mW + 2.4mW
= 1087.415mW
ICS844S012AKI REVISION A APRIL 2, 2010
18
©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 31.4°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.087W * 31.4°C/W = 119.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 56 Lead VFQFN, Forced Convection
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
31.4°C/W
27.5°C/W
24.6°C/W
ICS844S012AKI REVISION A APRIL 2, 2010
19
©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Reliability Information
Table 8. θJA vs. Air Flow Table for a 56 Lead VFQFN
θJA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
31.4°C/W
27.5°C/W
24.6°C/W
Transistor Count
The transistor count for ICS844S012I is: 11,509
ICS844S012AKI REVISION A APRIL 2, 2010
20
©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Package Outline and Package Dimensions
Package Outline - K Suffix for 56 Lead VFQFN
(Ref.)
Seating Plane
N & N
(N -1)x e
(Ref.)
Even
A1
IndexArea
L
A3
E2
e
2
N
N
(Ty p.)
If N & N
are Even
Anvil
1
Singulation
2
or
(N -1)x e
(Ref.)
Sawn
E2
2
Singulation
TopView
D
b
(Ref.)e
N &N
Odd
Thermal
Base
A
D2
2
0. 08
C
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
D2
C
Bottom View w/Type A ID
Bottom View w/Type B ID
Bottom View w/Type C ID
4
2
1
2
1
2
1
CHAMFER
RADIUS
4
N N-1
N N-1
DD
N N-1
4
4
There are 3 methods of indicating pin 1 corner
at the back of the VFQFN package are:
1. Type A: Chamfer on the paddle (near pin 1)
2. Type B: Dummy pad between pin 1 and N.
4
AA
4
3. Type C: Mouse bite on the paddle (near pin 1)
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This drawing
is not intended to convey the actual pin count or pin layout of this
device. The pin count and pinout are shown on the front page. The
package dimensions are in Table 9.
Table 9. Package Dimensions
SPEC NON_JEDEC: VLLD-2/-5
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
56
A
A1
0.80
0
1.00
0.05
A3
0.25 Ref.
b
0.18
0.30
ND & NE
D & E
D2
14
8.00 Basic
4.35
5.05
4.65
5.35
E2
e
0.50 Basic
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
ICS844S012AKI REVISION A APRIL 2, 2010
21
©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number
844S012AKILF
844S012AKILFT
Marking
ICS844S012AIL
ICS844S012AIL
Package
“Lead-Free” 56 Lead VFQFN
“Lead-Free” 56 Lead VFQFN
Shipping Packaging
Tray
1000 Tape & Reel
Temperature
-40°C to +85°C
-40°C to +85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS844S012AKI REVISION A APRIL 2, 2010
22
©2010 Integrated Device Technology, Inc.
ICS844S012I Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
San Jose, California 95138
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2010. All rights reserved.
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