853052AG [IDT]
Clock Driver;
| 型号： | 853052AG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver |
| 文件： | 总14页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL
2.5V, 3.3V, 5V LVPECL MULTIPLEXER
ICS853052
GENERAL DESCRIPTION
FEATURES
The ICS853052 is a Dual LVCMOS / LVTTL-to-
• One differential 2.5V, 3.3V or 5V LVPECL output
• Two selectable LVCMOS/LVTTL clock inputs
• Output frequency: TBD
ICS
HiPerClockS™
Differential 2.5V, 3.3V, 5V LVPECL Multiplexer and
a member of the HiPerClocks™ family of High
Performance Clocks Solutions from IDT. The
ICS853052 has two selectable single ended clock
• Additive phase jitter, RMS: 0.06ps (typical)
• Propagation Delay: 370ps (typical)
inputs.The single ended clock input accepts LVCMOS or LVTTL
input levels and translates them to 2.5V, 3.3V or 5V LVPECL
levels. The small outline 8-pin TSSOP or 8-pin SOIC packages
make this device ideal for applications where space, high
performance and low power are important.
• 2.5V, 3.3V or 5V operating supply voltage
(operating range 2.375V to 5.5V)
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
nc
Da
VCC
Q
1
2
3
4
8
7
6
5
Db
SEL
nQ
VEE
Pulldown
Da
1
Q
nQ
ICS853052
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Pulldown
Db
0
Top View
Pulldown
SEL
8-Lead SOIC, 150 mil
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
nc
Type
Description
1
Unused
Input
No connect.
2, 3
Da, Db
Pulldown LVCMOS / LVTTL clock inputs.
Select input pin. When HIGH, selects Da input clock.
4
SEL
Input
Pulldown When Low selects Db input clock.
Single-ended 100H LVPECL interface levels.
5
6, 7
8
VEE
nQ, Q
VCC
Power
Output
Power
Negative supply pin.
Differential output pair. LVPECL interface levels.
Positive supply pin.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pulldown Resistor
1
pF
RPULLDOWN
75
kΩ
TABLE 3. CONTROL INPUT FUNCTION TABLE
Inputs
SEL
0
Selected Source
Db
Da
1
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
6V (LVPECL mode, VEE = 0)
-6V (ECL mode, VCC = 0)
-0.5V to VCC + 0.5 V
NOTE: Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the DC Characteristics or AC Characteristics is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 101.7°C/W (0 m/s) TSSOP
112.7°C/W (0 lfpm) SOIC
(Junction-to-Ambient)
TABLE 4A. DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
-40°C
Typ
21
25°C
Typ
21
85°C
Typ
21
Symbol Parameter
Min
Units
Max
Min
Max
Min
Max
IEE
Power Supply Current
mA
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
1.375 1.475
0.605 0.745
1.58
0.88
1.425
0.625
1.495
0.72
1.57
1.495
0.64
1.53
1.565
0.83
V
0.815
0.735
Input High Voltage,
Single-Ended
V
VIH
1.275
0.63
1.56
1.275
0.63
1.56
1.275
0.63
-0.83
V
VIL
IIH
Input Low Voltage, Single-Ended
Input High Current
0.965
200
0.965
200
0.965
200
µA
µA
IIL
Input Low Current
200
200
200
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4B. DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
-40°C
Typ
21
25°C
Typ
21
85°C
Typ
21
Symbol Parameter
Min
Units
Max
Min
Max
Min
Max
IEE
VOH
VOL
VIH
VIL
IIH
Power Supply Current
mA
mV
mV
mV
mV
µA
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage, Single-Ended
Input Low Voltage, Single-Ended
Input High Current
2175
1405
2075
1355
2275
1545
2380
1680
2420
1675
200
2225
1425
2075
1355
2295
1520
2370
1615
2420
1675
200
2295
1440
2075
1355
2330
1535
2365
1630
2420
1675
200
IIL
Input Low Current
200
200
200
µA
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
TABLE 4C. DC CHARACTERISTICS, VCC = 5V; VEE = 0V
-40°C
Typ
21
25°C
Typ
21
85°C
Typ
21
Symbol Parameter
Units
Min
Max
Min
Max
Min
Max
IEE
VOH
VOL
VIH
VIL
IIH
Power Supply Current
mA
mV
mV
mV
mV
µA
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage, Single-Ended
Input Low Voltage, Single-Ended
Input High Current
3875
3105
3775
3055
200
3975
3245
4105
3380
4120
3375
4080
3125
3775
3055
200
3925
3220
3995
3315
4120
3375
4070
3140
3775
3055
200
3995
3235
4065
3330
4120
3375
200
IIL
Input Low Current
200
200
µA
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -2.375V
-40°C
25°C
Typ
21
85°C
Typ
21
Symbol Parameter
Units
Min
Typ
Max
Min
Max
Min
Max
IEE
VOH
VOL
VIH
VIL
IIH
Power Supply Current
21
mA
mV
mV
mV
mV
µA
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage, Single-Ended
Input Low Voltage, Single-Ended
Input High Current
-1125 -1025
-920
-1075 -1005
-930
-1005
-970
-935
-1895 -1755 -1620 -1875 -1780 -1685 -1860 -1765 -1670
-1225
-1945
-880
-1225
-880
-1225
-880
-1625
200
-1625 -1945
-1625 -1945
200
200
200
200
IIL
Input Low Current
200
µA
Input and output parameters vary 1:1 with VCC.
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -5.5V TO -2.375V OR VCC = 2.375V TO 5.5V; VEE = 0V
-40°C
Typ
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Max
Min
Max
Min
Max
fMAX
Output Frequency
TBD
TBD
TBD
GHz
ps
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter section
tPLH
TBD
TBD
370
370
TBD
TBD
tPHL
ps
ps
tjit
TBD
0.06
TBD
VPP
Input Voltage Swing (Differential)
TBD
TBD
TBD
180
TBD
TBD
ps
ps
Output
tR/tF
20% to 80%
Rise/Fall Time
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from VCC/2 of the input crossing point to the differential output crossing point.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
ADDITIVE PHASE JITTER
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
0
-10
-20
-30
-40
Additive Phase Jitter @ 155.52MHz
(12kHz to 20MHz) = 0.06ps typical
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
100
1k
10k
100k
1M
10M
100M
-190
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
SCOPE
VCC
Qx
Da Db
nQ
LVPECL
Q
nQx
tPD
VEE
-3.5V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
PROPAGATION DELAY
80%
tF
80%
VSWING
20%
Clock
20%
Outputs
tR
OUTPUT RISE/FALL TIME
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
DX INPUTS
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the Dx input to
ground.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 1A and Figure 1B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground
level. The R3 in Figure 1B can be eliminated and the termination
is shown in Figure 1C.
CC
CC
CC
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
Zo = 50 Ohm
R1
250
R3
250
+
-
Zo = 50 Ohm
Zo = 50 Ohm
+
-
2,5V LVPECL
Driver
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 1A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 1B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 1C. 2.5V LVPECL TERMINATION EXAMPLE
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 2A and 2B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
TERMINATION FOR 5V LVPECL OUTPUT
This section shows examples of 5V LVPECL output termination.
Figure 3A shows standard termination for 5V LVPECL. The
termination requires matched load of 50Ω resistors pull down to
V
- 2V = 3V at the receiver. Figure 3B shows Thevenin
CC
equivalence of Figure 3A. In actual application where the 3V DC
power supply is not available, this approached is normally used.
5V
5V
5V
5V
R3
84
R4
84
PECL
Zo = 50 Ohm
Zo = 50 Ohm
PECL
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
PECL
PECL
R1
125
R2
125
R1
50
R2
50
3V
FIGURE 3A. STANDARD 5V LVPECL OUTPUT TERMINATION
FIGURE 3B. 5V LVPECL OUTPUT TERMINATION EXAMPLE
ICS853052AG REV. B OCTOBER 24, 2007
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
8
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853052.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853052 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 5.5V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 5.5V * 21mA = 115.5mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30.94mW/Loaded Output pair
MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 112.7°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.146W * 112.7°C/W = 101.52°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θ FOR 8-PIN TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 6B. THERMAL RESISTANCE θ FOR 8-PIN SOIC, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
Figure 4. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 0.935V
CC_MAX
OUT
OH_MAX
)
= 0.935V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
– 1.67V
CC_MAX
OUT
OL_MAX
)
(V
- V
= 1.67V
CC_MAX
OL_MAX
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V ) =
OH_MAX
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
CC
OH_MAX
CC _MAX
L
L
[(2V - 0.935V)/50Ω] * 0.935V = 19.92mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
CC
OL_MAX
CC_MAX
OL_MAX
L
L
[(2V - 1.67V)/50Ω] * 1.67V = 11.02mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
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DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7A. θ VS. AIR FLOW TABLE FOR 8 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TABLE 7B. θ VS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853052 is: 110
Pin compatible with MC100EP58
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
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DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8A. PACKAGE DIMENSIONS
TABLE 8B. PACKAGE DIMENSIONS
Millimeters
Millimeters
SYMBOL
SYMBOL
MINIMUN
MAXIMUM
Minimum
Maximum
N
A
A1
B
C
D
E
e
8
N
A
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
--
1.10
0.15
0.97
0.38
0.23
A1
A2
b
0
0.79
0.22
0.08
c
D
3.00 BASIC
4.90 BASIC
3.00 BASIC
0.65 BASIC
1.95 BASIC
1.27 BASIC
E
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
E1
e
L
e1
L
α
0.40
0°
0.80
8°
Reference Document:JEDEC Publication 95, MS-012
α
aaa
--
0.10
Reference Document:JEDEC Publication 95, MO-187
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
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ICS853052AG REV. B OCTOBER 24, 2007
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DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS853052AG
Marking
052A
Package
8 lead TSSOP
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS853052AGT
ICS853052AGLF
ICS853052AGLFT
ICS853052AM
052A
8 lead TSSOP
2500 tape & reel
tube
52AL
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
8 lead SOIC
52AL
2500 tape & reel
tube
853052A
853052A
TBD
ICS853052AMT
ICS853052AMLF
ICS853052AMLFT
8 lead SOIC
2500 tape & reel
tube
8 lead "Lead-Free" SOIC
8 lead "Lead-Free" SOIC
TBD
2500 tape & reel
Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
13
ICS853052AG REV. B OCTOBER 24, 2007
ICS853052
DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V, 3.3V, 5V LVPECL MULTIPLEXER
PRELIMINARY
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Asia Pacific and Japan
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Singapore (1997) Pte. Ltd.
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Europe
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United States
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+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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