85314AGI-11 [IDT]
Low Skew Clock Driver, 85314 Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20;
| 型号： | 85314AGI-11 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 85314 Series, 5 True Output(s), 0 Inverted Output(s), PDSO20, 6.50 X 4.40 MM, 0.92 MM HEIGHT, MO-153, TSSOP-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总19页 (文件大小：842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-5 Differential-to-2.5V, 3.3V
LVPECL Fanout Buffer
ICS85314I-11
DATA SHEET
General Description
Features
The ICS85314I-11 is a low skew, high performance
1-to-5 Differential-to-2.5V/3.3V LVPECL fanout buffer.
The ICS85314I-11 has two selectable differential clock
inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can
accept most standard differential input levels. The
• Five differential 2.5V/3.3V LVPECL outputs
• Selectable differential CLKx, nCLKx inputs
S
IC
HiPerClockS™
• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the following
differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Maximum output frequency: 700MHz
clock enable is internally synchronized to eliminate runt clock pulses
on the outputs during asynchronous assertion/deassertion of the
clock enable pin.
• Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
Guaranteed output and part-to-part skew characteristics make the
ICS85314I-11 ideal for those applications demanding well defined
performance and repeatability.
• Propagation delay: 1.8ns (maximum)
• RMS phase jitter @ 155.52MHz (12kHz - 20MHz):
0.05ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
Pulldown
nCLK_EN
Q0
nQ0
Q1
1
2
20
19
VCC
nCLK_EN
D
Q
3
4
18
17
VCC
nCLK1
CK
nQ1
Q2
nQ2
Q3
5
6
7
16 CLK1
Pulldown
CLK0
nCLK0
Pullup
0
1
15
14
13
RESERVED
nCLK0
Q0
Pulldown
Pullup
nQ0
CLK1
nCLK1
CLK0
nQ3
8
Q4
nQ4
9
10
12 CLK_SEL
11
VEE
Q1
nQ1
ICS85314I-11
Q2
Pulldown
nQ2
CLK_SEL
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm package body
G Package
Q3
nQ3
Top View
Q4
nQ4
ICS85314I-11
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 2
Name
Type
Description
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Output
Output
Output
Output
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
3, 4
5, 6
7, 8
9, 10
11
Q4, nQ4
VEE
Output
Power
Differential output pair. LVPECL interface levels.
Negative supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVTTL / LVCMOS interface levels.
12
CLK_SEL
Input
Pulldown
13
14
CLK0
nCLK0
RESERVED
CLK1
Input
Input
Pulldown
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
Reserved pin.
15
Reserve
Input
16
Pulldown
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
Positive supply pins.
17
nCLK1
VCC
Input
18, 20
Power
Synchronizing clock enable. When LOW, clock outputs follow clock input. When
HIGH, Q outputs are forced low, nQ outputs are forced high.
LVTTL / LVCMOS interface levels.
19
nCLK_EN
Input
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
nCLK_EN
CLK_SEL
Selected Source
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
Q[0:4]
Enabled
nQ[0:4]
Enabled
0
0
1
1
0
1
0
1
Enabled
Enabled
Disabled; LOW
Disabled; LOW
Disabled; HIGH
Disabled; HIGH
After nCLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. In the
active mode, the state of the outputs are a function of the CLK0, nCLK0 and CLK1, nCLK1 inputs as described in Table 3B.
Enabled
Disabled
nCLK[0:1]
CLK[0:1]
nCLK_EN
nQ[0:4]
Q[0:4]
Figure 1. nCLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK0 or CLK1
nCLK0 or nCLK1
Q[0:4]
LOW
nQ[0:4]
HIGH
Input to Output Mode
Differential-to-Differential
Differential-to-Differential
Polarity
0
1
1
0
Non-Inverting
Non-Inverting
HIGH
LOW
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Inputs, VI
4.6V
-0.5V to VCC + 0.5V
Outputs, IO
Continuos Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
20 Lead SOIC
20 Lead TSSOP
46.2°C/W (0 lfpm)
73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
VCC Positive Supply Voltage
IEE Power Supply Current
Test Conditions
Minimum
Typical
Maximum
Units
V
2.375
3.3
3.8
80
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VCC + 0.3
0.8
Units
V
VIH
VIL
IIH
Input High Voltage
2
Input Low Voltage
Input High Current
Input Low Current
-0.3
V
nCLK_EN, CLK_SEL
nCLK_EN, CLK_SEL
VCC = VIN = 3.8V
150
µA
µA
IIL
VCC = 3.8V, VIN = 0V
-5
Table 4C. Differential DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VCC = VIN = 3.8V
VCC = VIN = 3.8V
VCC = 3.8V, VIN = 0V
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
150
5
Input
IIH
High Current
-5
Input
IIL
Low Current
VCC = 3.8V, VIN = 0V
-150
0.15
0.5
VPP
Peak-to-Peak Voltage; NOTE 1
1.3
VCMR
Common Mode Range; NOTE 1, 2
VCC – 0.85
V
NOTE 1: VIL should not be less than -0.3V
NOTE 2: Common mode voltage is defined as VIH.
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Table 4D. LVPECL DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC – 1.4
VCC – 2.0
0.6
Typical
Maximum
VCC – 0.9
VCC – 1.7
1.0
Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
V
V
V
VOL
VSWING
NOTE 1: Outputs termination with 50Ω to VCC – 2V.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
700
MHz
Propagation Delay, Low to High;
NOTE 1
tpLH
ƒ ≤ 700MHz
1.0
1.4
1.8
30
ns
ps
ps
tsk(o)
tjit(θ)
Output Skew; NOTE 2, 3
RMS Phase Jitter (Random);
NOTE 4
155.52MHz,
Integration Range: 12kHz - 20MHz
0.05
tsk(pp)
tS
Part-to-Part Skew; NOTE 3, 5
Setup Time
350
ps
ps
ps
ps
%
nCLK_EN to CLK
nCLK_EN to CLK
20% to 80%
50
50
tH
Hold Time
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle Skew
200
45
700
55
ƒ ≤ 700MHz
NOTE: All parameters measured at ƒmax unless otherwise noted.
NOTE: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Refer to Phase Noise Plot.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Typical Phase Noise at 155.52MHz
0
155.52MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.05ps (typical)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
Raw Phase Noise Data
-160
-170
-180
-190
Offset Frequency (Hz)
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Parameter Measurement Information
2V
V
CC
SCOPE
nCLK[0:1]
Qx
VCC
VPP
VCMR
Cross Points
CLK[0:1]
LVPECL
nQx
V
EE
VEE
-1.8V to -0.375V
LVPECL Output Load AC Test Circuit
Differential Input Level
Part 1
nQx
nQx
nQx
nQx
Part 2
nQy
nQy
nQy
nQy
tsk(pp)
tsk(o)
Output Skew
Part-to-Part Skew
Phase Noise Plot
nCLK[0:1]
CLK[0:1]
nQ[0:4]
Q[0:4]
tPD
Offset Frequency
f1
f2
Propagation Delay
RMS Phase Jitter
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Parameter Measurement Information
nCLK[0:1]
CLK[0:1]
nQ[0:4]
80%
tF
80%
tR
VSWING
20%
20%
nCLK_EN
Q[0:4]
tSET-UP
tHOLD
Setup & Hold Time
Output Rise/Fall Time
nQ[0:4]
Q[0:4]
tPW
tPERIOD
tPW
odc =
x 100%
tPERIOD
Output Duty Cycle
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Application Information
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VCC/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VCC are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than Vcc + 0.3V. Though some of
the recommended components might not be used, the pads should
be placed in the layout. They can be utilized for debugging purposes.
The datasheet specifications are characterized and guaranteed by
using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
Recommendations for Unused Input and Output Pins
Outputs:
Inputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLK to ground.
Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both VSWING and VOH must meet the VPP and
VCMR input requirements. Figures 3A to 3F show interface examples
for the CLK/nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example in Figure 3A, the input
termination applies for IDT LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
Input
LVPECL
nCLK
R1
50Ω
R2
50Ω
Differential
Input
LVHSTL
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
R2
50Ω
Figure 3B. CLK/nCLK Input
Figure 3A. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Driven by an IDT LVHSTL Driver
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125Ω
R4
125Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
nCLK
nCLK
Zo = 50Ω
Differential
Input
Receiver
LVPECL
LVDS
R1
R2
84Ω
84Ω
Figure 3C. CLK/nCLK Input
Figure 3D. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
Zo = 50Ω
Zo = 60Ω
Zo = 60Ω
*R3
*R4
33Ω
33Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
Differential
Input
Differential
Input
SSTL
HCSL
R1
50Ω
R2
50Ω
R1
120Ω
R2
120Ω
*Optional – R3 and R4 can be 0Ω
Figure 3E. CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
R3
R4
3.3V
125Ω
125Ω
3.3V
3.3V
Z
o = 50Ω
3.3V
Z
o = 50Ω
+
_
+
_
Input
LVPECL
Zo = 50Ω
LVPECL
Input
Zo = 50Ω
R1
R2
R1
84Ω
R2
84Ω
50Ω
50Ω
VCC - 2V
1
RTT =
* Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Termination for 2.5V LVPECL Outputs
Figure 5A and Figure 5B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to
ground level. The R3 in Figure 5B can be eliminated and the
termination is shown in Figure 5C.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
50Ω
R1
R3
250Ω
250Ω
+
50Ω
50Ω
+
–
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
2.5V LVPECL Driver
R2
R4
62.5Ω
62.5Ω
R3
18Ω
Figure 5A. 2.5V LVPECL Driver Termination Example
Figure 5B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
Figure 5C. 2.5V LVPECL Driver Termination Example
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS85314I-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85314I-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.8V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.8V * 80mA = 304mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 30mW = 150mW
Total Power_MAX (3.6V, with all outputs switching) = 304mW + 150mW = 454mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and it directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air
flow or 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6B below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.454W * 66.6°C/W = 115°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6A. Thermal Resistance θJA for 20 Lead SOIC, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
65.7°C/W
39.7°C/W
57.5°C/W
36.8°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Table 6B. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50Ω
VCC - 2V
Figure 6. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of
VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.9V
(VCC_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.7V
(VCC_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Reliability Information
Table 7A. θJA vs. Air Flow Table for a 20 Lead SOIC, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
83.2°C/W
46.2°C/W
65.7°C/W
39.7°C/W
57.5°C/W
36.8°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Table 7B. θJA vs. Air Flow Table for a 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB design use multi-layered boards. The data in the second row pertains to most designs.
Transistor Count
The transistor count for ICS85314I-11 is: 674
ICS85314AGI-11 REVISION E MAY 4, 2010
15
©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Package Outlines and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Package Outline - M Suffix for 20 Lead SOIC
Table 8A. Package Dimensions
All Dimensions in Millimeters
Table 8B. Package Dimensions for 20 Lead SOIC
300 Millimeters
All Dimensions in Millimeters
Symbol
Minimum
Maximum
Symbol
Minimum
Maximum
N
A
20
N
A
A1
A2
B
C
D
E
20
1.20
0.15
1.05
0.30
0.20
6.60
2.65
A1
A2
b
0.05
0.80
0.19
0.09
6.40
0.10
2.05
0.33
0.18
12.60
7.40
2.55
0.51
0.32
13.00
7.60
c
D
E
6.40 Basic
E1
e
4.30
4.50
e
1.27 Basic
0.65 Basic
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
7°
L
0.45
0°
0.75
8°
α
L
aaa
0.10
α
Reference Document: JEDEC Publication 95, MO-153
Reference Document: JEDEC Publication 95, MS-013, MS-119
ICS85314AGI-11 REVISION E MAY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Ordering Information
Table 9. Ordering Information
Part/Order Number
85314AGI-11
Marking
ICS85314AI11
ICS85314AI11
ICS5314AI11L
ICS5314AI11L
Package
20 lead TSSOP
20 lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Tube
1000 Tape & Reel
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
85314AGI-11T
85314AGI-11LF
85314AGI-11LFT
85314AMI-11
85314AMI-11T
85314AMI-11LF
85314AMI-11LFT
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
20 Lead SOIC
20 Lead SOIC
“Lead-Free” 20 Lead SOIC
“Lead-Free” 20 Lead SOIC
ICS85314AI-11
ICS85314AI-11
ICS85314AMI-11LF
ICS85314AMI-11LF
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS85314AGI-11 REVISION E MAY 4, 2010
17
©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T1
2
Pin Description Table - Pin 14 & 17, nCLKx, deleted partial description and added Pullup in
the “Type” column.
T2
2
4
7
8
Pin Characteristics Table - CIN changed 4pF max. to 4pF typical.
AMR - corrected Output rating.
Added Wiring the Differential Input to Accept Single Ended Levels section.
Added Differential Clock Input Interface section.
A
6/11/03
1
5
6
8
9
Added Phase Noise bullet in Features section.
AC Characteristics Table - added RMS Phase Jitter.
Added Phase Jitter Plot.
Updated Termination for 3.3V LVPECL Output diagrams.
Added Termination for 2.5V LVPECL Output section.
T5
B
8/11/04
1
2
16
Features section - added Lead-Free bullet.
Pin Description Table - corrected CLK_SEL description.
Ordering Information Table - added ""Lead-Free"" part number for TSSOP package.
B
C
D
T1
T9
3/22/05
5/24/05
9/23/05
1
5
Features section - changed Part-to-Part Skew from 250ps max. to 350ps max.
AC Characteristics table - changed Part-to-Part Skew from 250ps max. to 350ps max.
T5
T4D
5
8
LVPECL DC Characteristics Table - changed VOH max from VCC - 1.0V to VCC - 0.9V.
Application Information Section - added Recommendations for Unused Input and Output
Pins.
T4C
T5
4
5
Differential DC Characteristics Table - corrected typo in IIH row, nCLKx to 5uA from 150uA.
Added thermal note to AC Characteristics Table.
E
E
9
17
Updated “Wiring the Differential Input to Accept Single-ended Levels” section.
Ordering Information Table - added LF marking for SOIC package.
Converted datasheet format.
4/16/10
5/4/10
T9
T9
17
Ordering Information Table - corrected package in the Package Column.
ICS85314AGI-11 REVISION E MAY 4, 2010
18
©2010 Integrated Device Technology, Inc.
ICS85314I-11 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-2.5V, 3.3V LVPECL FANOUT BUFFER
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
San Jose, California 95138
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2009. All rights reserved.
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