853S9252BKILF/W [IDT]
2.5V, 3.3V ECL/LVPECL Clock/Data Fanout Buffer;
| 型号： | 853S9252BKILF/W |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 2.5V, 3.3V ECL/LVPECL Clock/Data Fanout Buffer |
| 文件： | 总21页 (文件大小：402K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V, 3.3V ECL/LVPECL Clock/Data
Fanout Buffer
ICS853S9252I
DATASHEET
General Description
Features
• 1:2 differential clock/data fanout buffer
• Clock frequency: 3GHz (maximum)
• Two differential 2.5V/3.3V ECL/LVPECL clock output
• Differential input accepts ECL/LVPECL, LVDS and CML levels
• Additive phase jitter, RMS @ 122.88MHz: 45fs (typical)
• Propagation delay: 175ps (maximum), VCC = 3.3V
• Output rise/fall time: 135ps (maximum), VCC = 3.3V
• Internal input signal termination
The ICS853S9252I is a 2.5V/3.3V ECL/LVPECL fanout buffer
designed for high-speed, low phase-noise wireless infrastructure
applications. The device fanouts a differential input signal to two
ECL/LVPECL outputs. Optimized for low additive phase-noise,
sub-100ps output rise and fall times, low output skew and
high-frequencies, the ICS853S9252I is an effective solution for
high-performance clock and data distribution applications, for
instance driving the reference clock inputs of ADC/DAC circuits.
Internal input termination, a bias voltage output (VREF) for
AC-coupling and small packaging (3.0mm x 3.0mm 16-lead VFQFN)
supports space-efficient board designs.
• Supply voltage: 2.5V-5% to 3.3V+10%
• Lead-free (RoHS 6) packaging
• -40°C to 85°C ambient operating temperature
The ICS853S9252I operates from a full 2.5V or 3.3V power supply
and supports the industrial temperature range of -40°C to 85°C. The
extended temperature range also supports wireless infrastructure,
tele-communication and networking end equipment requirements.
Block Diagram
Pin Assignment
Q0
nQ0
IN
nIN
Q1
16 15 14 13
12
11
10
9
Q0
IN
nIN
nc
1
2
3
4
nQ1
50
50
nQ0
Q1
VTT
nQ1
nc
5
6
7
8
VREF
Generator
VREF
ICS853S9252I
16 lead VFQFN
3.0mm x 3.0mm x 0.925mm
package body
K Package
Top View
ICS853S9252BKI JUNE 14, 2017
1
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Type
Description
Non-inverting and inverting clock input. ECL/LVPECL, LVDS and CML interface levels. 50
to VTT or 100 input termination.
1, 2
IN, nIN
Input
3, 4, 5, 6
7, 14
8, 13
9, 10
11, 12
15
nc
VEE
Unused
Power
Power
Output
Output
Output
No connect.
Negative supply pins.
VCC
Power supply pins.
nQ1, Q1
nQ0, Q0
VREF
Differential clock output. ECL/LVPECL interface levels.
Differential clock output. ECL/LVPECL interface levels.
Bias voltage reference for AC-coupling of the differential inputs.
Center tap for input termination. Leave floating for LVDS inputs, connect 50 to GND for
3.3V LVPECL inputs and to the VREF output for AC-coupled applications.
16
VTT
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VCC
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, VI (ECL mode)
4.6V (LVPECL mode, VEE = 0V)
-4.6V (ECL mode, VCC = 0V)
-0.5V to VCC + 0.5V
0.5V to VEE – 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Input Current, IN, nIN
±25mA
VT Current, IVT
±50mA
Input Sink/Source, IREF
±2mA
Operating Temperature Range, TA
Package Thermal Impedance, JA, (Junction-to-Ambient)
Storage Temperature, TSTG
-40°C to +85°C
74.7C/W (0 mps)
-65C to 150C
ICS853S9252BKI JUNE 14, 2017
2
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
DC Electrical Characteristics
Table 2A. Power Supply DC Characteristics, V = 2.5V-5% to V = 3.3V+10%, V = 0V, T = -40°C to 85°C
CC
CC
EE
A
Symbol
VCC
Parameter
Test Conditions
Minimum
2.375
Typical
Maximum
Units
V
Power Supply Voltage
Power Supply Current
Output Supply Current
3.3
79
26
3.63
99
ICC
Includes load current
mA
mA
IEE
33
Table 2B. DC Characteristics, V = 2.5V-5% to V = 3.3V+10%, V = 0V, T = -40°C to 85°C
CC
CC
EE
A
Symbol
RIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
IN to VTT, nIN to VTT
50
V
V
V
VIH
1.2
0
VCC
VIH - 0.1
1.4
VIL
VIN
0.1
Differential Input
Voltage Swing
VDIFF_IN
0.2
2.8
V
VREF
CIN
Bias Voltage Reference
Input Capacitance
VCC – 1.3
2
V
pF
Table 2C. LVPECL DC Characteristics, V = 3.3V ± 10%, V = 0V, T = -40°C to 85°C
CC
EE
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage;
NOTE 1
VOH
V
CC – 1.4
CC – 2.0
0.6
VCC – 0.76
V
Output Low Voltage;
NOTE 1
VOL
V
VCC – 1.6
1.1
V
V
Peak-to-Peak Output
Voltage Swing
VSWING
NOTE 1: The outputs are terminated with 50 to VCC – 2V.
Table 2D. LVPECL DC Characteristics, V = 2.5V ± 5%, V = 0V, T = -40°C to 85°C
CC
EE
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage;
NOTE 1
VOH
V
CC – 1.4
CC – 2.0
0.4
VCC – 0.56
V
Output Low Voltage;
NOTE 1
VOL
V
VCC – 1.5
1.1
V
V
Peak-to-Peak Output
Voltage Swing
VSWING
NOTE 1: The outputs are terminated with 50 to VCC – 2V.
ICS853S9252BKI JUNE 14, 2017
3
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
AC Characteristics
Table 3. AC Characteristics, V = 2.5V-5% to V = 3.3V+10%, V = 0V, T = -40°C to 85°C
CC
CC
EE
A
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
GHz
ps
fREF
Input Reference Frequency
Propagation Delay, NOTE 1
Output Pulse Skew
3
VCC = 3.3V
VCC = 2.5V
75
85
135
130
175
200
15
tPD
ps
tsk(p)
tsk(o)
ps
VCC = 3.3V
VCC = 2.5V
10
ps
Output Skew, NOTE 2, 3
17
ps
tsk(pp)
Part-to-Part Skew, NOTE 3, 4
Output Duty Cycle
50
ps
odc
47
53
%
Buffer Additive Phase Jitter,
RMS; Refer to Additive Phase
Jitter Section
122.88MHz,
Integration Range:10Hz – 10MHz
tjit
45
fs
122.88MHz, Offset: 10Hz
122.88MHz, Offset: 100Hz
122.88MHz, Offset: 1kHz
122.88MHz, Offset: 10kHz
122.88MHz, Offset: 100kHz
122.88MHz, Offset: >1MHz
-98
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-128
-150
-158
-161
-161
Phase Noise Frequency
Offset
Power Supply Rejection;
NOTE 5
VCC = 3.3V
3
ps/V
VCC = 3.3V, 20% to 80%
VCC = 2.5V, 20% to 80%
90
135
170
ps
ps
tR / tF
Output Rise/Fall Time
110
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: All parameters characterized at fREF 2GHz, unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoints.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 5: Change in tPD per change in VCC
.
ICS853S9252BKI JUNE 14, 2017
4
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 122.88MHz
10Hz to 10MHz = 45fs (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator used is, low noise Wenzel Oscillator at
122.88MHz.
ICS853S9252BKI JUNE 14, 2017
5
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Parameter Measurement Information
2V
VCC
nIN
SCOPE
VCC
Qx
VIN
VIH
Cross Points
IN
nQx
VIL
VEE
VEE
-1.63V to -0.375V
Output Load AC Test Circuit
Differential Input Level
Part 1
nQx
Qx
nQx
Qx
nQy
Qy
Part 2
nQy
Qy
tsk(pp)
Part-to-Part Skew
Output Skew
nIN
IN
VDIFF_IN
VIN
nQ[0:1]
Q[0:1]
tPLH
tPHL
Differential Voltage Swing = 2 x Single-ended VIN
tsk(p)= |tPHL - tPLH
|
Pulse Skew
Single-ended & Differential Input Voltage Swing
ICS853S9252BKI JUNE 14, 2017
6
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Parameter Measurement Information, continued
nQ[0:1]
Q[0:1]
nQ[0:1]
Q[0:1]
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
nIN
IN
nQ[0:1]
Q[0:1]
tPD
Propagation Delay
Applications Information
Recommendations for Unused Output Pins
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
ICS853S9252BKI JUNE 14, 2017
7
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
3.3V Differential Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both differential signals must
meet the VIN and VIH input requirements. Figures 2A to 2C show
interface examples for the IN/nIN input with built-in 50 terminations
driven by the most common driver types. The input interfaces
suggested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termination
requirements.
Figure 2A. IN/nIN Input with Built-In 50
Figure 2B. IN/nIN Input with Built-In 50
Driven by an LVDS Driver
Driven by an LVPECL Driver
Figure 2C. IN/nIN Input with Built-In 50
Driven by a CML Driver
ICS853S9252BKI JUNE 14, 2017
8
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
2.5V LVPECL Input with Built-In 50 Termination Interface
The IN /nIN with built-in 50 terminations accept LVDS, LVPECL,
CML and other differential signals. Both differential signals must
meet the VIN and VIH input requirements. Figures 3A to 3C show
interface examples for the IN/nIN with built-in 50 termination input
driven by the most common driver types. The input interfaces
suggested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver termination
requirements.
Figure 3A. IN/nIN Input with Built-In 50
Figure 3B. IN/nIN Input with Built-In 50
Driven by an LVDS Driver
Driven by an LVPECL Driver
2.5V
2.5V
IN
VT
nIN
V_REF_AC
CML
Figure 3C. IN/nIN Input with Built-In 50
Driven by a CML Driver
ICS853S9252BKI JUNE 14, 2017
9
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
2.5V Differential Input with Built-In 50 Termination Unused Input Handling
To prevent oscillation and to reduce noise, it is recommended to have
pullup and pulldown connect to true and compliment of the unused
2.5V
input as shown in Figure 4A.
2.5V
R1
680
IN
VT
nIN
Receiver
With
Built-In
R2
50Ω
680
Figure 4A. Unused Input Handling
3.3V Differential Input with Built-In 50 Termination Unused Input Handling
To prevent oscillation and to reduce noise, it is recommended to have
pullup and pulldown connect to true and compliment of the unused
3.3V
input as shown in Figure 4B.
3.3V
R1
1k
IN
VT
nIN
Receiver
With
Built-In
R2
50Ω
1k
Figure 4B. Unused Input Handling
ICS853S9252BKI JUNE 14, 2017
10
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
3.3V
R3
R4
125
125
3.3V
3.3V
Zo = 50
+
_
Input
Z
o = 50
R1
84
R2
84
Figure 5A. 3.3V LVPECL Output Termination
Figure 5B. 3.3V LVPECL Output Termination
ICS853S9252BKI JUNE 14, 2017
11
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Termination for 2.5V LVPECL Outputs
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECLdriver. These terminations are equivalent to terminating 50
to VCC – 2V. For VCC = 2.5V, the VCC – 2V is very close to ground
level. The R3 in Figure 6B can be eliminated and the termination is
shown in Figure 6C.
2.5V
VCC = 2.5V
2.5V
2.5V
VCC = 2.5V
50Ω
R1
R3
250Ω
250Ω
+
50Ω
50Ω
+
–
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
2.5V LVPECL Driver
R2
R4
62.5Ω
62.5Ω
R3
18Ω
Figure 6A. 2.5V LVPECL Driver Termination Example
Figure 6B. 2.5V LVPECL Driver Termination Example
2.5V
VCC = 2.5V
50Ω
+
50Ω
–
2.5V LVPECL Driver
R1
R2
50Ω
50Ω
Figure 6C. 2.5V LVPECL Driver Termination Example
ICS853S9252BKI JUNE 14, 2017
12
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 7. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, please refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadframe Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
Figure 7. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)
ICS853S9252BKI JUNE 14, 2017
13
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS853S9252I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853S9252I is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for VCC = 3.3V + 10% = 3.63V, which gives worst case results.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 33mA = 119.8mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 31.6mW = 63.2mW
•
Power Dissipation for internal termination RT
Power (RT)MAX = (VIN_MAX)2 / RT_MIN = (1.4V)2 / 50 = 39.2mW
Total Power = Power (core)MAX + Power (output)MAX + Power (RT)MAX = 119.8mW + 63.2mW + 39.2mW = 222.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 74.7°C/W per Table 4 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.222W * 74.7°C/W = 101.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 4. Thermal Resistance for 16 Lead VFQFN, Forced Convection
JA
JA by Velocity
0
Meters per Second
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
ICS853S9252BKI JUNE 14, 2017
14
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
The LVPECL output driver circuit and termination are shown in Figure 8.
VCC
Q1
VOUT
RL
VCC - 2V
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VCC – 2V.
•
•
For logic high, VOUT = VOH_MAX = VCC_MAX – 0.76V
(VCC_MAX – VOH_MAX) = 0.76V
For logic low, VOUT = VOL_MAX = VCC_MAX – 1.6V
(VCC_MAX – VOL_MAX) = 1.6V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOH_MAX) = [(2V – (VCC_MAX – VOH_MAX))/RL] * (VCC_MAX – VOH_MAX) =
[(2V – 0.76V)/50] * 0.76V = 18.8mW
Pd_L = [(VOL_MAX – (VCC_MAX – 2V))/RL] * (VCC_MAX – VOL_MAX) = [(2V – (VCC_MAX – VOL_MAX))/RL] * (VCC_MAX – VOL_MAX) =
[(2V – 1.6V)/50] * 1.6V = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 31.6mW
ICS853S9252BKI JUNE 14, 2017
15
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Reliability Information
Table 5. vs. Air Flow Table for a 16 Lead VFQFN
JA
JA by Velocity
0
Meters per Second
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
74.7°C/W
65.3°C/W
58.5°C/W
Transistor Count
The transistor count forICS853S9252I is: 190
ICS853S9252BKI JUNE 14, 2017
16
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
16 Lead VFQFN Package Outline and Package Dimensions – Sheet 1
ICS853S9252BKI JUNE 14, 2017
17
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
16 Lead VFQFN Package Outline and Package Dimensions – Sheet 2
ICS853S9252BKI JUNE 14, 2017
18
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Ordering Information
Table 6. Ordering Information
Part/Order Number
853S9252BKILF
853S9252BKILFT
853S9252BKILF/W
Marking
252B
252B
Package
Shipping Packaging
Tube
Tape & Reel, Pin 1 Orientation: EIA-481-C
Tape & Reel, Pin 1 Orientation: EIA-481-D
Temperature
-40C to 85C
-40C to 85C
-40C to 85C
“Lead-Free” 16 Lead VFQFN
“Lead-Free” 16 Lead VFQFN
“Lead-Free” 16 Lead VFQFN
252B
Table 7. Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
T
Quadrant 1 (EIA-481-C)
/W
Quadrant 2 (EIA-481-D)
ICS853S9252BKI JUNE 14, 2017
19
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Revision History Sheet
Date
Description of Change
6/14/2017
Updated the packaging diagrams
Ordering Information Table - added additional row.
Added Orientation Packaging Table.
7/17/2013
ICS853S9252BKI JUNE 14, 2017
20
©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved.
相关型号：
©2020 ICPDF网 联系我们和版权申明