854054AGLF [IDT]
Multiplexer, 854054 Series, 1-Func, 4 Line Input, 1 Line Output, Complementary Output, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16;
| 型号： | 854054AGLF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Multiplexer, 854054 Series, 1-Func, 4 Line Input, 1 Line Output, Complementary Output, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS854054 is a 4:1 Differential-to-LVDS Clock • High speed 4:1 differential multiplexer
ICS
HiPerClockS™
Multiplexer which can operate up to 2.8GHz and
is a member of the HiPerClockS™family of High
Performance Clock Solutions from ICS. The
ICS854054 has 4 selectable differential clock
• One differential LVDS output
• Four selectable differential clock inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
inputs. The PCLK, nPCLK input pairs can accept LVPECL,
LVDS, CML or SSTL levels. The fully differential architec-
ture and low propagation delay make it ideal for use in clock
distribution circuits. The select pins have internal pulldown
resistors. The SEL1 pin is the most significant bit and the
binary number applied to the select pins will select the same
numbered data input (i.e., 00 selects PCLK0, nPCLK0).
• Maximum output frequency: 2.8GHz
• Translates any single ended input signal to
LVDS levels with resistor bias on nPCLKx input
• Part-to-part skew: 375ps (maximum)
• Propagation delay: 700ps (maximum)
• Supply voltage range: 3.135V to 3.465V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
PCLK0
nPCLK0
PCLK1
nPCLK1
VDD
SEL0
SEL1
GND
16
15
14
13
12
11
10
9
VDD
Q
nQ
GND
nPCLK3
PCLK3
nPCLK2
PCLK2
PCLK0
nPCLK0
(default)
00
01
10
PCLK1
nPCLK1
Q
nQ
PCLK2
nPCLK2
ICS854054
16-LeadTSSOP
PCLK3
nPCLK3
4.4mm x 5.0mm x 0.92mm package body
G Package
11
TopView
SEL0
SEL1
854054AG
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REV.A MARCH 29, 2006
1
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
1
PCLK0
Input
Input
Input
Input
Non-inverting differential clock input.
Inverting differential clock input.
VDD/2 default when left floating.
2
3
4
nPCLK0
PCLK1
Pullup/Pulldown
Pulldown
Non-inverting differential clock input.
Inverting differential clock input.
VDD/2 default when left floating.
nPCLK1
Pullup/Pulldown
5, 16
6, 7
8, 13
9
VDD
SEL0, SEL1
GND
Power
Input
Positive supply pins.
Pulldown
Clock select input pins. LVCMOS/LVTTL interface levels.
Power supply ground.
Power
Input
PCLK2
Pulldown
Pullup/Pulldown
Pulldown
Non-inverting differential clock input.
Inverting differential clock input.
VDD/2 default when left floating.
10
11
nPCLK2
PCLK3
Input
Input
Non-inverting differential clock input.
Inverting differential clock input.
VDD/2 default when left floating.
12
nPCLK3
nQ0, Q0
Input
Pullup/Pulldown
14, 15
Output
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
RPULLDOWN Pulldown Resistor
75
50
kΩ
kΩ
RVDD/2
Pullup/Pulldown Resistors
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
SEL1
SEL0
Q
nQ
0
0
1
1
0
1
0
1
PCLK0
PCLK1
PCLK2
PCLK3
nPCLK0
nPCLK1
nPCLK2
nPCLK3
854054AG
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REV.A MARCH 29, 2006
2
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
5.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
I
Outputs, IO
Continuous Current
10mA
15mA
Surge Current
PackageThermal Impedance, θ
89°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
3.135
3.3
3.465
90
V
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
Input High Current
Input Low Current
-0.3
VDD = VIN = 3.465V
150
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-10
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
Minimum
Typical Maximum Units
PCLK0:PCLK3
nPCLK0:nPCLK3
PCLK0:PCLK3
nPCLK0:nPCLK3
150
150
µA
µA
µA
µA
V
-10
-150
0.15
1.2
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
1.2
VDD
VCMR
Common Mode Input Voltage; NOTE 1, 2
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx or nPCLKx is VDD + 0.3V.
854054AG
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REV.A MARCH 29, 2006
3
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VOD
Differential Output Voltage
250
450
525
50
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.125
1.25
1.375
50
Δ VOS
VOS Magnitude Change
mV
TABLE 5. AC CHARACTERISTICS, VDD = 3.135V TO 3.465V, TA = -40°C TO 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum Typical Maximum Units
Output Frequency
Propagation Delay; NOTE 1
2.8
GHz
ps
tPD
325
700
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
155.52 MHz,
(12kHz - 20MHz)
tjit
0.195
ps
tsk(pp)
tsk(i)
Part-to-Part Skew; NOTE 2, 3
Input Skew
375
90
ps
ps
ps
tR / tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
50
250
155.52MHz,
Input Peak-to-Peak = 800mV
MUXISOLATION MUX Isolation
-50
dB
All parameters measured up to 1.5MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
854054AG
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REV.A MARCH 29, 2006
4
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
-40
Additive Phase Jitter, RMS
@ 155.52MHz (12kHz - 20MHz) = <0.195ps typical
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
854054AG
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REV.A MARCH 29, 2006
5
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
Qx
nPCLK0:3
PCLK0:3
3.3V 5ꢀ
Power Supply
Float GND
VPP
VCMR
Cross Points
LVDS
+
-
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLK0:3
nQx
PART 1
Qx
PCLK0:3
nQ0
nQy
PART 2
Qy
Q0
tPD
tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
nPCLK0
PCLK0
nPCLK1
PCLK1
80ꢀ
tF
80ꢀ
VOD
Clock
20ꢀ
20ꢀ
Outputs
nQ
tR
Q
tPD2
tPD1
tsk(i)
tsk(i) = |tPD1 - tPD2
|
INPUT SKEW
OUTPUT RISE/FALL TIME
VDD
out
out
VDD
➤
DC Input
➤
LVDS
out
LVDS
DC Input
100
V
OD/Δ VOD
VOS/Δ VOS
➤
➤
out
DIFFERENTIAL OUTPUT VOLTAGE
OFFSET VOLTAGE
854054AG
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REV.A MARCH 29, 2006
6
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD= 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resister can be tied
from PCLK to ground.
SELECT PINS:
All select pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resister can be used.
854054AG
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REV.A MARCH 29, 2006
7
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other gested here are examples only. If the driver is from another
differential signals. Both VSWING and VOH must meet the VPP vendor, use their termination recommendation. Please con-
and VCMR input requirements. Figures 2A to 2E show inter- sult with the vendor of the driver component to confirm the
face examples for the HiPerClockS PCLK/nPCLK input driven driver termination requirements.
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R3
120
R4
120
R1
50
R2
50
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
nPCLK
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
R2
120
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL IN DRIVER
BY A CML DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
84
R4
84
C1
C2
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R5
100 - 200
R6
100 - 200
R1
125
R2
125
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
854054AG
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REV.A MARCH 29, 2006
8
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω receiver input. For a multiple LVDS outputs buffer, if only par-
differential transmission line environment, LVDS drivers re- tial outputs are used, it is recommended to terminate the un-
used outputs.
quire a matched load termination of 100Ω across near the
3.3V
3.3V
LVDS_Driver
+
-
R1
100
100 Ohm Differiential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVERTERMINATION
854054AG
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REV.A MARCH 29, 2006
9
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS854054.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS854054 is the sum of the core power.
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
qJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8°C/W per
Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.312W * 81.8°C/W = 110.5°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 16-LEADTSSOP, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
118.2°C/W
500
106.8°C/W
Single-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
89.0°C/W
81.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
854054AG
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REV.A MARCH 29, 2006
10
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOWT ABLE FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS854054 is: 361
854054AG
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REV.A MARCH 29, 2006
11
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
854054AG
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REV.A MARCH 29, 2006
12
ICS854054
4:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
Integrated
Circuit
Systems, Inc.
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS854054AG
Marking
854054AG
854054AG
TBD
Package
Shipping Packaging Temperature
16 Lead TSSOP
16 Lead TSSOP
16 Lead TSSOP
16 Lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS854054AGT
ICS854054AGLF
ICS854054AGLFT
2500 tape & reel
tube
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
854054AG
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REV.A MARCH 29, 2006
13
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