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85411AMLFT

更新时间：2024-09-18 22:12:44

品牌：IDT

描述：Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

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85411AMLFT 概述

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer 时钟缓冲器、驱动器、锁相环时钟驱动器

85411AMLFT 规格参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Lifetime Buy	零件包装代码：	SOIC
包装说明：	SOIC-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	0.88
系列：	85411	输入调节：	DIFFERENTIAL
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e3
长度：	4.9 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
湿度敏感等级：	1	功能数量：	1
反相输出次数：		端子数量：	8
实输出次数：	2	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
Prop。Delay @ Nom-Sup：	2.5 ns	传播延迟（tpd）：	2.5 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.02 ns
座面最大高度：	1.75 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.63 V	最小供电电压 (Vsup)：	2.97 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3.9 mm	Base Number Matches：	1

85411AMLFT 数据手册

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Low Skew, 1-to-2 Differential-to-LVDS

Fanout Buffer

85411

Data Sheet

GENERAL DESCRIPTION

FEATURES

• Two differential LVDS outputs

The 85411 is a low skew, high performance 1-to-2 Differential-

to-LVDS Fanout Buffer and a member of the family of High

Performance Clock Solutions from IDT. The CLK, nCLK pair

can accept most standard differential input levels.The 85411 is

characterized to operate from a 3.3V power supply. Guaranteed

output and part-to-part skew characteristics make the 85411 ideal

for those clock distribution applications demanding well deﬁned

performance and repeatability.

• One differential CLK, nCLK clock input

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum output frequency: 650MHz

• Translates any single ended input signal to

LVDS levels with resistor bias on nCLK input

• Output skew: 20ps (maximum)

• Part-to-part skew: 250ps (maximum)

• Additive phase jitter, RMS: 0.05ps (typical)

• Propagation delay: 2.5 ns (maximum)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Available in lead free (RoHS 6) package

BLOCK DIAGRAM

PIN ASSIGNMENT

nQ0

VDD

Pullup

CLK

Pulldown

nCLK

CLK

nCLK

GND

nQ1

85411

8-Lead SOIC

3.90mm x 4.90mm x 1.37mm package body

M Package

Top View

Revision C January 20, 2016

85411 Data Sheet

TABLE 1. PIN DESCRIPTIONS

Number

Name

Q0, nQ0

Q1, nQ1

GND

Type

Description

1, 2

3, 4

Output

Power

Input

Differential output pair. LVDS interface levels.

Power supply ground.

nCLK

Pulldown Inverting differential clock input.

CLK

Input

Pullup Non-inverting differential clock input.

Positive supply pin.

Power

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum Units

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

kΩ

PULLUP

PULLDOWN

Revision C January 20, 2016

85411 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

4.6V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress speciﬁcations only. Functional

operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

Inputs, V

-0.5V to V + 0.5V

Outputs, I

Continuous Current

Surge Current

10mA

15mA

Package Thermal Impedance, θ

112.7°C/W (0 lfpm)

-65°C to 150°C

Storage Temperature, T

STG

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, V = 3.3V 10ꢀ, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

Positive Supply Voltage

Power Supply Current

2.97

3.3

3.63

TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, V = 3.3V 10ꢀ, TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

CLK

= V = 3.63V

µA

Input High Current

nCLK

CLK

= V = 3.63V

150

= 3.63, V = 0V

-150

-5

Input Low Current

nCLK

= 3.63V, V = 0V

Peak-to-Peak Input Voltage; NOTE 1

0.15

0.5

1.3

Common Mode Input Voltage; NOTE 1, 2

- 0.85

CMR

NOTE 1: V should not be less than -0.3V.

NOTE 2: Common mode voltage is deﬁned as V .

TABLE 3C. LVDS DC CHARACTERISTICS, V = 3.3V 10ꢀ, TA = 0°C TO 70°C

Symbol Parameter

Differential Output Voltage

Test Conditions

Minimum

Typical Maximum Units

247

325

454

∆ V

VOD Magnitude Change

Offset Voltage

1.325

-20

1.45

1.575

∆ V

VOS Magnitude Change

Power Off Leakage

µA

+20

-5

OFF

Differential Output Short Circuit Current

Output Short Circuit Current

-3.5

OSD

-5

Revision C January 20, 2016

85411 Data Sheet

TABLE 4. AC CHARACTERISTICS, V = 3.3V 10ꢀ TA = 0°C TO 70°C

Symbol Parameter

Test Conditions

Minimum

Typical Maximum Units

Output Frequency

650

2.5

MHz

MAX

Propagation Delay; NOTE 1

Output Skew; NOTE 2, 4

1.5

tsk(o)

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

250

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

tjit

(12kHz to 20MHz)

0.05

t / t

Output Rise/Fall Time

20ꢀ to 80ꢀ @ 50MHz

> 500MHz

150

350

ꢀ

odc

Output Duty Cycle

≤ 500MHz

NOTE: Electrical parameters are guaranteed over the speciﬁed ambient operating temperature range, which is established

when the device is mounted in a test socket with maintained transverse airﬂow greater than 500 lfpm. The device will meet

speciﬁcations after thermal equilibrium has been reached under these conditions.

All parameters measured at ƒ ≤ 650MHz unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Deﬁned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Deﬁned as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is deﬁned in accordance with JEDEC Standard 65.

Revision C January 20, 2016

85411 Data Sheet

ADDITIVE PHASE JITTER

(dBm) or a ratio of the power in the 1Hz band to the power in the

fundamental.When the required offset is speciﬁed, the phase noise

is called a dBc value, which simply means dBm at a speciﬁed offset

from the fundamental.By investigating jitter in the frequency domain,

we get a better understanding of its effects on the desired application

over the entire time record of the signal.It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

The spectral purity in a band at a speciﬁc offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the speciﬁed plot in many applications. Phase

noise is deﬁned as the ratio of the noise power present in a 1Hz

band at a speciﬁed offset from the fundamental frequency to the

power value of the fundamental.This ratio is expressed in decibels

-10

-20

-30

-40

-50

Input/Output Additive Phase Jit-

ter @ 200MHz (12kHz to 20MHz)

= 0.05ps typical

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

100

10k

100k

10M

100M

500M

OFFSET FROM CARRIER FREQUENCY (HZ)

As with most timing speciﬁcations, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

ﬂoor of the equipment is higher than the noise ﬂoor of the device.

This is illustrated above. The device meets the noise ﬂoor of what

is shown, but can actually be lower.The phase noise is dependent

on the input source and measurement equipment.

Revision C January 20, 2016

85411 Data Sheet

PARAMETER MEASUREMENT INFORMATION

3.3V OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

PART-TO-PART SKEW

OUTPUT SKEW

PROPAGATION DELAY

OUTPUT RISE/FALL TIME

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

DIFFERENTIAL OUTPUT VOLTAGE SETUP

Revision C January 20, 2016

85411 Data Sheet

PARAMETER MEASUREMENT INFORMATION, CONTINUED

OFFSET VOLTAGE SETUP

POWER OFF LEAKAGE SETUP

OUTPUT SHORT CIRCUIT CURRENT SETUP

DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP

Revision C January 20, 2016

85411 Data Sheet

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input clock

swing is only 2.5V and V = 3.3V, V_REF should be 1.25V and R2/

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V /2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

R1 = 0.609.

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

RECOMMENDATIONS FOR UNUSED OUTPUT PINS

OUTPUTS:

LVDS

All unused LVDS output pairs can be either left ﬂoating or

terminated with 100Ω across. If they are left ﬂoating, there

should be no trace attached.

Revision C January 20, 2016

85411 Data Sheet

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both signals must meet the VPP and

Please consult with the vendor of the driver component to conﬁrm

the driver termination requirements. For example in Figure 2A, the

input termination applies for IDT HiPerClockS LVHSTL drivers. If

you are using an LVHSTL driver from another vendor, use their

termination recommendation.

VCMR input requirements. Figures 2A to 2E show interface examples

for the HiPerClockS CLK/nCLK input driven by the most common

driver types.The input interfaces suggested here are examples only.

3.3V

1.8V

Zo = 50 Ohm

CLK

Zo = 50 Ohm

CLK

Zo = 50 Ohm

nCLK

Zo = 50 Ohm

HiPerClockS

Input

LVPECL

nCLK

HiPerClockS

Input

LVHSTL

ICS

HiPerClockS

LVHSTL Driver

FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

IDT HIPERCLOCKS LVHSTL DRIVER

FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

3.3V

Zo = 50 Ohm

125

Zo = 50 Ohm

LVDS_Driver

CLK

100

nCLK

Receiver

HiPerClockS

Input

LVPECL

Zo = 50 Ohm

FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

125

LVPECL

Zo = 50 Ohm

CLK

nCLK

HiPerClockS

Input

100 - 200

R5,R6 locate near the driver pin.

FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER WITH AC COUPLE

Revision C January 20, 2016

85411 Data Sheet

LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 3. In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate

the unused outputs.

FIGURE 3. TYPICAL LVDS DRIVER TERMINATION

Revision C January 20, 2016

85411 Data Sheet

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the 85411.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 85411 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V = 3.3V + 10ꢀ = 3.63V, which gives worst case results.

•

Power (core) = V

* I

= 3.63V * 50mA = 181.5mW

DD_MAX

MAX

DD_MAX

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockS^TMdevices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + T

Tj = Junction Temperature

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a

moderate air ﬂow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.182W * 103.3°C/W = 88.8°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air ﬂow, and the

type of board (multi-layer).

TABLE 5. THERMAL RESISTANCE θ_JAFOR 8-LEAD SOIC, FORCED CONVECTION

θ_JAby Velocity (Linear Feet per Minute)

153.3°C/W

200

128.5°C/W

500

115.5°C/W

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

112.7°C/W

103.3°C/W

97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

Revision C January 20, 2016

85411 Data Sheet

RELIABILITY INFORMATION

TABLE 6. θ VS. AIR FLOW TABLE FOR 8 LEAD SOIC

θ_JAby Velocity (Linear Feet per Minute)

153.3°C/W

200

128.5°C/W

500

115.5°C/W

Single-Layer PCB, JEDEC Standard Test Boards

Multi-Layer PCB, JEDEC Standard Test Boards

112.7°C/W

103.3°C/W

97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

TRANSISTOR COUNT

The transistor count for 85411 is: 636

PACKAGE OUTLINE & DIMENSIONS

PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC

TABLE 7. PACKAGE DIMENSIONS

SYMBOL

MINIMUN

Millimeters

MAXIMUM

1.35

0.10

0.33

0.19

4.80

3.80

1.75

0.25

0.51

0.25

5.00

4.00

1.27 BASIC

5.80

0.25

0.40

0°

6.20

0.50

1.27

8°

Reference Document: JEDEC Publication 95, MS-012

Revision C January 20, 2016

85411 Data Sheet

TABLE 8. ORDERING INFORMATION

Part/Order Number

85411AMLF

Marking

85411ALF

Package

Shipping Packaging

Tray

Temperature

8 lead “Lead Free” SOIC

0°C to +70°C

85411AMLFT

Tape and Reel

Revision C January 20, 2016

85411 Data Sheet

REVISION HISTORY SHEET

Description of Change

Rev

Table

Page

Date

6/9/04

6/16/04

Features - added Additive Phase Jitter bullet.

AC Characteristics table - added tjit row.

Added Additive Phase Jitter Application Note

Ordering Information Table - added Lead Free Part Number.

Changed V from 5ꢀ to 10ꢀ throughout datasheet.

LVDS DC Characteristics Table - changed V range from

T3C

200mV min./360mV max. to 247mV min./454mV max.

Changed ∆V from 40mV max. to 50mV max.

9/19/06

Changed V from 1.125mV min./1.375mV max. to 1.325mV min./1.575mV max.

Changed ∆V from 25mV max. to 50mV max.

Added Recommendations for Unused Output Pins.

Added Power Considerations.

Ordering Information Table - corrected lead-free marking.

LVDS DC Characteristics Table - deleted V & V rows.

1/17/07

1/20/09

T3C

Removed ICS from part numbers where needed.

General Description - Deleted the ICS chip and removed HiPerClockS.

Features - removed reference to leaded part numbers.

Ordering Information - removed quantity for tape and reel. Deleted LF note below

the table.

1/20/16

Updated header and footer.

Revision C January 20, 2016

85411 Data Sheet

Tech Support

www.idt.com/go/support

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or speciﬁcations described herein at any time, without notice, at IDT's sole discretion. Performance speciﬁcations and

operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided

without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe-

ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect-

ed to signiﬁcantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or

their respective third party owners.

For datasheet type deﬁnitions and a glossary of common terms, visit www.idt.com/go/glossary.

85411AMLFT 替代型号

型号	制造商	描述	替代类型	文档
85411AMILF	IDT	Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer	类似代替
85411AMILFT	IDT	Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer	类似代替

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