85454AK [IDT]
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, MO-220, VFQFN-16;
| 型号： | 85454AK |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, MO-220, VFQFN-16 驱动 逻辑集成电路 |
| 文件： | 总15页 (文件大小：629K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DUAL 2:1 AND 1:2 DIFFERENTIAL-
TO-LVDS MULTIPLEXER
ICS85454
GENERAL DESCRIPTION
FEATURES
The ICS85454 is a dual 2:1 and 1:2 Multiplexer
• Three LVDS outputs
TM
and a member of the HiPerClockS family of high
performance clock solutions from IDT. The 2:1
Multiplexer allows one of 2 inputs to be selected
onto one output pin and the 1:2 MUX switches one
input to one of two outputs. This device is useful
ICS
HiPerClockS™
• Three differential clock inputs
• CLKx pair can accept the following differential input levels:
LVPECL, LVDS, CML
• Maximum output frequency: 2.5GHz
• Additive phase jitter, RMS: 0.11ps (typical)
• Part-to-part skew: 200ps (maximum)
for multiplexing multi-rate Ethernet PHYs which have 100 M bit
and 1000 bit transmit/receive pairs onto an optical SFP
module which has a single trasmit/receive pair. See Application
Section for further information.
• Propagation delay: 425ps (maximum), QA/nQA
375ps (maximum), QBx/nQBx
The ICS85454 is optimized for applications requiring very
high performance and has a maximum operating frequency
• Full 2.5V operating supply
of 2.5GHz. The device is packaged in
3mm x 3mm VFQFN package, making it ideal for use on
space-constrained boards.
a small,
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pulldown
CLK_SELA
Pulldown
CLKA0
nCLKA0
16 15 14 13
0
Pullup/Pulldown
QB0
1
2
12 CLKA0
11 nCLKA0
10 CLKA1
QA
nQA
nQB0
Pulldown
CLKA1
QB1
3
4
1
Pullup/Pulldown
nCLKA1
nQB1
9
nCLKA1
5
6
7
8
Pulldown
CLKB
QB0
nQB0
Pullup/Pulldown
nCLKB
ICS85454
QB1
nQB1
16-Lead VFQFN
Pulldown
3mm x 3mm x 0.95 package body
K Package
CLK_SELB
Top View
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
1
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Type
Output
Description
QB0, nQB0
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
3, 4
QB1, nQB1 Output
5
CLKB
Input
Input
Pulldown Non-inverting LVPECL differential clock input.
Pullup/
6
nCLKB
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Pulldown
Clock select pin for QBx outputs. When HIGH, selects QB1, nQB1
Pulldown outputs. When LOW, selects QB0, nQB0 outputs.
LVCMOS/LVTTL interface levels.
7
CLK_SELB
Input
8
GND
Power
Input
Input
Input
Power supply ground.
Pullup/
9
nCLKA1
CLKA1
nCLKA0
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Pulldown
10
11
Pulldown Non-inverting LVPECL differential clock input.
Pullup/
Inverting differential LVPECL clock input. VDD/2 default when left floating.
Pulldown
12
13
CLKA0
VDD
Input
Pulldown Non-inverting LVPECL differential clock input.
Positive supply pin.
Power
Clock select pin for CLKA inputs. When HIGH, selects CLKA1/nCLKA1
Pulldown inputs. When LOW, selects CLKA0/nCLKA0 inputs. LVCMOS/LVTTL
interface levels.
14
CLK_SELA
nQA, QA
Input
15, 16
Output
Differential output pair. LVDS interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
RPULLDOWN Input Pulldown Resistors
37.5
37.5
kΩ
kΩ
RVDD/2
Pullup/Pulldown Resistors
TABLE 3A. CONTROL INPUT FUNCTION TABLE, BANK A
Bank A
Control Inputs
Outputs
CLK_SELA
QA, nQA
0
1
Selects CLKA0, nCLKA0
Selects CLKA1, nCLKA1
TABLE 3B. CONTROL INPUT FUNCTION TABLE, BANK B
Bank B
Control Inputs
Outputs
CLK_SELB
QB0, nQB0
QB1, nQB1
Logic Low
0
1
Follows CLKB input
Logic Low
Follows CLKB input
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
2
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to
the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those listed
in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect product reliability.
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG -65°C to 150°C
Package Thermal Impedance, θJA 51.5°C/W (0 lfpm)
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
2.375
2.5
2.625
94
V
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
1.7
VDD + 0.3
0.7
V
V
Input Low Voltage
Input High Current
-0.3
CLK_SELA,
CLK_SELB
CLK_SELA,
CLK_SELB
IIH
IIL
VDD = VIN = 2.625V
150
µA
µA
Input Low Current
VDD = 2.625V, VIN = 0
-10
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 2.5V 5ꢀ, TA = -40°C TO 85°C
-40°C
Typ
25°C
Typ
85°C
Typ
Symbol Parameter
Units
Min
Max
Min
Max
Min
Max
Input
IIH
CLKAx, CLKB
nCLKx, nCLKB
CLKAx, CLKB
nCLKx, nCLKB
150
150
150
µA
High Current
Input
Low Current
IIL
-150
0.15
1.2
-150
0.15
1.2
-150
0.15
1.2
µA
V
VPP
Peak-to-Peak Input Voltage
1.2
VDD
1.2
VDD
1.2
VDD
Commond Mode Input Voltage;
NOTE 1, 2
VCMR
V
NOTE 1: Common mode input voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLKAx, nCLKAx and CLKB, nCLKB is VDD + 0.3V.
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
3
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V 5ꢀ, TA = -40°C TO 85°C
-40°C
Typ
25°C
85°C
Typ
350
Symbol Parameter
Units
Min
Max
450
30
Min
Typ
Max
450
30
Min
Max
450
30
VOD
Differential Output Voltage
250
350
250
350
250
mV
mV
V
∆ VOD
VOS
VOD Magnitude Change
Offset Voltage
0.93
1.18
1.43
10
0.97
1.22
1.47
10
1.02
1.27
1.52
10
∆ VOS
VOS Magnitude Change
mV
NOTE 1: Refer to Parameter Measurement Information, "2.5V Output Load Test Circuit" diagram.
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol
Parameter
Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
2.5
425
375
GHz
ps
QA, nQA
250
200
Propagation Delay;
NOTE 1
tPD
QBx, nQBx
ps
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section; NOTE 4
QA, nQA
0.11
0.11
ps
ps
tjit
QBx, nQBx
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
200
ps
dB
ps
MUX_ISOLATION MUX Isolation
55
tR/tF
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
47
200
53
QA, nQA
ꢀ
ꢀ
odc
Output Duty Cycle
QBx, nQBx
48
52
All parameters are measured ≤ 1.2GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Measured using clock input at 622MHz.
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
4
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
VDD
VDD
SCOPE
Qx
nCLKA0, nCLKA1
nCLKB
2.5V 5ꢀ
POWER SUPPLY
LVDS
+
Float GND
-
VPP
VCMR
Cross Points
CLKA0, CLKA1
CLKB
nQx
GND
OUTPUT LOAD 2.5V AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nCLKA0,
nCLKA1
nCLKB
nQx
PART 1
Qx
CLKA0,
CLKA1
CLKB
nQA,
nQB0,
nQB1
nQy
PART 2
Qy
QA,
QB0,
QB1
tPD
tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
nQA,
nQB0:nQB1
80ꢀ
tF
80ꢀ
QA,
QB0:QB1
VSWING
20ꢀ
tPW
Clock
20ꢀ
tPERIOD
Outputs
tR
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
5
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias DcDircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUT:
LVDS
For applications not requiring the use of a differential input, both
the CLK and nCLK pins can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from CLK
to ground.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
6
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
2.5V LVDS DRIVER TERMINATION
transmission line environment.For buffer with multiple LVDS driver,
it is recommended to terminate the unused outputs.
Figure 2 shows a typical termination for LVDS driver in
characteristic impedance of 100Ω differential (50Ω single)
2.5V
2.5V
LVDS_Driver
+
R1
100
-
100Ω DifferentialTransmission Line
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to
the P.C. board. The expose metal pad is ground pad connected
to ground plane through thermal via. The exposed pad on the
device to the exposed metal pad on the PCB is contacted through
solder as shown in Figure 3. For further information, please refer
to the Application Note on Surface Mount Assembly of Amkor’s
Thermally /Electrically Enhance Leadframe Base Package, Amkor
Technology.
EXPOSED PAD
SOLDER
SOLDER MASK
SIGNAL
TRACE
SIGNAL
TRACE
GROUND PLANE
Expose Metal Pad
(GROUND PAD)
THERMAL VIA
FIGURE 3. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
7
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
ATYPICAL APPLICATION FOR THE ICS85454
Used to connect a multi-rate PHY with the Tx/Rx pins of an
SFP Module.
Problem Addressed: How to map the 2 Tx/Rx pairs of the multi-
rate PHY to the single Tx/Rx pair on the SFP Module.
MULTI-RATE PHY
SFP MODULE
Tx
Rx
➣
➣
100BaseFX
1000BaseX
➣
➣
Rx
Tx
➣
?
➣
Tx
Rx
MODE 1, 100BASEX CONNECTED TO SFP
All lines are differential pairs, but drawn as single-ended to sim-
plify the drawing.
Bold red lines
signal path.
are active connections highlighting the
CLK_SELA = 0
M
ULTI-RATE PHY
SFP MODULE
CLKA0
CLKA1
Tx
Rx
0
QA
Rx
1
100BaseFX
CLKB
Tx
QB0
QB1
CLK_SELB = 0
Tx
Rx
ICS85454
1000BaseX
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
8
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
MODE 2, 100BASEX CONNECTED TO SFP
All lines are differential pairs, but drawn as single-ended to sim-
plify the drawing.
Bold red lines
signal path.
are active connections highlighting the
CLK_SELA = 1
M
ULTI-RATE PHY
SFP MODULE
CLKA0
CLKA1
Tx
Rx
0
QA
Rx
1
100BaseFX
CLKB
Tx
QB0
QB1
CLK_SELB = 1
Tx
Rx
ICS85454
1000BaseX
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
9
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85454.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85454 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 2.5V + 5ꢀ = 2.625V, which gives worst case results.
DD
•
Power_ = V
* I
= 2.625V * 94mA = 247mW
DD_MAX
MAX
DD_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability
TM
of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming
no air flow and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.247W * 51.5°C/W = 97.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 16-PIN VFQFN, FORCED CONVECTION
JA
θ vs. 0 Air Flow (Linear Feet per Minute)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
10
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 16 LEAD VFQFN
JA
θ at 0 Air Flow (Linear Feet per Minute)
JA
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TRANSISTOR COUNT
The transistor count for ICS85454 is: 189
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
11
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN
(Ref.)
N & N
Even
Seating Plane
(N -1)x e
(Ref.)
A1
Index Area
L
A3
E2
N
N
(Typ.)
e
2
If N & N
are Even
1
Anvil
Singulation
2
(N -1)x e
(Ref.)
OR
E2
2
Sawn
Singulation
Top View
b
e
Thermal
Base
(Ref.)
D2
2
A
D
N & N
Odd
D2
C
0.08
C
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
16
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
4
4
3.0
D2
E
1.0
1.8
3.0
E2
L
1.0
1.8
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
12
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
TABLE 9. ORDERING INFORMATION
Part/Order Number
85454AK
Marking
454A
Package
Shipping Packaging
Tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
16 Lead VFQFN
85454AKT
454A
16 Lead VFQFN
2500 Tape & Reel
Tube
85454AKLF
85454AKLFT
44AL
16 Lead "Lead-Free" VFQFN
16 Lead "Lead-Free" VFQFN
44AL
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
13
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
13
Ordering Information Table - corrected lead-free marking.
A
7/20/06
T4D
4
7
LVDS DC Characteristics table - corrected VOD, ∆VOD, and ∆VOS.
Added Thermal Release Path.
B
12/21/06
IDT™ / ICS™ DUAL 2:1 AND 1:2 LVDS MULTIPLEXER
14
ICS85454 REV. B FEBRUARY 24, 2009
ICS85454
DUAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
85454AK-01
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, MO-220, VFQFN-16
IDT
85454AK-01LF
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16
IDT
85454AK-01LFT
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16
IDT
85454AK-01T
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, MO-220, VFQFN-16
IDT
85454AKLF
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16
IDT
85454AKLFT
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, ROHS COMPLIANT, MO-220, VFQFN-16
IDT
85454AKT
Low Skew Clock Driver, 85454 Series, 3 True Output(s), 0 Inverted Output(s), 3 X 3 MM, 0.95 MM HEIGHT, MO-220, VFQFN-16
IDT
854550-1
69.99 MHz SAW Bandpass Filter for CDMA Basestation Receiver Applications Part Number 854550-1
TRIQUINT
©2020 ICPDF网 联系我们和版权申明