854S202AYI-01_技术文档

12:2, Differential-To-LVDS Multiplexer

ICS854S202I-01

DATASHEET

General Description

Features

The ICS854S202I-01 is a 12:2 Differential-to-LVDS Clock Multiplexer

which can operate up to 3GHz. The ICS854S202I-01 has twelve se-

lectable differential clock inputs, any of which can be independently

routed to either of the two LVDS outputs. The CLKx, nCLKx input

pairs can accept LVPECL, LVDS or CML levels. The fully differential

architecture and low propagation delay make it ideal for use in clock

distribution circuits.

• Two differential 2.5V LVDS clock outputs

• Twelve selectable differential clock inputs

• CLKx, nCLKx pairs can accept the following differential input levels:

LVPECL, LVDS, CML

• Maximum output frequency: 3GHz

• Propagation delay: 1.1ns (maximum)

• Input skew: 100ps (maximum)

• Output skew: 50ps (maximum)

• Part-to-part skew: 250ps (maximum)

• Additive phase jitter, RMS (12kHz – 20MHz): 0.16ps (typical)

• Full 2.5V operating supply mode

• -40°C to 85°C ambient operating temperature

Pin Assignment

Block Diagram

4

Pulldown

SELA_[3:0]

Pulldown

CLK0

Pullup/Pulldown

nCLK0

48 47 46 45 44 43 42 41 40 39 38 37

Pulldown

CLK1

CLK2

nCLK2

1

36

35

34

33

32

31

30

29

28

27

26

25

CLK9

Pullup/Pulldown

nCLK1

2

nCLK9

SELB_0

SELB_1

SELA_0

SELA_1

3

Pulldown

CLK2

ICS854S202I-01

48-Pin LQFP

7mm x 7mm x 1.4mm

package body

Y Package

4

Pullup/Pulldown

nCLK2

V

5

V

DD

QB

DD

QA

nQA

Pulldown

QA

nQA

6

CLK3

Pullup/Pulldown

7

nQB

nCLK3

Pullup

GND

8

GND

OEA

Pulldown

CLK4

SELA_2

SELA_3

CLK3

9

SELB_2

SELB_3

CLK8

nCLK8

Pullup/Pulldown

Top View

nCLK4

10

11

12

Pulldown

CLK5

nCLK3

Pullup/Pulldown

13 14 15 16 17 18 19 20 21 22 23 24

nCLK5

Pulldown

CLK6

Pullup/Pulldown

nCLK6

Pulldown

CLK7

Pullup/Pulldown

nCLK7

Pulldown

CLK8

QB

nQB

Pullup/Pulldown

nCLK8

Pulldown

Pullup

CLK9

OEB

Pullup/Pulldown

nCLK9

Pulldown

CLK10

Pullup/Pulldown

nCLK10

Pulldown

CLK11

Pullup/Pulldown

nCLK11

4

Pulldown

SELB_[3:0]

ICS854S202AYI-01 REV. A DECEMBER 18, 2012

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Table 1. Pin Descriptions

Number

Name

CLK2

Type

Pulldown

Description

Non-inverting differential clock input.

1

2

Input

nCLK2

Pullup/Pulldown Inverting differential clock input. V_DD/2 default when left floating.

3,

4,

9,

SELA_0,

SELA_1,

SELA_2,

SELA_3

Clock select pins for Bank A output pair. See Control Input Function

Pulldown

Input

Table. LVCMOS/LVTTL interface levels. See Table 3B.

10

5, 18, 32, 43

6, 7

V_DD

Power

Output

Power supply pins.

QA, nQA

Clock outputs. LVDS interface levels.

8, 15, 22, 29,

39, 46

GND

Power

Power supply ground.

11

12

CLK3

nCLK3

nCLK4

CLK4

nCLK5

CLK5

V_DD

Input

Power

Pulldown

Non-inverting differential clock input.

Pullup/Pulldown Inverting differential clock input. V_DD/2 default when left floating.

13

14

Pulldown

Non-inverting differential clock input.

16

Pullup/Pulldown Inverting differential clock input. V_DD/2 default when left floating.

17

Pulldown

Non-inverting differential clock input.

Positive supply pins.

18, 43

Output enable pin. Controls enabling and disabling of QA, nQA

output pair. LVCMOS/LVTTL interface levels.

19

OEA

Input

Pullup

20

21

23

24

25

26

CLK6

nCLK6

CLK7

Input

Pulldown

Non-inverting differential clock input.

Pullup/Pulldown Inverting differential clock input. V_DD/2 default when left floating.

Pulldown Non-inverting differential clock input.

nCLK7

nCLK8

CLK8

Pullup/Pulldown Inverting differential clock input. V_DD/2 default when left floating.

Pulldown

Non-inverting differential clock input.

27,

28,

33,

34

SELB_3,

SELB_2,

SELB_1,

SELB_0

Clock select pins for Bank B output pair. See Control Input Function

Table. LVCMOS/LVTTL interface levels. See Table 3C.

Input

Pulldown

30, 31

35

nQB, QB

nCLK9

CLK9

Output

Input

Clock outputs. LVDS interface levels.

Pullup/Pulldown Inverting differential clock input. V_DD/2 default when left floating.

Pulldown Non-inverting differential clock input.

Pullup/Pulldown Inverting differential clock input. V_DD/2 default when left floating.

Pulldown Non-inverting differential clock input.

Pullup/Pulldown Inverting differential clock input. V_DD/2 default when left floating.

36

37

nCLK10

CLK10

nCLK11

CLK11

38

40

41

Pulldown

Pullup

Non-inverting differential clock input.

Output enable pin. Controls enabling and disabling of QB, nQB

output pair. LVCMOS/LVTTL interface levels.

42

44

OEB

Input

CLK0

Pulldown

Non-inverting differential clock input.

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Number

45

Name

nCLK0

CLK1

Type

Pullup/Pulldown Inverting differential clock input. V_DD/2 default when left floating.

Pulldown Non-inverting differential clock input.

Pullup/Pulldown Inverting differential clock input. V_DD/2 default when left floating.

Description

Input

47

48

nCLK1

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

pF

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

2

R_PULLUP

R_PULLDOWN

51

k

Table 3A. OEA, OEB Control Input Function Table

Input

Output

OEA, OEB

QA, nQA, QB, nQB

Disabled (Logic LOW)

Active (default)

0

1

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Table 3B. SEL_A Control Input Function Table

Control Input

Input Selected to QA, nQA

SELA_3

SELA_2

SELA_1

SELA_0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CLK0, nCLK0 (default)

CLK1, nCLK1

CLK2, nCLK2

CLK3, nCLK3

CLK4, nCLK4

CLK5, nCLK5

CLK6, nCLK6

CLK7, nCLK7

CLK8, nCLK8

CLK9, nCLK9

CLK10, nCLK10

CLK11, nCLK11

Output at logic LOW

Table 3C. SEL_B Control Input Function Table

Control Input

Input Selected to QB, nQB

SELB_3

SELB_2

SELB_1

SELB_0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CLK0, nCLK0 (default)

CLK1, nCLK1

CLK2, nCLK2

CLK3, nCLK3

CLK4, nCLK4

CLK5, nCLK5

CLK6, nCLK6

CLK7, nCLK7

CLK8, nCLK8

CLK9, nCLK9

CLK10, nCLK10

CLK11, nCLK11

Output at logic LOW

ICS854S202AYI-01 REV. A DECEMBER 18, 2012

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC

Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_DD

Inputs, V_I

4.6V

-0.5V to V_DD+ 0.5V

Outputs, I_O(LVDS)

Continuous Current

Surge Current

10mA

15mA

Package Thermal Impedance, _JA

70.2C/W (0 mps)

-65C to 150C

Storage Temperature, T_STG

Table 4A. Power Supply DC Characteristics, V_DD= 2.5V 5%, T_A= -40°C to 85°C

Symbol Parameter

V_DDPower Supply Voltage

I_DDPower Supply Current

Test Conditions

Minimum

Typical

2.5

Maximum

2.625

Units

V

2.375

110

128

ma

Table 4B. LVCMOS/LVTTL DC Characteristics, V_DD= 2.5V 5%, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

Minimum

1.7

Typical

Maximum

V_DD+ 0.3

0.7

Units

V_IH

V_IL

Input High Voltage

V

Input Low Voltage

-0.3

SELA_[3:0],

SELB_[3:0]

V_DD= 2.625V

150

10

A

Input High

Current

I_IH

OEA, OEB

SELA_[3:0,

SELB_[3:0]

V_DD= 2.625V, V_IN= 0V

-10

Input Low

Current

I_IL

OEA, OEB

-150

Table 4C. Differential DC Characteristics, V_DD= 2.5V 5%, T_A= -40°C to 85°C

Symbol Parameter

Test Conditions

V_DD= V_IN= 2.625V

V_DD= 2.625V, V_IN= 0V

Minimum

Typical

Maximum

Units

Input High

Current

CLK[0:11],

nCLK[0:11]

I_IH

150

A

CLK[0:11]

-10

-150

0.15

A

V

Input Low

Current

I_IL

nCLK[0:11]

V

_DD= 2.625V, V_IN= 0V

V_PP

Peak-to-Peak Input Voltage; NOTE 1

1.5

Common Mode Input Voltage:

NOTE 1, 2

V_CMR

GND + 0.5

V_DD– 0.7

V

NOTE 1: V_ILshould not be less than -0.3V.

NOTE 2: Common mode voltage is defined as V_IH.

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Table 4D. LVDS DC Characteristics, V_DD= 2.5V 5%, T_A= -40°C to 85°C

Symbol

V_OD

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

mV

V

Differential Output Voltage

V_ODMagnitude Change

Offset Voltage

247

454

50

V_OD

V_OS

1.2

1.4

50

V_OS

V_OSMagnitude Change

mV

Table 5. AC Characteristics, V_DD= 2.5V 5%, T_A= -40°C to 85°C

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

3

Units

GHz

ps

f_OUT

Output Frequency

f_OUT< 2GHz

450

550

450

550

660

700

660

700

25

1100

900

Propagation Delay, Low to High;

NOTE 1

tp_LH

tp_HL

f

_OUT> 2GHz

ps

f_OUT< 2GHz

f_OUT> 2GHz

1100

900

ps

Propagation Delay, High to Low;

NOTE 1

ps

tsk(o)

tsk(i)

Output Skew; NOTE 2, 3

Input Skew; NOTE 3

50

ps

25

100

ps

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

250

ps

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter

section, NOTE 5

155.52MHz,

Integration Range:

12kHz - 20MHz

tjit

0.16

0.215

ps

t_R/ t_F

Output Rise/Fall Time

Output Duty Cycle; NOTE 6

MUX Isolation

20% to 80%

50

40

110

50

250

60

ps

%

odc

MUX_ISOLATION

f_OUT< 1.2GHz

75

dB

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range. NOTE that phase noise may increase

slightly with higher operating temperature. However, they will remain in spec as long as the maximum transistor junction temperature is not

violated. The device will meet specifications after thermal equilibrium has been reached under these conditions.

NOTE 1: Measured from the differential input cross point to the differential output cross point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output

cross point.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltage, same frequency, same temperature and

with equal load conditions. Using the same type of input on each device, measured at the differential output cross point.

NOTE 5: Driving only one input clock.

NOTE 6: The output duty cycle will depend on the input duty cycle.

ICS854S202AYI-01 REV. A DECEMBER 18, 2012

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot and

is most often the specified plot in many applications. Phase noise is

defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

Offset From Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements have

issues. The primary issue relates to the limitations of the equipment.

Often the noise floor of the equipment is higher than the noise floor

of the device. This is illustrated above. The device meets the noise

floor of what is shown, but can actually be lower. The phase noise is

dependent on the input source and measurement equipment.

Used the Rhode & Schwartz SMA100 as the input source.

ICS854S202AYI-01 REV. A DECEMBER 18, 2012

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Parameter Measurement Information

V_DD

SCOPE

Qx

nCLK[0:11]

CLK[0:11]

2.5V 5%

V_DD

POWER SUPPLY

V_PP

V_CMR

Cross Points

+

Float GND –

nQx

GND

2.5V Output Load Test Circuit

Differential Input Level

nCLKx

CLKx

Part 1

nQx

nQA

QA

Qx

Part 2

nQy

t_PD1

Qy

tsk(pp)

nCLKy

CLKy

nQB

Part-to-Part Skew

QB

t_PD2

nQx

Qx

tsk(i) = |t_PD1- t_PD2

|

Input Skew

nQy

Qy

tsk(o)

Output Skew

ICS854S202AYI-01 REV. A DECEMBER 18, 2012

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Parameter Measurement Information, continued

nQA, nQB

QA, QB

80%

t_F

80%

t_R

t_PW

V_OD

20%

t_PERIOD

20%

QA, QB

t_PW

odc =

x 100%

t_PERIOD

Output Duty Cycle/Pulse Width

Output Rise/Fall Time

Spectrum of Output Signal Q

MUX selects active

input clock signal

A0

A1

nCLK[0:11]

CLK[0:11]

MUX_{_ISOL}= A0 – A1

nQA, nQB

MUX selects static input

QA, QB

tp_LH

tp_HL

ƒ

Frequency

(fundamental)

Propagation Delay

MUX Isolation

V_DD

out

DC Input

LVDS

V_OS/Δ V_OS

ä

Differential Output Voltage Setup

Offset Voltage Setup

ICS854S202AYI-01 REV. A DECEMBER 18, 2012

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Applications Information

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

CLK/nCLK Inputs

LVDS Outputs

For applications requiring only one differential input, the unused CLK

and nCLK input can be left floating. Though not required, but for

additional protection, a 1k resistor can be tied from CLK pin to

ground.

All unused LVDS output pairs can be either left floating or terminated

with 100 across. If they are left floating, there should be no trace

attached

LVCMOS Control Pins

All control pins have internal pullups or pulldowns; additional

resistance is not required but can be added for additional protection.

A 1k resistor can be used.

Wiring the Differential Input to Accept Single-Ended Levels

Figure 1 shows how a differential input can be wired to accept single

ended levels. The reference voltage V₁= V_DD/2 is generated by the

bias resistors R1 and R2. The bypass capacitor (C1) is used to help

filter noise on the DC bias. This bias circuit should be located as close

to the input pin as possible. The ratio of R1 and R2 might need to be

adjusted to position the V₁in the center of the input voltage swing. For

example, if the input clock swing is 2.5V and V_DD= 2.5V, R1 and R2

value should be adjusted to set V₁at 1.25V. The values below are for

when both the single ended swing and V_DDare at the same voltage.

This configuration requires that the sum of the output impedance of

the driver (Ro) and the series resistance (Rs) equals the transmission

line impedance. In addition, matched termination at the input will

attenuate the signal in half. This can be done in one of two ways.

First, R3 and R4 in parallel should equal the transmission line

impedance. For most 50 applications, R3 and R4 can be 100. The

values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however V_ILcannot be less

than -0.3V and V_IHcannot be more than V_DD+ 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

ICS854S202AYI-01 REV. A DECEMBER 18, 2012

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

2.5V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, CML and other differential

signals. Both differential signals must meet the V_PPand V_CMRinput

requirements. Figures 2A to 2E show interface examples for the

IN/nIN input with built-in 50 terminations driven by the most

common driver types. The input interfaces suggested here are

examples only. If the driver is from another vendor, use their

termination recommendation. Please consult with the vendor of the

driver component to confirm the driver termination requirements.

2.5V

R3

R4

Zo = 50

250

CLK

Zo = 50

CLK

Zo = 50

nCLK

Differential

LVPECL

nCLK

Input

R1

R2

Differential

Input

50

LVPECL

R1

R2

62.5

R3

18

Figure 2A. CLK/nCLK Input Driven by a 

Figure 2B. CLK/nCLK Input Driven by a 

2.5V LVPECL Driver

2.5V

Zo = 50

Zo = 50Ω

CLK

R1

100

100Ω

nCLK

Zo = 50

Zo = 50Ω

Differential

Input

Differential

Input

LVDS

CML Built-In Pullup

Figure 2C. CLK/nCLK Input Driven by a 

2.5V LVDS Driver

Figure 2D. CLK/nCLK Input Driven by a

Built-In Pullup CML Driver

2.5V

R1

R2

50Ω

Zo = 50Ω

CLK

nCLK

Differential

Input

CML

Figure 2E. CLK/nCLK Input Driven by an

IDT Open Collector CML Driver

ICS854S202AYI-01 REV. A DECEMBER 18, 2012

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

LVDS Driver Termination

For a general LVDS interface, the recommended value for the

termination impedance (Z_T) is between 90 and 132. The actual

value should be selected to match the differential impedance (Z₀) of

your transmission line. A typical point-to-point LVDS design uses a

100 parallel resistor at the receiver and a 100 differential

transmission-line environment. In order to avoid any

transmission-line reflection issues, the components should be

surface mounted and must be placed as close to the receiver as

possible. IDT offers a full line of LVDS compliant devices with two

types of output structures: current source and voltage source. The

standard termination schematic as shown in Figure 3A can be used

with either type of output structure. Figure 3B, which can also be

used with both output types, is an optional termination with center tap

capacitance to help filter common mode noise. The capacitor value

should be approximately 50pF. If using a non-standard termination, it

is recommended to contact IDT and confirm if the output structure is

current source or voltage source type. In addition, since these

outputs are LVDS compatible, the input receiver’s amplitude and

common-mode input range should be verified for compatibility with

the output.

Z_O Z_T

LVDS

Driver

LVDS

Receiver

Z_T

Figure 3A. Standard Termination

Z_T

Z_O Z_T

LVDS

Driver

LVDS

Receiver

2

Z_T

2

C

Figure 3B. Optional Termination

LVDS Termination

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

LVDS Power Considerations

This section provides information on power dissipation and junction temperature for the ICS854S202I-01. 

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS854S202I-01 is the sum of the core power plus the output power dissipated due to the load. 

The following is the power dissipation for V_DD= 2.5V + 5% = 2.625V, which gives worst case results.

•

Power_MAX= V_{DD_MAX}* I_{DD_MAX}= 2.6255V * 128mA = 336mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = _JA* Pd_total + T_A

Tj = Junction Temperature

_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance _JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 70.2°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.336W * 70.2°C/W = 108.6°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6. Thermal Resistance _JAfor 48 Lead LQFP, Forced Convection

_JAby Velocity

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

70.2°C/W

60.4°C/W

56.9°C/W

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ICS854S202I-01 Data Sheet

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Reliability Information

Table 7. _JAvs. Air Flow Table for a 48 Lead LQFP,

_JAvs. Air Flow

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

70.2°C/W

60.4°C/W

56.9°C/W

Transistor Count

The transistor count for ICS854S202I-01 is: 8,537

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12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

Package Outline and Package Dimensions

Package Outline - Y Suffix for 48 Lead LQFP

Table 8. Package Dimensions for 48 Lead LQFP

JEDEC Variation: BBC - HD

All Dimensions in Millimeters

Symbol

Minimum

Nominal

Maximum

N

48

A

1.60

0.15

1.45

0.27

0.20

A1

0.05

1.35

0.17

0.09

0.10

1.40

0.22

A2

b

c

D & E

D1 & E1

D2 & E2

e

9.00 Basic

7.00 Basic

5.50 Ref.

0.5 Basic

0.60

L

0.45

0°

0.75

7°



ccc

0.08

Reference Document: JEDEC Publication 95, MS-026

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Ordering Information

Table 9. Ordering Information

Part/Order Number

854S202AYI-01LF

854S202AYI-01LFT

Marking

ICSS202AI01L

Package

“Lead-Free” 48 Lead LQFP

Shipping Packaging

Tray

Temperature

-40C to 85C

Tape & Reel

ICS854S202AYI-01 REV. A DECEMBER 18, 2012

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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

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party owners.


型号：	854S202AYI-01
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Differential Multiplexer, 2 Func, 12 Channel, PQFP48
文件：	总17页 (文件大小：449K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

854S202AYI-01 [IDT]

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