86004BG-01T [IDT]
Clock Driver, PDSO16;
| 型号： | 86004BG-01T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, PDSO16 光电二极管 |
| 文件： | 总12页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
62.5MHZ TO 250MHZ, 1:4 LVCMOS/
LVTTL ZERO DELAY CLOCK BUFFER
ICS86004-01
FEATURES
GENERAL DESCRIPTION
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Single LVCMOS/LVTTL clock input
The ICS86004-01 is a high performance 1-to-4
ICS
HiPerClockS™
LVCMOS/LVTTL Clock Buffer and a member of
the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The ICS86004-01 has a
fully integrated PLL and can be configured as zero
• CLK accepts the following input levels: LVCMOS or LVTTL
• Output frequency range: 62.5MHz to 250MHz
• Input frequency range: 62.5MHz to 250MHz
delay buffer and has an input and output frequency range of
62.5MHz to 250MHz. The external feedback allows the
device to achieve “zero delay” between the input clock and the
output clocks. The PLL_SEL pin can be used to bypass the
PLL for system test and debug purposes. In bypass mode, the
reference clock is routed around the PLL and into the
internal output divider.
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Fully integrated PLL
• Cycle-to-cycle jitter, (F_SEL = 1): 45ps (maximum)
• Output skew: 60ps (maximum)
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• 5V tolerant input
• -40°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
CONTROL INPUT FUNCTION TABLE
Input/Output
Input
Frequency Range (MHz)
F_SEL
Minimum
125
Maximum
250
0
1
62.5
125
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
1
2
3
4
5
6
7
8
Q1
GND
Q0
F_SEL
VDD
CLK
GND
VDDA
16
15
14
13
12
11
10
9
VDDO
Q2
GND
Q3
VDDO
MR
FB_IN
PLL_SEL
Q0
Q1
Q2
Q3
÷8
0
1
CLK
PLL
1:1
FB_IN
ICS86004-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
MR
F_SEL
IDT™ / ICS™ LVCMOS ZERO DELAY CLOCK BUFFER
1
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 3,
13, 15
Name
Q1, Q0,
Q3, Q2
Type
Output
Power
Description
Clock outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels.
2, 7, 14
4
GND
Power supply ground.
Frequency range select input. When LOW, I/O frequency range is from
F_SEL
Input Pulldown 125MHz to 250Mz. When HIGH, I/O frequency range is from
62.5MHz to 125MHz. LVCMOS/LVTTL interface levels.
5
6
8
VDD
CLK
VDDA
Power
Core supply pin.
Input Pulldown LVCMOS/LVTTL clock input.
Power
Analog supply pin.
Selects between the PLL and reference clock as input to the dividers.
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
9
PLL_SEL Input
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
10
FB_IN
Input Pulldown
11
MR
Input Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
12, 16
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
VDD, VDDO = 3.465V
VDD, VDDO = 2.625V
3.3V 5%
23
17
12
pF
pF
Ω
CPD
Power Dissipation Capacitance
(per output)
ROUT
Output Impedance
5
7
TABLE 3. CONTROL INPUT FUNCTION TABLE
Input/Output
Input
Frequency Range (MHz)
F_SEL
Minimum
125
Maximum
250
0
1
62.5
125
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
2
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to +5.0V
-0.5V to VDDO + 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
Package Thermal Impedance, θ
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
VDD
3.465
100
16
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
6
NOTE: Special thermal handling maybe required in some configurations.
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.465
VDD
2.625
100
16
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
3.3
2.375
2.5
V
mA
mA
mA
IDDA
IDDO
6
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.625
VDD
2.625
96
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
2.375
2.5
2.375
2.5
V
mA
mA
mA
IDDA
IDDO
15
6
NOTE: Special thermal handling maybe required in some configurations.
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
3
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V 5% OR 2.5V 5%, TA = -40°C TO 70°C
Symbol Parameter
Test Conditions
VDD = 3.465V
VDD = 2.625V
VDD = 3.465V
VDD = 2.625V
Minimum Typical Maximum Units
2.0
1.7
5.0
5.0
0.8
0.7
V
V
V
V
VIH
VIL
Input High Voltage
-0.3
-0.3
Input Low Voltage
Input High Current
CLK, MR,
FB_IN, F_SEL
VDD = VIN = 3.465V or 2.625V
150
5
µA
µA
IIH
PLL_SEL
V
DD = VIN = 3.465V or 2.625V
CLK, MR,
FB_IN, F_SEL
VDD = 3.465V or 2.625V,
VIN = 0V
-5
µA
µA
IIL
Input Low Current
VDD = 3.465V or 2.625V,
VIN = 0V
PLL_SEL
-150
VDDO = 3.465V
VDDO = 2.625V
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 3.465V or 2.625V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagrams.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40°C TO 70°C
Symbol Parameter
Test Conditions
F_SEL = 0
Minimum Typical Maximum Units
125
250
125
MHz
MHz
fMAX
Output Frequency
F_SEL = 1
62.5
PLL_SEL = 0V,
Bypass Mode
PLL_SEL = 3.3V
PLL_SEL = 0V
F_SEL = 0
tpLH
Propagation Delay, Low-to-High; NOTE 1
4.1
-75
5.1
50
6.1
ns
t(Ø)
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
175
60
65
45
1
ps
ps
ps
ps
mS
ps
%
tsk(o)
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
F_SEL = 1
tL
PLL Lock Time
tR / tF
Output Rise/Fall Time
300
44
750
56
53
F_SEL = 0
F_SEL = 1
50
50
odc
Output Duty Cycle
47
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.All parameters measured at fMAX unless
noted otherwise.
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
4
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 70°C
Symbol Parameter
Test Conditions
F_SEL = 0
Minimum Typical Maximum Units
125
250
125
MHz
MHz
fMAX
Output Frequency
F_SEL = 1
62.5
PLL_SEL = 0V,
Bypass Mode
PLL_SEL = 3.3V
PLL_SEL = 0V
F_SEL = 0
tpLH
Propagation Delay, Low-to-High; NOTE 1
4.25
-300
5.25
6.25
ns
t(Ø)
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
0
60
65
45
1
ps
ps
ps
ps
mS
ps
%
tsk(o)
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
F_SEL = 1
tL
PLL Lock Time
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
45
700
55
50
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.All parameters measured at fMAX unless
noted otherwise.
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40°C TO 70°C
Symbol Parameter
Test Conditions
F_SEL = 0
Minimum Typical Maximum Units
125
250
125
MHz
MHz
fMAX
Output Frequency
F_SEL = 1
62.5
PLL_SEL = 0V,
Bypass Mode
tpLH
Propagation Delay, Low-to-High; NOTE 1
4.5
5.5
6.5
ns
t(Ø)
Static Phase Offset; NOTE 2, 4
Output Skew; NOTE 3, 4
PLL_SEL = 3.3V
PLL_SEL = 0V
F_SEL = 0
-100
250
55
65
45
1
ps
ps
ps
ps
mS
ps
%
tsk(o)
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
F_SEL = 1
tL
PLL Lock Time
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
45
700
55
50
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.All parameters measured at fMAX unless
noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
5
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5%
2.05V 5%
1.25V 5%
SCOPE
VDD
VDDA
VDDO
,
SCOPE
VDD
VDDA
,
,
VDDO
GND
Qx
Qx
LVCMOS
LVCMOS
GND
-1.65V 5%
-1.25V 5%
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5%
VDDO
2
VDDO
2
VDDO
2
SCOPE
VDD
VDDA
,
Q0:Q3
,
VDDO
➤
➤
Qx
t
t
c
c
y
y
c
c
l
l
e
e n
n
tcycle n+1
tcycle n+1
➤
➤
LVCMOS
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
GND
-1.25V 5%
2.5VCORE/ 2.5V OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
VDD
2
CLK
VDDO
Qx
Qy
2
VDD
2
FB_IN
➤
VDDO
2
➤
t(Ø)
tsk(o)
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
OUTPUT SKEW
STATIC PHASE OFFSET
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
6
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
VDDO
2
VDDO
2
VDDO
2
80%
tF
80%
tR
Q0:Q3
tPW
20%
20%
Q0:Q3
tPERIOD
tPW
tPERIOD
odc =
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
2
CLK
VDDO
2
Q0:Q3
t
PD
PROPAGATION DELAY
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
7
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS86004-01
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA and VDDO
should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic VDD pin and
also shows that VDDA requires that an additional 10Ω resistor
along with a 10µF bypass capacitor be connected to the VDDA
3.3V or 2.5V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
pin.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVCMOS output can be left floating. We recommend
that there is no trace attached.
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of using an ICS86004-01.
It is recommended to have one decouple capacitor per power
pin. Each decoupling capacitor should be located as close as
possible to the power pin. The low pass filter R7, C11 and C16
for clean analog supply should also be located as close to the
VDDA pin as possible.
R1
43
VDD
Zo = 50
Serial Termination
R3
1K
VDD
U1
R2
43
VDD
1
16
15
14
13
12
11
10
9
Zo = 50
Q1
2
VDDO
Q2
GND
Q3
VDDO
MR
GND
3
Q0
4
F_SEL
VDD
CLK
GND
VDDA
Ro
~
7
Ohm
5
6
7
8
Zo = 50
VDD
FB_IN
PLL_SEL
R8
43
R11 43
LVCMOS
ICS86004-01
Zo = 50
R7
10
VDD R6
1K
C16
10u
C11
0.01u
VDD
Parallel Termination
(U1-5)
(U1-12)
(U1-16)
VDD
R4
100
C1
0.1uF
C2
0.1uF
C3
0.1uF
Zo = 50
VDD=3.3V
R5
100
FIGURE 2. ICS86004-01 SCHEMATIC EXAMPLE
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
8
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
RELIABILITY INFORMATION
TABLE 6. θ VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS86004-01 is: 2496
PACKAGE OUTLINE AND DIMENSIONS
PACKAGE OUTLINE - G SUFFIX 16 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
9
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
86004BG-01
Marking
86004B01
86004B01
6004B01L
6004B01L
Package
Shipping Packaging
tube
Temperature
-40°C to 70°C
-40°C to 70°C
-40°C to 70°C
-40°C to 70°C
16 Lead TSSOP
86004BG-01T
16 Lead TSSOP
2500 tape & reel
tube
86004BG-01LF
86004BG-01LFT
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
iapplications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
10
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
A
Throughout data sheet, changed part number from ICS86004I-01 to ICS86004-01.
12/16/03
1
11
Features section - added Lead-Free bullet.
A
A
9/7/04
T7
Ordering Information table - added Lead Free part number.
Changed temperature range throughout the data sheet from "-40°C - 85°C" to "
0°C - 70°C".
11/2/04
1
Features section - changed Ambient Operating Temperature from 0°C to -40°C and
throughout the datasheet.
T4A
T4B
T4C
T7
3
3
3.3V Power Supply Table - changed VDDA max. from 3.465V to VDD. Added note.
3.3V/2.5V Power Supply Table - changed VDDA max. from 3.465V to VDD. Added note.
2.5V Power Supply Table - changed VDDA max. from 3.465V to VDD. Added note.
Ordering Information Table - added lead-free note.
B
06/21/06
3
11
4
C
D
T4D
LVCMOS DC Characteristics Table - defined 2.5V VIH/VIL specs.
11/30/06
1/19/09
3
Absolute Maximum Ratings - Inputs, VI changed from -0.5V to VDD + 0.5V to
-0.5V to 5.0V.
Mix Power Supply Table - corrected VDD and VDDA from 2.5V to 3.3V .
LVCMOS DC Characteristics Table - VIH rows - changed max. from VDD + 0.3V to
5.0V.
T4B
T4D
3
4
T5A - T5C
5 - 6
AC Tables - added ambient temperature note.
IDT™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
11
ICS86004BG-01 REV. D JANUARY 19, 2009
ICS86004-01
62.5MHZ TO 250MHZ, 1:4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
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Printed in USA
相关型号：
86004BGI
Clock Driver, 86004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.925 MM HEIGHT, MO-153, TSSOP-16
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86004BGIT
Clock Driver, 86004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5 MM, 0.925 MM HEIGHT, MO-153, TSSOP-16
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86004G-01
PLL Based Clock Driver, 86004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5.0 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
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86004G-01LF
PLL Based Clock Driver, 86004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5.0 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
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86004G-01LFT
PLL Based Clock Driver, 86004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5.0 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
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86004G-01T
PLL Based Clock Driver, 86004 Series, 4 True Output(s), 0 Inverted Output(s), PDSO16, 4.40 X 5.0 MM, 0.92 MM HEIGHT, MO-153, TSSOP-16
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