8624BY [IDT]
PLL Based Clock Driver, 8624 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32;
| 型号： | 8624BY |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8624 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总19页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-5 Differential-to-HSTL
Zero Delay Buffer
ICS8624
DATA SHEET
Not Recommended for New Designs - 10/22/13
For replacement device use ICS8725BY-01LF
NRND
General Description
Features
The ICS8624 is a high performance, 1-to-5
• Fully integrated PLL
• Five differential HSTL output pairs
• Selectable differential CLKx/nCLKx input pairs
S
IC
Differential-to-HSTL zero delay buffer and a member
of the HiPerClockS™ family of High Performance
Clock Solutions from IDT. The ICS8624 has two
selectable clock input pairs. The CLK0, nCLK0 and
HiPerClockS™
• CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, HCSL, SSTL
CLK1, nCLK1 pair can accept most standard differential input levels.
The VCO operates at a frequency range of 250MHz to 700MHz.
Utilizing one of the outputs as feedback to the PLL, output
frequencies up to 700MHz can be regenerated with zero delay with
respect to the input. Dual reference clock inputs support redundant
clock or multiple reference applications.
• Output frequency range: 31.25MHz to 700MHz
• Input frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
• Cycle-to-cycle jitter: 25ps (maximum)
• Output skew: 25ps (maximum)
• Static phase offset: 100ps
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
Q0
nQ0
PLL_SEL
Q1
nQ1
32 31 30 29 28 27 26 25
÷4, ÷8
0
CLK0
Q2
nQ2
1
2
3
4
5
6
7
8
SEL0
VDDO
24
23
22
21
20
0
1
nCLK0
1
SEL1
CLK0
Q3
CLK1
nCLK1
Q3
nQ3
nQ3
Q2
PLL
nCLK0
CLK1
Q4
nQ4
CLK_SEL
nQ2
nCLK1
CLK_SEL
MR
Q1
19
18
17
FB_IN
nFB_IN
nQ1
VDDO
9
10 11 12 13 14 15 16
SEL0
SEL1
MR
ICS8624
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
ICS8624BY REVISION F OCTOBER 22, 2013
1
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Table 1. Pin Descriptions
Number
Name
Type
Description
Determines the input and output frequency range noted in Table 3A.
LVCMOS / LVTTL interface levels.
1, 2
SEL0, SEL1
Input
Pulldown
3
4
5
6
CLK0
nCLK0
CLK1
Input
Input
Input
Input
Pulldown
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Pulldown
Pullup
nCLK1
Clock select input. When HIGH, selects CLK1, nCLK1. When LOW, selects CLK0,
nCLK0. LVCMOS/LVTTL interface levels.
7
CLK_SEL
MR
Input
Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
8
Input
Pulldown
9, 32
10
VDD
Power
Input
Core supply pins.
Inverting differential feedback input to phase detector for regenerating clocks with
“Zero Delay.”
nFB_IN
Pullup
Non-inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
11
FB_IN
Input
Pulldown
12, 13,
28, 29
GND
nQ0, Q0
VDDO
Power
Output
Power
Power supply ground.
14, 15
Differential output pair. HSTL interface levels.
Output supply pins.
16, 17,
24, 25
18, 19
20, 21
22, 23
26, 27
30
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
VDDA
Output
Output
Output
Output
Power
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Analog supply pin.
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
31
PLL_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
k
RPULLDOWN Input Pulldown Resistor
k
ICS8624BY REVISION F OCTOBER 22, 2013
2
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
PLL_SEL = 1
PLL Enable Mode
SEL1
SEL0
Reference Frequency Range (MHz)*
Q[0:4], nQ[0:4]
0
0
1
1
0
1
0
1
250 - 700
125 - 350
÷1
÷1
÷1
÷1
62.5 - 175
31.25 - 87.5
*NOTE: VCO frequency range for all configurations above is 250MHz to 700MHz.
Table 3B. PLL Bypass Function Table
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL1
SEL0
Q[0:4], nQ[0:4]
0
0
1
1
0
1
0
1
÷4
÷4
÷4
÷8
ICS8624BY REVISION F OCTOBER 22, 2013
3
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
47.9C/W (0 lfpm)
-65C to 150C
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO = 1.5V to 2V, TA = 0°C to 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
3.135
1.5
Typical
3.3
Maximum
3.465
3.465
2.0
Units
V
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDDA
VDDO
IDD
3.3
V
1.8
V
120
mA
mA
mA
IDDA
15
IDDO
0
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
VDD + 0.3
0.8
Units
Input High Voltage
Input Low Voltage
2
V
V
VIL
-0.3
CLK_SEL,
SEL[0:1], MR
VDD = VIN = 3.465V
150
5
µA
µA
µA
µA
IIH
Input High Current
Input Low Current
PLL_SEL
VDD = VIN = 3.465V
CLK_SEL,
SEL[0:1], MR
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
IIL
PLL_SEL
-150
ICS8624BY REVISION F OCTOBER 22, 2013
4
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Table 4C. Differential DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
FB_IN, CLK0, CLK1
nFB_IN, nCLK0, nCLK1
FB_IN, CLK0, CLK1
nFB_IN, nCLK0, nCLK1
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
IIH Input High Current
V
-5
-150
0.1
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Voltage; NOTE 1
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. HSTL DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
1.0
0
1.4
0.4
60
V
V
VOL
Output Low Voltage; NOTE 1
VOX
Output Crossover Voltage; NOTE 2
Peak-to-Peak Output Voltage Swing
40
0.6
%
V
VSWING
1.1
NOTE 1: Outputs terminated with 50 to ground.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Table 5. Input Frequency Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum
Typical
Maximum
700
Units
MHz
MHz
31.25
CLK0, nCLK0,
CLK1, nCLK1
FIN
Input Frequency
700
ICS8624BY REVISION F OCTOBER 22, 2013
5
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
AC Electrical Characteristics
Table 6A. AC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol
fMAX
tPD
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ns
Output Frequency
700
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
ƒ 700MHz
3.2
4.4
t(Ø)
PLL_SEL = 3.3V
-100
100
ps
tsk(o)
tjit(cc)
tjit()
tL
25
ps
25
ps
50
1
ps
ms
ps
tR / tF
tPW
Output Rise/Fall Time
Output Pulse Width
20% to 80% @ 50MHz
300
700
tcycle/2 - 85
tcycle/2
tcycle/2 + 85
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when
the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
Table 6B. AC Characteristics, VDD = 3.3V 10%, VDDO = 1.8V 0.2V, TA = 0°C to 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Typical
Maximum
Units
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
35
ps
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
Table 6C. AC Characteristics, VDD = 3.3V 5%, VDDO = 1.5V to 1.6V, TA = 0°C to 70°C
Symbol
fMAX
tPD
Parameter
Test Conditions
Minimum
Maximum
Units
MHz
ns
Output Frequency
700
Propagation Delay; NOTE 1
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
ƒ 700MHz
3.2
4.4
t(Ø)
PLL_SEL = 3.3V
-100
150
ps
tsk(o)
tjit(cc)
tjit()
tL
35
ps
25
ps
50
1
ps
ms
ps
tR / tF
tPW
Output Rise/Fall Time
Output Pulse Width
20% to 80% @ 50MHz
300
700
tcycle/2 - 95
tcycle/2
tcycle/2 + 95
ps
For NOTES, see Table 6A above.
ICS8624BY REVISION F OCTOBER 22, 2013
6
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Parameter Measurement Information
3.3V 5%
1.8V 0.2V
V
DD
SCOPE
Qx
V
DD,
V
nCLK0, nCLK1
DDA
V
DDO
VPP
VCMR
Cross Points
HSTL
CLK0, CLK1
GND
nQx
GND
0V
0V
3.3V Core/1.8V Output Load AC Test Circuit
Differential Input Level
nCLK0, nCLK1
CLK0, CLK1
nFB_IN
VOH
VOL
nQx
Qx
VOH
VOL
FB_IN
nQy
Qy
➤
t(Ø)
➤
tjit(Ø) = ⎪ t(Ø) – t(Ø) mean⎪= Phase Jitter
t(Ø) mean = Static Phase Offset
Where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on the controlled edges)
Phase Jitter and Static Phase Offset
Output Skew
nQ[0:4]
VDDO
nQ[0:4]
Q[0:4]
VDDO
2
VDDO
2
2
Q[0:4]
Pulse Width
tcycle n
tcycle n+1
tPERIOD
tjit(cc) = tcycle n – tcycle n+1
|
|
1000 Cycles
Cycle-to-Cycle Jitter
Output Pulse Width/Period
ICS8624BY REVISION F OCTOBER 22, 2013
7
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Parameter Measurement Information, continued
nCLK0,
nCLK1
nQ[0:4]
Q[0:4]
80%
tF
80%
tR
CLK0,
CLK1
VOX
20%
VSWING
20%
nQ[0:4]
Q[0:4]
tPD
Propagation Delay
Output Rise/Fall Time
Application Information
Power Supply Filtering Technique
To achieve optimum jitter performance, power supply isolation is
required. To achieve optimum jitter performance, power supply
isolation is required. The ICS8624 provides separate power supplies
to isolate any high switching noise from the outputs to the internal
PLL. VDD, VDDA and VDDO should be individually connected to the
power supply plane through vias, and 0.01µF bypass capacitors
should be used for each pin. Figure 1 illustrates this for a generic VDD
pin and also shows that VDDA requires that an additional 10 resistor
along with a 10F bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
.01µF
10Ω
VDDA
10µF
Figure 1. Power Supply Filtering
ICS8624BY REVISION F OCTOBER 22, 2013
8
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Recommendations for Unused Input and Output Pins
Outputs:
Inputs:
LVCMOS Control Pins
HSTL Outputs
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
All unused HSTL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
VDD
R1
1K
CLK_IN
CLKx
V_REF
nCLKx
C1
0.1uF
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
ICS8624BY REVISION F OCTOBER 22, 2013
9
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the VPP and VCMR
input requirements. Figures 3A to 3F show interface examples for the
HiPerClockS CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 3A, the input
termination applies for IDT HiPerClockS open emitter LVHSTL
drivers. If you are using an LVHSTL driver from another vendor, use
their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
Input
nCLK
LVPECL
Differential
Input
R1
50Ω
R2
50Ω
LVHSTL
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
R2
50Ω
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
3.3V
Zo = 50Ω
CLK
CLK
R1
100Ω
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Receiver
LVDS
Figure 3C. HiPerClockS CLK/nCLK Input
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
*R3
Zo = 60Ω
Zo = 60Ω
CLK
CLK
nCLK
nCLK
Differential
Input
Differential
Input
*R4
SSTL
HCSL
R1
R2
120Ω
120Ω
Figure 3E. HiPerClockS CLK/nCLK Input
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Driven by a 2.5V SSTL Driver
ICS8624BY REVISION F OCTOBER 22, 2013
10
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Schematic Example
The schematic of the ICS8624 layout example is shown in Figure 4A.
The ICS8624 recommended PCB board layout for this example is
shown in Figure 4B. This layout example is used as a general
guideline. The layout in the actual system will depend on the selected
component types, the density of the components, the density of the
traces, and the stack up of the P.C. board.
VDD
SP = Spare (i.e. not installed)
R7
VDD
VDDA
RU2
SP
RU3
1K
RU4
1K
RU5
SP
10
C11
0.01u
VDD=3.3V
C16
10u
VDDO=1.8V
CLK_SEL
PLL_SEL
SEL0
SEL1
Zo = 50 Ohm
Zo = 50 Ohm
155.5 MHz
DIV_SEL[1:0] = 01
+
-
VDDO
RD2
1K
RD3
SP
RD4
SP
RD5
1K
LVHSTL_input
VDD
U1
R4A
50
R4B
50
3.3V
(155.5 MHz)
Zo = 50 Ohm
SEL0
SEL1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SEL0
SEL1
VDDO
Q3
nQ3
Q2
nQ2
Q1
nQ1
VDDO
CLK0
nCLK0
CLK1
nCLK2
CLK_SEL
MR
Bypass capacitor located near the power pins
Zo = 50 Ohm
CLK_SEL
VDD
(U1-9)
(U1-32)
3.3V PECL Driver
C1
0.1uF
C6
0.1uF
R8
50
R9
50
8624
VDDO
R10
50
(U1-16)
(U1-17)
(U1-24)
(U1-25)
R2B
50
R2A
50
C2
0.1uF
C4
0.1uF
C5
0.1uF
C7
0.1uF
Figure 4A. ICS8624 HSTL Zero Delay Buffer Schematic Example
ICS8624BY REVISION F OCTOBER 22, 2013
11
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
The following component footprints are used in this layout example:
All the resistors and capacitors are size 0603.
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
• The differential 50 output traces should have same length.
Power and Grounding
Place the decoupling capacitors C1, C6, C2, C4, and C5, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This can
reduce unwanted inductance between the decoupling capacitor and
the power pin caused by the via.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever possible,
avoid placing vias on the clock traces. Placement of vias on
the traces can affect the trace characteristic impedance and
hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace widths
between the differential clock trace and the other signal trace.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the VDDA pin as possible.
Clock Traces and Termination
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the clock
signal is less tolerant to poor signal integrity than other signals. Any
ringing on the rising or falling edge or excessive ring back can cause
system failure. The shape of the trace and the trace delay might be
restricted by the available space on the board and the component
• Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as close to the
receiver input pins as possible.
GND
R7
C16 C11
C7
VDDO
VDD
C6
C5
U1
Pin 1
VDDA
VIA
50 Ohm
Traces
C4
C1
C2
Figure 4B. PCB Board Layout for ICS8624
ICS8624BY REVISION F OCTOBER 22, 2013
12
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8624.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8624 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX)= 3.465V * (120mA + 15mA) = 467.775mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power_MAX (3.465V, with all outputs switching) = 467.775mW + 164mW = 631.775mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to
125°C ensures that the bond wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 47.9°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.632W * 47.9°C/W = 100.3°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance JA for 32 Lead LQFP, Forced Convection
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
ICS8624BY REVISION F OCTOBER 22, 2013
13
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the HSTL output pairs.
HSTL output driver circuit and termination are shown in Figure 5.
VDDO
Q1
VOUT
RL
50Ω
Figure 5. HSTL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /RL) * (VDDO_MAX – VOH_MAX
)
Pd_L = (VOL_MAX/RL) * (VDDO_MAX – VOL_MAX
)
Pd_H = (1V/50) * (2V – 1V) = 20mW
Pd_L = (0.4V/50) * (2V – 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
ICS8624BY REVISION F OCTOBER 22, 2013
14
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Reliability Information
Table 8. JA vs. Air Flow Table for a 32 Lead LQFP
JA vs. Air Flow
Linear Feet per Minute
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
Transistor Count
The transistor count for ICS8624 is: 1565
ICS8624BY REVISION F OCTOBER 22, 2013
15
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Package Outline and Dimensions
Package Outline - Y Suffix for 32 Lead LQFP
Table 9. Package Dimensions for 32 Lead LQFP
JEDEC Variation: BBA
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
0.15
1.45
0.45
0.20
A1
0.05
1.35
0.30
0.09
A2
1.40
0.37
b
c
D & E
D1 & E1
D2 & E2
e
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
L
0.45
0°
0.75
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
ICS8624BY REVISION F OCTOBER 22, 2013
16
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Ordering Information
Table 10. Ordering Information
Part/Order Number
8624BY
8624BYT
8624BYLF
8624BYLFT
Marking
ICS8624BY
ICS8624BY
ICS8624BYLF
ICS8624BYLF
Package
32 Lead LQFP
32 Lead LQFP
Shipping Packaging
Tray
1000 Tape & Reel
Tray
Temperature
0C to 70C
0C to 70C
0C to 70C
0C to 70C
“Lead-Free” 32 Lead LQFP
“Lead-Free” 32 Lead LQFP
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product
for use in life support devices or critical medical instruments.
ICS8624BY REVISION F OCTOBER 22, 2013
17
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
8
Switched labels on Figure 8, odc & tPERIOD diagram.
A
10/30/01
10/31/01
8/13/02
10
Revised label on Figure 11 to read ICS8624 LVHSTL... from ICS8634 LVDS...
A
1
Revised Block Diagram.
7 - 8
Updated Phase Jitter Diagram and Output Rise & Fall Time Diagram.
Revised Figures 3A & 3B.
A
11 - 12
T1
2
4
Pin Description table - revised MR & VDD descriptions.
T4A
Power Supply table - revised VDD parameter description to correspond with the Pin
Description table.
B
C
2/12/03
2/19/04
T4C
4
9
Differential DC Charc. table - changed VPP limit from 0.15V minimum to 0.1V minimum.
Revised Single Ended Signal diagram.
Updated format.
T2
3
4
5
5
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings - updated Output rating.
T4D
T6B
HSTL DC Characteristics Table - changed VOX to 40% min. - 60% max. and added note.
Added Table 6B AC Characteristics Table with VDD = VDDA = 3.3V 10%.
Changed LVHSTL to HSTL throughout the data sheet.
8
Added Differential Clock Input Interface section.
C
D
6/15/04
6/27/05
T10
T6A
14
Added ""Lead Free"" part number to Ordering Information table.
5
AC Characteristics Table -adjusted TPD spec from 3.4ns Min. to 3.2ns Min. and deleted
the typical spec.
T10
T4A
14
4
Ordering Information Table - added Lead-Free note.
Power Supply DC Characteristics Table - changed VDDO min. from 1.6V to 1.5V. Updated
Table Header to match change.
T4C
T6A
T6C
5
6
Differential DC Characteristics Table - updated NOTES 1 & 2.
Added Thermal note.
6
Added 1.5V to 1.6V AC Characteristics Table.
E
F
10/6/09
9
Added Recommendations for Unused Input & Output Pins section.
Updated Differential Clock Input Interface section.
Power Considerations - updated Power Dissipation calculation.
Ordering Information Table - deleted “ICS” prefix from Part/Order Number column.
Converted datasheet format.
10
13
17
T10
1
Added NRND - Not Recommended for New Designs
10/22/13
ICS8624BY REVISION F OCTOBER 22, 2013
18
©2013 Integrated Device Technology, Inc.
ICS8624 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
San Jose, California 95138
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any
license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT
product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third
party owners.
Copyright 2013. All rights reserved.
相关型号：
8624BYT
PLL Based Clock Driver, 8624 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBA, LQFP-32
IDT
©2020 ICPDF网 联系我们和版权申明