87004AG-03T [IDT]
Clock Driver, PDSO20;
| 型号： | 87004AG-03T |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, PDSO20 光电二极管 |
| 文件： | 总13页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
ICS87004-03
GENERAL DESCRIPTION
FEATURES
The ICS87004-03 is a low skew, ÷1, ÷2 ÷3, ÷4
• Two banks of two LVCMOS/LVTTL outputs,
ICS
HiPerClockS™
÷5, ÷6 ÷8, ÷16 LVCMOS/LVTTL Fanout Buffer/
Divider and a member of theHiPerClockS™ family
of High Performance Clock Solutions from IDT. The
ICS87004-03 has selectable clock inputs that
15Ω typical output impedance
• Selectable LVCMOS/LVTTL clock inputs
• LVCMOS_CLK supports the following input types: LVCMOS,
LVTTL
accept single ended input levels. Output enable pin controls
whether the output is in the active or high impedance state.
•
•
•
•
Maximum output frequency: 200MHz
Output skew: 100ps (typical)
Bank skew: 50ps (typical)
The ICS87004-03 is characterized at 3.3V, 2.5V and mixed 3.3V/
2.5V, 3.3V/1.8V, 2.5V/1.8V input/output supply operating
modes.Guaranteed bank, output, and part-to-part skew
characteristics make the ICS87004-03 ideal for those
applications demanding well defined performance and
repeatability.
Part-to-part skew: TBD
• Power supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
Pullup
OEA
3
Pulldown
NA2:NA0
N Output Divider
NA2:NA0
PIN ASSIGNMENT
0 0 0 ÷1 (default)
VDD
NA2
NA1
NA0
OEA
VDDOA
QA0
QA1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
0 0 1 ÷2
QA0
0 1 0 ÷3
0 1 1 ÷4
Pulldown
CLK_SEL
QA1
1 0 0 ÷5
1 0 1 ÷6
CLK0
CLK_SEL
CLK1
GND
QB1
QB0
VDD0A
1 1 0 ÷8
Pulldown
Pulldown
CLK0
CLK1
0
1
1 1 1 ÷16
VDDOB
NB2
NB1
NB0
GND
OEB
N Output Divider
NB2:NB0
VDD0B
0 0 0 ÷1 (default)
0 0 1 ÷2
ICS87004-03
20-Lead TSSOP
6.50mm x 4.40mm x 0.92mm package body
G Package
QB0
QB1
0 1 0 ÷3
0 1 1 ÷4
1 0 0 ÷5
1 0 1 ÷6
Top View
1 1 0 ÷8
1 1 1 ÷16
3
Pulldown
NB2:NB0
OEB
Pullup
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
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ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDD
Power
Input
Input
Input
Power supply pin.
N divider pins for Bank A outputs.
LVCMOS / LVTTL interface levels.
2, 3, 4
5, 7
6
NA2, NA1, NA0
CLK0, CLK1
CLK_SEL
Pulldown
Pulldown LVCMOS / LVTTL clock inputs.
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.
N divider pins for Bank B outputs.
LVCMOS / LVTTL interface levels.
Output enable. When LOW, Bank B outputs are in HIGH
impedance state. When HIGH, Bank B outputs are active.
LVCMOS / LVTTL interface levels.
Pulldown
Pulldown
8, 9, 10
11
NB2, NB1, NB0
OEB
Input
Input
Pullup
12, 16
13
GND
VDDOB
Power
Power
Output
Output
Power
Power supply ground.
Output supply pin for Bank B outputs.
Bank B clock outputs. LVCMOS / LVTTL interface levels.
Bank A clock outputs. LVCMOS / LVTTL interface levels.
Bank A output supply pin.
14, 15
17, 18
19
QB0, QB1
QA1, QA0
VDDOA
Output enable. When LOW, Bank A outputs are in HIGH
impedance state. When HIGH, Bank A outputs are active.
LVCMOS / LVTTL interface levels.
20
OEA
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Units
pF
Symbol Parameter
Test Conditions
Minimum Typical Maximum
CIN
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
Power Dissipation Capacitance
(per output)
CPD
TBD
15
pF
ROUT
Output Impedance
Ω
TABLE 3. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
Minimum Maximum
N2
0
N1
0
N0
0
N Divider Value
÷1 (default)
0
0
1
÷2
÷3
0
1
0
0
1
1
÷4
1
0
0
÷5
1
0
1
÷6
1
1
0
÷8
1
1
1
÷16
NOTE: Some combinations of Bank A and Bank B output divider selections
are not synchronous.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
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ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 93.1°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Power Supply Voltage
3.135
3.135
3.3
3.3
40
1
3.465
3.465
V
V
DDOA, VDDOB Output Supply Voltage
V
IDD
Power Supply Current
Output Supply Current
mA
mA
IDDOA, IDDOB
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDOA = VDDOB = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Power Supply Voltage
3.135
2.375
3.3
2.5
40
1
3.465
2.625
V
V
DDOA, VDDOB Output Supply Voltage
V
IDD
Power Supply Current
Output Supply Current
mA
mA
I
DDOA, IDDOB
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDOA = VDDOB = 1.8V 0.15V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Power Supply Voltage
3.135
1.65
3.3
1.8
40
1
3.465
1.95
V
VDDOA, VDDOB Output Supply Voltage
V
IDD
Power Supply Current
Output Supply Current
mA
mA
IDDOA, IDDOB
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDOA = VDDOB = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Power Supply Voltage
2.375
2.375
2.5
2.5
39
1
2.625
2.625
V
VDDOA, VDDOB Output Supply Voltage
V
IDD
Power Supply Current
Output Supply Current
mA
mA
I
DDOA, IDDOB
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5ꢀ, VDDOA = VDDOB = 1.8V 0.15V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Power Supply Voltage
2.375
1.65
2.5
1.8
39
1
2.625
1.95
V
V
DDOA, VDDOB Output Supply Voltage
V
IDD
Power Supply Current
Output Supply Current
mA
mA
I
DDOA, IDDOB
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
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ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ OR 2.5V 5ꢀVDDOA = VDDOB = 3.3V 5ꢀ, 2.5V 5ꢀ OR
1.8V 0.15V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
VDD = 2.5V
1.7
-0.3
-0.3
VDD = 3.3V
Input Low Voltage
CLK0, CLK1, CLK_SEL,
VDD = 2.5V
VDD = VIN = 3.465V
0.7
150
5
µA
µA
µA
NA2:NA0, NB2:NB0
or 2.625V
VDD = VIN = 3.465V
Input
High Current
IIH
OEA, OEB
or 2.625V
VDD = 3.465V or 2.625V,
VIN = 0V
CLK0, CLK1, CLK_SEL,
NA2:NA0, NB2:NB0
-5
Input
Low Current
IIL
VDD = 3.465V or 2.625V,
OEA, OEB
-150
µA
V
IN = 0V
DDOX = 3.3V 5ꢀ
VDDOX = 2.5V 5ꢀ
V
2.6
1.8
1.5
V
V
VOH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
DDOX = 1.8V 0.15V
V
VDDOX = 3.3V 5ꢀ
0.5
0.5
0.4
V
VOL
V
DDOX = 2.5V 5ꢀ
V
VDDOX = 1.8V 0.15V
V
IOZL
IOZH
Output Hi-Z Current Low
Output Hi-Z Current High
-5
µA
µA
5
NOTE 1: Outputs terminated with 50Ω to VDDOX/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDOA = VDDOB = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
200
MHz
ns
ps
ps
ps
ps
ꢀ
tPD
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Bank Skew; NOTE 3, 5
4.5
100
TBD
50
tsk(o)
tsk(pp)
tsk(b)
tR / tF
odc
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
20ꢀ to 80ꢀ
800
50
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
5
5
ns
ns
tDIS
All parameters measured at ƒ ≤ TBDMHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDOX/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOX/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE: 5 Defined as skew within a bank with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
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ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDOA = VDDOB = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
200
MHz
ns
ps
ps
ps
ps
ꢀ
tPD
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Bank Skew; NOTE 3, 5
4.5
100
TBD
50
tsk(o)
tsk(pp)
tsk(b)
tR / tF
odc
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
20ꢀ to 80ꢀ
850
50
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
5
5
ns
ns
tDIS
All parameters measured at ƒ ≤ TBDMHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDOX/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOX/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE: 5 Defined as skew within a bank with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDOA = VDDOB = 1.8V 0.15V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
200
MHz
ns
ps
ps
ps
ps
ꢀ
tPD
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Bank Skew; NOTE 3, 5
4.5
100
TBD
50
tsk(o)
tsk(pp)
tsk(b)
tR / tF
odc
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
20ꢀ to 80ꢀ
900
50
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
5
5
ns
ns
tDIS
All parameters measured at ƒ ≤ TBDMHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDOX/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOX/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE: 5 Defined as skew within a bank with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
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ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
TABLE 5D. AC CHARACTERISTICS, VDD = VDDOA = VDDOB = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
200
MHz
ns
ps
ps
ps
ps
ꢀ
tPD
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Bank Skew; NOTE 3, 5
4.5
100
TBD
50
tsk(o)
tsk(pp)
tsk(b)
tR / tF
odc
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
20ꢀ to 80ꢀ
950
50
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
5
5
ns
ns
tDIS
All parameters measured at ƒ ≤ TBDMHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDOX/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOX/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE: 5 Defined as skew within a bank with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V 5ꢀ, VDDOA = VDDOB = 1.8V 0.15V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
200
MHz
ns
ps
ps
ps
ps
ꢀ
tPD
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Bank Skew; NOTE 3, 5
4.5
100
TBD
50
tsk(o)
tsk(pp)
tsk(b)
tR / tF
odc
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
20ꢀ to 80ꢀ
1000
50
tEN
Output Enable Time; NOTE 6
Output Disable Time; NOTE 6
5
5
ns
ns
tDIS
All parameters measured at ƒ ≤ TBDMHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDOX/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDOX/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDOX/2.
NOTE: 5 Defined as skew within a bank with equal load conditions.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
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ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2.05V 5ꢀ
1.25V 5ꢀ
SCOPE
VDD,
VDDOA,
VDDOB
SCOPE
VDD
Qx
VDDOA,
VDDOB
Qx
LVCMOS
GND
GND
LVCMOS
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/ 2.5V OUTPUT LOAD AC TEST CIRCUIT
2.4V 0.09V
0.9V 0.075V
PART 1
Qx
VDDOX
2
SCOPE
VDD
VDDOA,
VDDOB
Qx
PART 2
Qy
VDDOX
GND
GND
LVCMOS
2
tsk(pp)
-0.9V 0.075V
3.3V CORE/ 1.8V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
VDDOX
2
VDDOX
QX0, QX1
QX0, QX1
Qx
Qy
2
VDDOX
2
VDDOX
2
tsk(o)
tsk(b)
OUTPUT SKEW
BANK SKEW
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
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ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
VDD
80ꢀ
80ꢀ
tR
2
CLK0,
CLK1
20ꢀ
20ꢀ
Clock
Outputs
VDDOX
tF
2
QA0,QA1
QB0,QB1
t
PD
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
VDDOX
2
QA0,QA1
QB0,QB1
tPW
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
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LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
LVCMOS OUTPUT:
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
All unused LVCMOS output can be left floating. There should
be no trace attached.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 6. θ VS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
88.7°C/W
500
86.6°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
93.1°C/W
TRANSISTOR COUNT
The transistor count for ICS87004-03 is: 2781
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
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ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
MAX
N
A
20
--
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
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LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS87004AG-03
Marking
ICS87004AG03
ICS87004AG03
TBD
Package
Shipping Packaging Temperature
20 Lead TSSOP
tube
0°C to 70°C
ICS87004AG-03T
ICS87004AG-03LF
ICS87004AG-03LFT
20 Lead TSSOP
2500 tape & reel
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
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ICS87004AG-03 REV. B FEBRUARY 5, 2007
ICS87004-03
LVCMOS/LVTTL FANOUT BUFFER/DIVIDER
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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