8702BY [IDT]
Clock Driver, 8702 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48;
| 型号： | 8702BY |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, 8702 Series, 20 True Output(s), 0 Inverted Output(s), PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, LQFP-48 驱动 输出元件 逻辑集成电路 |
| 文件： | 总14页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8702
LOW SKEW, ÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8702 is a low skew, ÷1, ÷2 Differential-to-LVCMOS • Twenty LVCMOS outputs, 7Ω typical output impedance
Clock Generator. The ICS8702 is designed to translate any
differential signal levels to LVCMOS/LVTTL levels. True or
• One differential clock input pair
inverting, single-ended to LVCMOS translation can be
achieved with a resistor bias on the nCLK or CLK inputs,
respectively. The effective fan-out can be increased from 20
to 40 by utilizing the ability of the outputs to drive two series
terminated lines.
• CLK, nCLK supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Maximum output frequency: 250MHz
• Translates any differential input signal (LVPECL, LVHSTL,
LVDS) to LVCMOS levels without external bias networks
The divide select inputs, DIV_SELx, control the output
frequency of each bank. The outputs can be utilized in the
÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank
enable inputs, BANK_EN0:1, supports enabling and
disabling each bank of outputs individually. The master reset
input, nMR/OE, resets the internal frequency dividers and
also controls the enabling and disabling of all outputs
simultaneously.
• Translates any single-ended input signal to LVCMOS levels
with a resistor bias on nCLK input
• Bank enable logic allows unused banks to be disabled in
reduced fanout applications
•
•
•
•
Output skew: 200ps (maximum)
Bank skew: 150ps (maximum)
The ICS8702 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output, multiple frequency and part-to-part skew
characteristics make the ICS8702 ideal for those clock
dis-tribution applications demanding well defined performance
and repeatability.
Part-to-part skew: 650ps (maximum)
Multiple frequency skew: 250ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK
nCLK
÷1
÷2
1
0
QA0:QA4
QB0:QB4
QC0:QC4
QD0:QD4
48 47 46 45 44 43 42 41 40 39 38 37
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
1
36
35
34
33
32
31
30
29
28
27
26
25
QB1
VDDO
QB0
QA4
VDDO
QA3
GND
QA2
GND
QA1
VDDO
QA0
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
2
1
0
3
4
5
6
ICS8702
7
1
0
8
9
10
11
12
1
0
13 14 15 16 17 18 19 20 21 22 23 24
nMR/OE
BANK_EN0
BANK_EN1
Bank Enable
Logic
48-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
8702BY
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REV. E JULY 25, 2010
1
ICS8702
LOW SKEW,
÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Description
Number
Name
Type
2, 5, 11, 26,
32, 35, 41, 44
VDDO
Power
Power
Output supply pins.
7, 9, 18,
28, 30, 37,
39, 46, 48
16, 20
25, 27, 29,
31, 33
GND
VDD
QA0, QA1, QA2,
QA3, QA4
Output power supply.
Positive supply pins.
Bank A outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
Power
Output
34, 36, 38,
40, 42
43, 45, 47,
1, 3
4, 6, 8,
10, 12
QB0, QB1, QB2,
QB3, QB4
QC0, QC1, QC2,
QC3, QC4
QD0, QD1, QD2,
QD3, QD4
Bank B outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
Bank C outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
Bank D outputs. 7Ω typical output impedance.
LVCMOS/LVTTL interface levels.
Output
Output
Output
22
21
CLK
Input Pulldown Non-inverting differential clock input.
nCLK
Input
Pullup
Inverting differential clock input.
Controls frequency division for Bank D outputs.
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank C outputs.
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank B outputs
LVCMOS/LVTTL interface levels.
Controls frequency division for Bank A outputs.
LVCMOS/LVTTL interface levels.
13
14
DIV_SELD
DIV_SELC
DIV_SELB
DIV_SELA
Input
Pullup
Input
Input
Input
Input
Pullup
Pullup
Pullup
Pullup
23
24
BANK_EN1,
BANK_EN0
Enables and disables outputs by banks.
LVCMOS/LVTTL interface levels.
17, 19
Master Reset and output enable. When HIGH, output drivers are
enabled. When LOW, output drivers are in HiZ and dividers are
reset. LVCMOS/LVTTL interface levels.
15
nMR/OE
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
Power Dissipation Capacitance
(per output)
CPD
VDD = VDDO = 3.465V
15
pF
ROUT
Output Impedance
7
Ω
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ICS8702
LOW SKEW, ÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
Outputs
nMR/OE BANK_EN1 BANK_EN0 DIV_SELx QA0:QA4
QB0:QB4
Hi Z
QC0:QC4
Hi Z
QD0:QD4 Qx Frequency
0
1
1
1
1
1
1
1
1
X
0
1
0
1
0
1
0
1
X
0
0
1
1
0
0
1
1
X
0
0
0
0
1
1
1
1
Hi Z
Hi Z
Hi Z
zero
fIN/2
fIN/2
fIN/2
fIN/2
fIN
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Hi Z
Hi Z
Enabled
Enabled
Enabled
Hi Z
Hi Z
Hi Z
Enabled
Enabled
Hi Z
Hi Z
Enabled
Hi Z
Enabled
Enabled
Enabled
Hi Z
Hi Z
fIN
Enabled
Enabled
Hi Z
fIN
Enabled
fIN
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
nMR/OE
CLK
nCLK
Qx0:Qx4
LOW
1
1
1
1
1
1
0
1
Differential to Single Ended
Differential to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section, which discusses "Wiring the Differential Input to Accept
Single Ended Levels".
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ICS8702
LOW SKEW, ÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
Supply Voltage, V
4.6V
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
I
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
Outputs, VO
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA =0°C TO 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum Typical Maximum Units
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
3.135
3.135
3.3
3.3
3.465
3.465
95
V
V
VDDO
IDD
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol
VDD
Parameter
Test Conditions
Minimum Typical Maximum Units
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
3.135
2.375
3.3
2.5
3.465
2.625
95
V
V
VDDO
IDD
mA
TABLE 4C. LVCMOS /LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA =0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
Input
VIH
2
VDD + 0.3
V
V
High Voltage
Input
VIL
-0.3
0.8
5
Low Voltage
Input
IIH
VDD = V = 3.465V
µA
µA
IN
High Current
Input
IIL
VDD = 3.465V, V = 0V
-150
2.6
IN
Low Current
V
DD = VDDO = 3.135V
IOH = -36mA
VOH
VOL
Output High Voltage
Output Low Voltage
V
V
VDD = VDDO = 3.135V
IOL = 36mA
0.5
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REV. E JULY 25, 2010
4
ICS8702
LOW SKEW,
÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
BANK_EN0, BANK_EN1,
nMR/OE
Input
VIH
2
VDD + 0.3
V
V
High Voltage
Input
VIL
-0.3
0.8
5
Low Voltage
Input
IIH
VDD = V = 3.465V
µA
µA
IN
High Current
Input
IIL
VDD = 3.465V, V = 0V
-150
1.9
IN
Low Current
VDD = 3.135V
VOH
Output High Voltage
V
DDO = 2.375V
V
V
IOL = -27mA
VDD = 3.135V
VOL
Output Low Voltage
V
DDO = 2.375V
IOL = 27mA
0.5
TABLE 4E. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA =0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK
VDD = VIN = 3.465V
150
5
µA
µA
µA
µA
V
IIH
Input High Current
nCLK
CLK
V
DD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
nCLK
V
-150
0.15
1.8
VPP
VCMR
Peak-to-Peak Input Voltage
1.3
2.4
1.3
V
Common Mode Input Voltage;
NOTE 1, 2
DCM, LVHSTL, LVDS, SSTL Levels
0.31
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
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ICS8702
LOW SKEW,
÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA =0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
250
3.5
MHz
ns
tPD
Propagation Delay; NOTE 1
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
f ≤ 200MHz
2.2
tsk(b)
tsk(o)
Measured on rising edge atVDDO/2
Measured on rising edge atVDDO/2
150
200
ps
ps
Multiple Frequency Skew;
NOTE 4, 7
tsk(w)
Measured on rising edge atVDDO/2
250
ps
tsk(pp)
Part-to-Part Skew; NOTE 5, 7 Measured on rising edge atVDDO/2
650
850
850
ps
ps
ps
tR
tF
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
30ꢀ to 70ꢀ
30ꢀ to 70ꢀ
280
280
tCYCLE/2
- 0.5
tCYCLE/2
+ 0.5
f ≤ 200MHz
f = 200MHz
f = 10MHz
tCYCLE/2
2.5
ns
ns
ns
odc
Output Duty Cycle
2
3
Output Enable Time;
NOTE 6
tEN
6
Output Disable Time;
NOTE 6
tDIS
f = 10MHz
6
ns
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages
and equal load conditions.
NOTE 5: Defined as the skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8702
LOW SKEW,
÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
250
3.6
MHz
ns
tPD
Propagation Delay; NOTE 1
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
f ≤ 200MHz
2.3
tsk(b)
tsk(o)
Measured on rising edge atVDDO/2
Measured on rising edge atVDDO/2
150
200
ps
ps
Multiple Frequency Skew;
NOTE 4, 7
tsk(w)
Measured on rising edge atVDDO/2
250
ps
tsk(pp)
Part-to-Part Skew; NOTE 5, 7 Measured on rising edge atVDDO/2
700
850
850
ps
ps
ps
tR
tF
Output Rise Time; NOTE 6
Output Fall Time; NOTE 6
30ꢀ to 70ꢀ
30ꢀ to 70ꢀ
280
280
tCYCLE/2
- 0.5
tCYCLE/2
+ 0.5
f ≤ 200MHz
f = 200MHz
f = 10MHz
tCYCLE/2
2.5
ns
ns
ns
odc
Output Duty Cycle
2
3
Output Enable Time;
NOTE 6
tEN
6
Output Disable Time;
NOTE 6
tDIS
f = 10MHz
6
ns
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew across banks of outputs operating at different frequency with the same supply voltages
and equal load conditions.
NOTE 5: Defined as the skew between outputs on different devices operating at the same supply voltages and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8702
LOW SKEW,
÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD,
VDDO
VDD,
VDDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.165V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
VDDO
Qx
Qy
2
nCLK
VPP
VCMR
Cross Points
VDDO
2
CLK
tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
Part 1
VDDO
nCLK
CLK
Qx
2
Part 2
Qy
VDDO
VDDO
2
QA0:QA4,
QB0:QB4,
QC0:QC4,
QD0:QD4
2
t
tsk(pp)
PD
PART-TO-PART SKEW
PROPAGATION DELAY
VDDO
2
VDDO
VDDO
70ꢀ
tF
70ꢀ
tR
2
2
QA0:QA4,
QB0:QB4,
QC0:QC4,
QD0:QD4
tPW
30ꢀ
30ꢀ
Clock
Outputs
tPERIOD
tPW
tPERIOD
odc =
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIIOD
OUTPUT RISE/FALL TIME
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ICS8702
LOW SKEW, ÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V and VDD = 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUT:
LVCMOS OUTPUT:
For applications not requiring the use of the differential input, All unused LVCMOS output can be left floating. We
both CLK and nCLK can be left floating. Though not required, recommend that there is no trace attached.
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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ICS8702
LOW SKEW,
÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
POWER CONSIDERATIONS
For Power Dissipation, please refer to a separate Application Note: Power Dissipation for LVCMOS Buffer.
DRIVER TERMINATION
For LVCMOS Output Termination, please refer to a separate Application Note: LVCMOS Driver Termination.
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 48 LQFP
θJA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8702 is: 1746
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10
ICS8702
LOW SKEW,
÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX FOR 48 LQFP
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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ICS8702
LOW SKEW, ÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
Shipping
Packaging
Marking
Package
Temperature
8702BY
8702BYT
ICS8702BY
ICS8702BY
48 Lead LQFP
48 Lead LQFP
tray
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
1000 tape & reel
tray
8702BYLF
8702BYLFT
ICS8702BYLF
ICS8702BYLF
48 Lead "Lead-Free" LQFP
48 Lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS
compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
8702BY
www.idt.com
REV. E JULY 25, 2010
12
ICS8702
LOW SKEW, ÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
4A
4
Revised IDD row from 70mA Maximum to 95mA Maximum.
B
8/2/01
4D
4B
6
4
Revised IDD row from 70mA Maximum to 95mA Maximum.
Revised VIH row from 3.8 Maximum to VDD + 0.3 Maximum.
C
C
4E
6
Revised VIH row from 3.8 Maximum to VDD + 0.3 Maximum.
11/28/01
8/21/02
11
2
Added Power Dissipation and Driver Termination notes.
Pin Description Table revised nMR/OE description.
Updated Output Rise/Fall Time Diagram.
1
10
Format changes.
1
2
Features Section added Lead-Free bullet.
Pin Characteristics Table - changed CIN 4pF max to 4pF typical.
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free part number, marking, and note.
T2
T9
D
E
1/17/06
7/25/10
9
12
Updated datasheet layout.
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
12
14
8702BY
www.idt.com
REV. E JULY 25, 2010
13
ICS8702
LOW SKEW,
÷1, ÷2
DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
8702BY
www.idt.com
REV. E JULY 25, 2010
14
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