871002AGI-02 [IDT]
Differential-to-0.7V HCSL Differential PCI EXPRESS⢠Jitter Attenuator; 差分至0.7V HCSL差分PCI EXPRESSâ ?? ¢抖动衰减器
| 型号： | 871002AGI-02 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Differential-to-0.7V HCSL Differential PCI EXPRESS⢠Jitter Attenuator |
| 文件： | 总16页 (文件大小：795K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Differential-to-0.7V HCSL Differential
PCI EXPRESS™ Jitter Attenuator
ICS871002I-02
DATA SHEET
General Description
Features
The ICS871002I-02 is a high performance Jitter
Attenuator designed for use in PCI Express™systems.
In some PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are generated
from a low bandwidth, high phase noise PLL frequency
• Two 0.7V HCSL differential output pairs
• One differential clock input
S
IC
HiPerClockS™
• CLK, nCLK can accept the following differential input levels:
LVPECL, LVDS, HSTL, HCSL, SSTL
• Input frequency range: 98MHz to 128MHz
• Output frequency range: 98MHz to 640MHz
• VCO range: 490MHz - 640MHz
synthesizer. In these systems, a jitter attenuator may be required to
attenuate high frequency random and deterministic jitter components
from the PLL synthesizer and from the system board. The
ICS871002I-02 has two PLL bandwidth modes: 350kHz and
2200kHz. The 350kHz mode provides the maximum jitter
attenuation, but it also results in higher PLL tracking time. In this
mode, the spread spectrum modulation may also be attenuated. The
2200kHz bandwidth provides the best tracking skew and will pass
most spread profiles, but the jitter attenuation will not be as good as
the lower bandwidth modes. The ICS871002I-02 can be set for
different modes using the F_SELx pins as shown in Table 3C.
• Cycle-to-cycle jitter: 45ps (maximum)
• Two bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
The ICS871002I-02 uses IDT 3rd Generation FemtoClockTM PLL
technology to achieve the lowest possible phase noise. The
device is packaged in a small 20 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI Express
add-in cards.
PLL Bandwidth (typical) Table
BW_SEL
0 = PLL Bandwidth: ~350kHz (default)
1 = PLL Bandwidth: ~2200kHz
Block Diagram
IREF
Pullup
OE
2
Pullup:Pulldown
F_SEL[1:0]
Pin Assignment
Pulldown
BW_SEL
nQ0
IREF
1
2
20 Q0
0 = 350kHz
1 = 2200kHz
Output Divider
00 ÷5
01 ÷4
10 ÷2 (default)
11 ÷1
Q0
19
VDD
FB_OUT
nFB_OUT
3
4
18
17
Q1
nQ1
nQ0
Pulldown
CLK
MR
BW_SEL
F_SEL1
5
6
7
8
9
16 nFB_IN
Phase
Detector
VCO
15
14
13
FB_IN
GND
nCLK
Pullup
nCLK
490 - 640 MHz
Q1
VDDA
F_SEL0
12 CLK
11
OE
nQ1
VDD 10
Pulldown
Pullup
FB_IN
nFB_IN
ICS871002I-02
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
÷5 (fixed)
FB_OUT
nFB_OU
G Package
Top View
Pulldown
MR
ICS871002AGI-02 REVISION A APRIL 14, 2010
1
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 20
nQ0, nQ0
Output
Input
Differential output pair. HCSL interface levels.
A fixed precision resistor (475Ω) from this pin to ground provides a reference
current used for differential current-mode Qx/nQx clock outputs.
2
IREF
3,
4
FB_OUT,
nFB_OUT
Output
Input
Differential feedback output pair. HCSL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs (Qx, FB_OUT) to go low and the inverted outputs (nQx,
nFB_OUT) to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
5
MR
Pulldown
6
BW_SEL
Input
Input
Pulldown
PLL Bandwidth select input. 0 = 350kHz, 1 = 2200kHz. See Table 3B.
7,
9
F_SEL1,
F_SEL0
Pullup
Pulldown
Frequency select pins. See Table 3C. LVCMOS/LVTTL interface levels
8
VDDA
VDD
Power
Power
Analog supply pin.
Core supply pins.
10, 19
Output enable pin. When HIGH, the outputs are active. When LOW, the outputs are
in a high impedance state. LVCMOS/LVTTL interface levels. See Table 3A.
11
OE
Input
Pullup
12
13
CLK
nCLK
Input
Input
Pulldown
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
14
GND
Power
Input
Power supply ground.
15
FB_IN
nFB_IN
nQ1, Q1
Pulldown
Pullup
Non-inverting differential feedback clock input.
Inverting differential feedback clock input.
Differential output pair. HCSL interface levels.
16
Input
17, 18
Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
ICS871002AGI-02 REVISION A APRIL 14, 2010
2
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Function Tables
Table 3A. Output Enable Function Table
Input
OE
Outputs
FB_OUT, nFB_OUT
Q[1:0], nQ[1:0]
High-Impedance
Enabled
0
Enabled
Enabled
1 (default)
Table 3B. PLL Bandwidth Control Table
Input
BW_SEL
PLL Bandwidth
350kHz (default)
2200kHz
0
1
Table 3C. F_SELx Function Table
Input Frequency
Inputs
Output Frequency
(MHz)
(MHz)
F_SEL1
F_SEL0
Divider
÷5
100
0
0
1
1
0
1
0
1
100
125
100
÷4
100
÷2
250 (default)
500
100
÷1
ICS871002AGI-02 REVISION A APRIL 14, 2010
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©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
86.7°C/W (0 mps)
-65°C to 150°C
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, VDD = 3.3V 10%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
2.97
Typical
3.3
Maximum
3.63
VDD
Units
V
VDD
VDDA
IDD
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
VDD – 0.12
3.3
V
75
mA
mA
IDDA
12
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 10%, TA = -40°C to 85°C
Symbol
VIH
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
V
Input High Voltage
Input Low Voltage
2
VDD + 0.3
VIL
-0.3
0.8
5
V
OE, F_SEL1
VDD = VIN = 3.63V
VDD = VIN = 3.63V
µA
IIH
Input High Current
Input Low Current
BW_SEL,
F_SEL0, MR
150
µA
µA
µA
OE, F_SEL1
VDD = 3.63V, VIN = 0V
VDD = 3.63V, VIN = 0V
-150
-5
IIL
BW_SEL,
F_SEL0, MR
Table 4C. Differential DC Characteristics, VDD = 3.3V 10%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
µA
µA
µA
µA
V
CLK, FB_IN
VDD = VIN = 3.465V
150
5
IIH Input High Current
nCLK, nFB_IN
CLK, FB_IN
VDD = VIN = 3.465V
V
DD = 3.465V, VIN = 0V
-5
-150
IIL
Input Low Current
nCLK, nFB_IN
VDD = 3.465V, VIN = 0V
VPP
Peak-to-Peak Voltage; NOTE 1
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as VIH.
ICS871002AGI-02 REVISION A APRIL 14, 2010
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©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Table 5. 0.7V HCSL Differential AC Characteristics, VDD = 3.3V 10%, TA = -40°C to 85°C
Symbol
fMAX
Parameter
Test Conditions
Minimum
Typical
Maximum
640
Units
MHz
ps
Output Frequency
Cycle-to-Cycle Jitter; NOTE 1
98
tjit(cc)
PLL Mode
45
Absolute Max. Output Voltage;
NOTE 2, 3
VMAX
1150
mV
Absolute Min. Output Voltage;
NOTE 2, 4
VMIN
-300
-100
200
mV
mV
mV
VRB
Ringback Voltage; NOTE 5, 6
100
550
Absolute Crossing Voltage;
NOTE 2, 7, 8
VCROSS
Total Variation of VCROSS over
all edges; NOTE 2, 7, 9
∆VCROSS
140
mV
tR / tF
odc
Output Rise/Fall Time
measured between -150mV to +150mV
0.6
48
4.75
52
V/ns
%
Output Duty Cycle; NOTE 10
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at f ≤ 250MHz unless noted otherwise.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Measurement taken from single ended waveform.
NOTE 3: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 4: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 5: Measurement taken from differential waveform.
NOTE 6:TSTABLE is the time the differential clock must maintain a minimum 150mV differential voltage after rising/falling edges before it is
allowed to drop back into the VRB 100mV differential range.
NOTE 7: Measured at crossing point where the instantaneous voltage value of the rising edge of Q equals the falling edge of nQ.
NOTE 8: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
NOTE 9: Defined as the total variation of all crossing voltages of rising Q and falling nQ, This is the maximum allowed variance in Vcross for
any particular system.
NOTE 10: Input duty cycle must be 50%.
ICS871002AGI-02 REVISION A APRIL 14, 2010
5
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Parameter Measurement Information
3.3V 10%
3.3V 10%
3.3V 10%
3.3V 10%
SCOPE
50Ω
V
Measurement
DD
50Ω
50Ω
V
33Ω
33Ω
Point
DD
V
DDA
V
DDA
HCSL
49.9Ω
49.9Ω
2pF
HCSL
50Ω
Measurement
Point
IREF
IREF
GND
0V
475Ω
GND
0V
2pF
475Ω
This load condition is used for IDD and tjit(cc) measurements.
3.3V HCSL Output Load AC Test Circuit
3.3V HCSL Output Load AC Test Circuit
V
nQ[0:1],
DD
nFB_OUT
nCLK,
Q[0:1],
nFB_IN
FB_OUT
VPP
VCMR
Cross Points
➤
➤
tcycle n
tcycle n+1
➤
➤
CLK,
FB_IN
tjit(cc) = tcycle n – tcycle n+1
|
|
1000 Cycles
GND
Differential Input Level
Cycle-to-Cycle Jitter
T
STABLE
Clock Period (Differential)
V
RB
Positive Duty
Cycle (Differential)
Negative Duty
Cycle (Differential)
+150mV
RB = +100mV
0.0V
V
VRB = -100mV
-150mV
0.0V
Q - nQ
V
RB
Q - nQ
T
STABLE
Differential Measurement Points for Duty Cycle/Period
Differential Measurement Points for Ringback
ICS871002AGI-02 REVISION A APRIL 14, 2010
6
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Parameter Measurement Information, continued
V
MAX = 1.15V
nQ
nQ
VCROSS_MAX = 550mV
VCROSS_DELTA = 140mV
V
CROSS_MIN = 250mV
Q
Q
V
MIN = -0.30V
Single-ended Measurement Points for Absolute Cross
Point and Swing
Single-ended Measurement Points for Delta Cross Point
Rise Edge Rate
Fall Edge Rate
+150mV
0.0V
-150mV
Q - nQ
Output Rise/Fall Time
ICS871002AGI-02 REVISION A APRIL 14, 2010
7
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS871002I-02 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD and VDDA should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic VDD pin and also shows that VDDA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single-Ended Levels
Figure 2 shows how a differential input can be wired to accept single
ended levels. The reference voltage VREF = VDD/2 is generated by
the bias resistors R1 and R2. The bypass capacitor (C1) is used to
help filter noise on the DC bias. This bias circuit should be located as
close to the input pin as possible. The ratio of R1 and R2 might need
to be adjusted to position the VREF in the center of the input voltage
swing. For example, if the input clock swing is 2.5V and VDD = 3.3V,
R1 and R2 value should be adjusted to set VREF at 1.25V. The values
below are for when both the single ended swing and VDD are at the
same voltage. This configuration requires that the sum of the output
impedance of the driver (Ro) and the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the input will attenuate the signal in half. This can be done in one of
two ways. First, R3 and R4 in parallel should equal the transmission
line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.
The values of the resistors can be increased to reduce the loading for
slower and weaker LVCMOS driver. When using single-ended
signaling, the noise rejection benefits of differential signaling are
reduced. Even though the differential input can handle full rail
LVCMOS signaling, it is recommended that the amplitude be
reduced. The datasheet specifies a lower differential amplitude,
however this only applies to differential signals. For single-ended
applications, the swing can be larger, however VIL cannot be less
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
of the recommended components might not be used, the pads
should be placed in the layout. They can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a differential signal.
Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels
ICS871002AGI-02 REVISION A APRIL 14, 2010
8
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and
other differential signals. The differential signal must meet the VPP
and VCMR input requirements. Figures 3A to 3F show interface
examples for the CLK/nCLK input driven by the most common driver
types. The input interfaces suggested here are examples only.
Please consult with the vendor of the driver component to confirm the
driver termination requirements. For example, in Figure 3A, the input
termination applies for IDT open emitter HSTL drivers. If you are
using an HSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
Differential
Input
nCLK
LVPECL
Differential
Input
R1
50Ω
R2
50Ω
HSTL
R1
50Ω
R2
50Ω
IDT
HSTL Driver
R2
50Ω
3A. CLK/nCLK Input Driven by an
IDT Open Emitter HSTL Driver
Figure 3B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
3.3V
3.3V
3.3V
3.3V
R3
R4
3.3V
125Ω
125Ω
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
Zo = 50Ω
nCLK
nCLK
Zo = 50Ω
Differential
Input
LVPECL
Receiver
LVDS
R1
R2
84Ω
84Ω
Figure 3C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
Zo = 50Ω
*R3
*R4
33Ω
33Ω
Zo = 60Ω
Zo = 60Ω
CLK
CLK
Zo = 50Ω
nCLK
nCLK
Differential
Input
Differential
Input
SSTL
HCSL
R1
50Ω
R2
50Ω
R1
120Ω
R2
120Ω
*Optional – R3 and R4 can be 0Ω
Figure 3E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver
ICS871002AGI-02 REVISION A APRIL 14, 2010
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©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
Differential Outputs
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
Recommended Termination
Figure 4A is the recommended termination for applications which
require the receiver and driver to be on a separate PCB. All traces
should be 50Ω impedance.
Figure 4A. Recommended Termination
Figure 4B is the recommended termination for applications which
require a point to point connection and contain the driver and receiver
on the same PCB. All traces should all be 50Ω impedance.
Figure 4B. Recommended Termination
ICS871002AGI-02 REVISION A APRIL 14, 2010
10
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Schematic Layout
Figure 5 shows an example of ICS871002I-02 application schematic.
In this example, the device is operated at VDD= 3.3V. The decoupling
capacitors should be located as close as possible to the power pin.
The input is driven by a 3.3V LVPECL driver. Two examples of HCSL
termination are shown in this schematic.
Logic Control Input Examples
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
RU1
1K
RU2
Not Install
To Logic
Input
To Logic
Input
pins
VDD=3.3V
pins
RD1
RD2
1K
Not Install
R1
R2
33
33
Q0
Zo = 50
Zo = 50
+
-
nQ0
VDD
FB_IN
R3
nFB_IN
475
R4
50
R5
50
U1
Recommended for
PCI Express Add-In
Card
R7
50
R8
50
C1
1
20
19
18
17
16
15
14
13
12
11
.1uf
nQ0
Q0
VDD
Q1
2
3
IREF
FB_IN
FB_OUT
4
nFB_IN
MR
nFB_OUT
MR
nQ1
5
FB_IN
nFB_IN
FB_IN
GND
nCLK
CLK
6
BW_SEL
F_SEL1
nFB_IN
VDD
BW_SEL
F_SEL1
VDDA
7
R6
VDDA
8
10
9
F_SEL0
F_SEL0
VDD
10
OE
C3
VDD
HCSL Termination
OE
C2
10u
0.1u
C4
.1uf
Q1
Zo = 50
Zo = 50
+
-
nQ1
Zo = 50 Ohm
Zo = 50 Ohm
CLK
R9
50
R10
50
nCLK
Recommended for PCI
Express Point-to-Point
Connection
LVPECL Driver
R11
50
R12
50
R13
50
Figure 5. ICS871002I-02 Schematic Layout
ICS871002AGI-02 REVISION A APRIL 14, 2010
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©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS871002I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS71002I-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.63V * (75mA + 12mA) = 315.81mW
Power (outputs)MAX = 46.8mW/Loaded Output Pair
If all outputs are loaded, the total power is 3 * 46.8mW = 140.4mW
Total Power_MAX (3.63V, with all outputs switching) = 315.81mW + 140.4mW = 456.21mW
•
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 86.7°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.456W * 86.7°C/W = 124.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
86.7°C/W
82.4°C/W
80.2°C/W
ICS871002AGI-02 REVISION A APRIL 14, 2010
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©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 6.
VDD
IOUT = 17mA
VOUT
RREF
=
475Ω 1%
RL
50Ω
IC
Figure 6. HCSL Driver Circuit and Termination
HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50Ω load to ground.
The highest power dissipation occurs when VDD MAX.
_
Power = (VDD_MAX – VOUT) * IOUT
,
since VOUT – IOUT * RL
= (VDD_MAX – IOUT * RL) * IOUT
= (3.6V – 17mA * 50Ω) * 17mA
Total Power Dissipation per output pair = 46.8mW
ICS871002AGI-02 REVISION A APRIL 14, 2010
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©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
86.7°C/W
82.4°C/W
80.2°C/W
Transistor Count
The transistor count for ICS871002I-02 is: 1,704
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP
Table 8 Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS871002AGI-02 REVISION A APRIL 14, 2010
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©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
Ordering Information
Table 9. Ordering Information
Part/Order Number
871002AGI-02
871002AGI-02T
871002AGI-02LF
871002AGI-02LFT
Marking
Package
20 Lead TSSOP
20 Lead TSSOP
Shipping Packaging
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS71002AI02
ICS71002AI02
ICS1002AI02L
ICS1002AI02L
Tube
2500 Tape & Reel
Tube
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support
devices or critical medical instruments.
ICS871002AGI-02 REVISION A APRIL 14, 2010
15
©2010 Integrated Device Technology, Inc.
ICS871002I-02 Data Sheet
PCI EXPRESS™ JITTER ATTENUATOR
6024 Silver Creek Valley Road Sales
Technical Support
800-345-7015 (inside USA)
netcom@idt.com
+408-284-8200 (outside USA) +480-763-2056
Fax: 408-284-2775
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www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,
including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not
guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the
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