8725AYI-01LFT [IDT]
PLL Based Clock Driver, 8725 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32;
| 型号： | 8725AYI-01LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 8725 Series, 5 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32 驱动 逻辑集成电路 |
| 文件： | 总16页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS8725I-01 is a highly versatile 1:5 Differential-to-
HSTL Clock Generator. The ICS8725I-01 has a fully
integrated PLL and can be configured as zero delay buffer,
multiplier or divider, and has an output frequency range of
31.25MHz to 630MHz. The reference divider, feedback
divider and output divider are each programmable, thereby
allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows
the device to achieve “zero delay” between the input clock
and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
• 5 differential HSTL outputs
• Selectable differential CLKx, nCLKx input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
• Output frequency range: 31.25MHz to 630MHz
• Input frequency range: 31.25MHz to 630MHz
• VCO range: 250MHz to 630MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Static phase offset: 30ps ± 125ps
• Cycle-to-cycle jitter: 35ps (maximum)
• Output skew: 50ps (maximum)
• 3.3V core, 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
PLL_SEL
Q0
nQ0
Q1
nQ1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32,÷64
32 31 30 29 28 27 26 25
0
1
CLK0
nCLK0
Q2
nQ2
0
1
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SEL0
SEL1
VDDO
Q3
CLK1
nCLK1
Q3
nQ3
CLK0
nQ3
Q2
PLL
nCLK0
CLK1
Q4
nQ4
ICS8725I-01
10 11 12 13 14 15 16
32-Lead LQFP
CLK_SEL
nQ2
Q1
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
nCLK1
CLK_SEL
FB_IN
nFB_IN
nQ1
VDDO
MR
9
SEL0
SEL1
SEL2
SEL3
MR
7mm x 7mm x 1.4mm package body
Y Package
Top View
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2,
12, 29
SEL0, SEL1,
SEL2, SEL3
Determines output divider values in Table 3.
LVCMOS/LVTTL interface levels.
Input Pulldown
3
4
5
6
CLK0
nCLK0
CLK1
Input Pulldown Non-inverting differential clock input.
Input Pullup Inverting differential clock input.
Input Pulldown Non-inverting differential clock input.
nCLK1
Input
Pullup Inverting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1.
7
CLK_SEL
MR
Input Pulldown
When LOW, selects CLK0, nCLK0. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go
high. When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
8
Input Pulldown
Power
9, 32
10
VDD
Core supply pins.
nFB_IN
FB_IN
GND
Input
Pullup
Feedback input to phase detector for regenerating clocks with "zero delay".
11
Input Pulldown Feedback input to phase detector for regenerating clocks with "zero delay".
13, 28
14, 15
Power
Output
Power supply ground.
nQ0, Q0
Differential output pair. HSTL interface levels.
16, 17,
24, 25
VDDO
Power
Output supply pins.
18, 19
20, 21
22, 23
26, 27
30
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
VDDA
Output
Output
Output
Output
Power
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Analog supply pin.
Selects between the PLL and reference clock as the input to the dividers.
When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
31
PLL_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
KΩ
RPULLDOWN Input Pulldown Resistor
KΩ
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1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Outputs
Inputs
SEL0
PLL_SEL = 1
PLL Enable Mode
Q0:Q4, nQ0:nQ4
SEL3
SEL2
SEL1
Reference Frequency Range (MHz)*
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
250 - 630
125 - 315
÷ 1
÷ 1
÷ 1
÷ 1
÷ 2
÷ 2
÷ 2
÷ 4
÷ 4
÷ 8
x 2
x 2
x 2
x 4
x 4
x 8
62.5 - 157.5
31.25 - 78.75
250 - 630
125 - 315
62.5 - 157.5
250 - 630
125 - 315
250 - 630
125 - 315
62.5 - 157.5
31.25 - 78.75
62.5 - 157.5
31.25 - 78.75
31.25 - 78.75
*NOTE: VCO frequency range for all configurations above is 250MHz to 630MHz.
TABLE 3B. PLL BYPASS FUNCTION TABLE
Inputs
Outputs
PLL_SEL = 0
PLL Bypass Mode
SEL3
SEL2
SEL1
SEL0
Q0:Q4, nQ0:nQ4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
÷ 4
÷ 4
÷ 4
÷ 8
÷ 8
÷ 8
÷ 16
÷ 16
÷ 32
÷ 64
÷ 2
÷ 2
÷ 4
÷ 1
÷ 2
÷ 1
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1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
-0.5V to VDD + 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum Typical Maximum Units
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.135
3.135
1.6
3.3
3.3
1.8
3.465
3.465
2.0
V
V
VDDA
VDDO
IDD
V
137
17
mA
mA
mA
IDDA
IDDO
No Load
0
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
VDD = VIN = 3.465V
150
5
µA
µA
µA
µA
V
DDO = 2V
DD = VIN = 3.465V
DDO = 2V
VDD = 3.465V,
VDDO = 2V, VIN = 0V
DD = 3.465V,
VDDO = 2V, VIN = 0V
IIH
Input High Current
V
PLL_SEL
V
CLK_SEL, MR, SEL0,
SEL1, SEL2, SEL3
-5
IIL
Input Low Current
V
PLL_SEL
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
Minimum Typical Maximum Units
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
CLK0, CLK1, FB_IN
nCLK0, nCLK1, nFB_IN
150
5
µA
µA
µA
µA
V
Input
IIH
High Current
-5
Input
IIL
Low Current
-150
0.15
0.5
VPP
Peak-to-Peak Input Voltage
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
TABLE 4D. HSTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Output High Voltage;
NOTE 1
VOH
1
1.4
V
Output Low Voltage;
NOTE 1
VOL
0
40% x (VOH - VOL) + VOL
0.6
0.4
60% x (VOH - VOL) + VOL
1.1
V
V
V
VOX
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
VSWING
NOTE 1: Outputs terminated with 50Ω to ground.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
fIN Input Frequency
Test Conditions
PLL_SEL = 1
PLL_SEL = 0
Minimum Typical Maximum Units
31.25
630
630
MHz
MHz
CLK0, nCLK0,
CLK1, nCLK1
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 1.8V±0.2V, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
Units
630
MHz
PLL_SEL = 0V
IJ 630MHz
PLL_SEL = 3.3V
Propagation Delay; NOTE 1
3.4
-95
3.9
30
4.5
ns
t(Ø)
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
155
50
ps
ps
ps
ps
ms
ps
tsk(o)
tjit(cc)
tjit(Ø)
tL
35
±50
1
tR / tF
Output Rise/Fall Time
20% to 80%
300
700
tPW
Output Pulse Width
tPERIOD/2 - 85 tPERIOD/2 tPERIOD/2 + 85
ps
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal
across alll conditions, when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.8V ± 0.2V
3.3V ± 5%
VDD
,
SCOPE
VDD
VDDA
Qx
nCLK0,
nCLK1
VDDO
VPP
VCMR
Cross Points
HSTL
CLK0,
CLK1
GND
nQx
GND
0V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQ0:nQ4
Q0:Q4
nQx
nQ
➤
➤
➤
tcycle n
tcycle n+1
➤
nQy
Qy
tjit(cc) = tcycle n –tcycle n+1
tsk(o)
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
nCLK0,
VOH
VOL
nCLK1
CLK0,
CLK1
80%
tF
80%
tR
VOH
VOL
nFB_IN
VOD
Clock
Outputs
FB_IN
20%
20%
➤
t(Ø)
➤
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
OUTPUT RISE/FALL TIME
PHASE JITTER AND STATIC PHASE OFFSET
nCLK0,
nCLK1
nQ0:nQ4
Q0:Q4
CLK0,
CLK1
Pulse Width
tPERIOD
nQ0:nQ4
Q0:Q4
tPW
odc =
tPD
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
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1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL examples only. Please consult with the vendor of the driver
and other differential signals. Both VSWING and VOH must meet component to confirm the driver termination requirements. For
the VPP and VCMR input requirements. Figures 3A to 3D show example in Figure 3A, the input termination applies for HSTL
interface examples for the CLK/nCLK input driven by the most drivers. If you are using an HSTL driver from another vendor,
common driver types. The input interfaces suggested here are use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. CLK/NCLK INPUT DRIVEN BY
HSTL DRIVER
FIGURE 3B. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
LAYOUT GUIDELINE
The schematic of the ICS8725I-01 layout example is shown in depend on the selected component types, the density of the
Figure 4A. The ICS8725I-01 recommended PCB board layout components, the density of the traces, and the stacking of the
for this example is shown in Figure 4B. This layout example is P.C. board.
used as a general guideline. The layout in the actual system will
VDD
SP = Space (i.e. not intstalled)
R7
VDD
VDDA
RU2
SP
RU3
1K
RU4
1K
RU5
SP
RU6
1K
RU7
SP
10
C11
0.01u
CLK_SEL
PLL_SEL
SEL0
C16
10u
SEL1
SEL2
SEL3
Zo = 50 Ohm
Zo = 50 Ohm
(155.5 MHz)
+
-
RD2
1K
RD3
SP
RD4
SP
RD5
1K
RD6
SP
RD7
1K
VDD
VDDO
LVHSTL_input
U1
3.3V
R4A
50
R4B
50
(155.5 MHz)
SEL0
SEL1
Zo = 50 Ohm
1
24
23
22
21
20
19
18
17
SEL0
SEL1
VDDO
2
3
4
5
6
7
8
Q3
nQ3
Q2
nQ2
Q1
nQ1
VDDO
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
Zo = 50 Ohm
CLK_SEL
3.3V PECL Driver
VDD=3.3V
R8
50
R9
50
VDDO=1.8V
8725_01
SEL[3:0] = 0101,
Divide by 2
R10
50
SEL2
R2B
50
R2A
50
Bypass capacitors located near the power pins
VDD
VDDO
(U1-9)
(U1-32)
(U1-16)
(U1-17)
(U1-24)
(U1-25)
C1
0.1uF
C6
0.1uF
C2
0.1uF
C4
0.1uF
C5
0.1uF
C7
0.1uF
FIGURE 4A. ICS8725I-01 HSTL ZERO DELAY BUFFER SCHEMATIC EXAMPLE
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1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
The following component footprints are used in this layout
example:
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
• The differential 50Ω output traces should have same
Place the decoupling capacitors C1, C6, C2, C4, and C5, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
length.
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
GND
R7
C16 C11
C7
VDDO
C6
C5
VDD
U1
Pin 1
VDDA
VIA
50 Ohm
Traces
C4
C1
C2
FIGURE 4B. PCB BOARD LAYOUT FOR ICS8725I-01
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ICS8725I-01
1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8725I-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8725I-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (137mA + 17mA) = 499mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 5 * 32.8mW = 164mW
Total Power_MAX (3.465V, with all outputs switching) = 499mW + 164mW = 663mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.663W * 42.1°C/W = 113°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 7. Thermal Resistance θJA for 32-pin LQFP, Forced Convection
θJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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1:5 DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 5.
VDD
Q1
VOUT
RL
50Ω
FIGURE 5. HSTL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
- V
)
)
OH_MIN
L
DD_MAX
OH_MIN
/R ) * (V
OL_MAX
L
DD_MAX
OL_MAX
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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ZERO DELAY CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE
θJA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8725I-01 is: 2969
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ZERO DELAY CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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ZERO DELAY CLOCK GENERATOR
TABLE 10. ORDERING INFORMATION
Part/Order Number
8725AYI-01
Marking
Package
Shipping Packaging
tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS8725AYI-01
ICS8725AYI-01
ICS8725AI01L
ICS8725AI01L
32 Lead LQFP
8725AYI-01T
8725AYI-01
32 Lead LQFP
1000 Tape and Reel
tray
32 Lead-Free LQFP
32 Lead-Free LQFP
8725AYI-01T
1000 Tape and Reel
NOTE: Parts that are ordered with an ""LF"" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Inc. (IDT) assumes no responsibility for either its use or for infringement of
any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves
the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ZERO DELAY CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
A
T10
15
Ordering Information - Added Lead-Free marking
12/19/07
Updated datasheet's header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
A
T10
15
17
8/9/10
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ZERO DELAY CLOCK GENERATOR
We’ve Got Your Timing Solution.
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Tech Support
netcom@idt.com
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
© 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc.
Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of
their respective owners.
Printed in USA
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