87421AMIT [IDT]
Low Skew Clock Driver, PDSO8;
| 型号： | 87421AMIT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, PDSO8 光电二极管 |
| 文件： | 总14页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
÷1/÷2 DIFFERENTIAL-TO-LVDS
CLOCK GENERATOR
ICS87421I
GENERAL DESCRIPTION
FEATURES
The ICS87421I is a high performance ÷1/÷2
• One differential LVDS output
ICS
Differential-to-LVDS Clock Generator and a mem-
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from IDT. The CLK, nCLK
pair can accept most standard differential input
• One differential CLK, nCLK input pair
HiPerClockS™
• CLK, nCLK pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
levels. The ICS87421I is characterized to operate from a 3.3V
power supply. Guaranteed part-to-part skew characteristics
make the ICS87421I ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
• Maximum clock input frequency: 1GHz
• Translates any single ended input signal (LVCMOS, LVTTL,
GTL) to LVDS levels with resistor bias on nCLK input
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 1.7ns (maximum)
• Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical)
• Full 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK
nCLK
MR
VDD
Q
1
2
3
4
8
7
6
5
÷1
÷2
0
1
Q
nQ
CLK
nCLK
nQ
GND
R
F_SEL
ICS87421I
MR
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
F_SEL
IDT™ / ICS™ LVDS CLOCK GENERATOR
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TABLE 1. PIN DESCRIPTIONS
Number
Name
CLK
Type
Description
1
2
Input
Input
Pulldown Non-inverting differential clock input.
nCLK
Pullup
Inverting differential clock input.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true output (Q) to go low and the inverted output
(nQ) to go high. When logic LOW, the internal dividers and the output
are enabled. LVCMOS / LVTTL interface levels. See Table 3.
Selects divider value for Q, nQ outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
3
MR
Input
Pulldown
4
F_SEL
Input
Pulldown
5
6, 7
8
GND
Q, nQ
VDD
Power
Output
Power
Power supply ground.
Differential output pair. LVDS interface levels.
Positive supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
kΩ
kΩ
RPULLUP
RPULLDOWN
51
51
TABLE 3. FUNCTION TABLE
MR
1
F_SEL
Divide Value
X
0
1
Reset: Q output low, nQ output high
0
÷1
÷2
0
CLK
MR
Q
FIGURE 1A. ÷1 CONFIGURATION TIMING DIAGRAM
FIGURE 1B. ÷2 CONFIGURATION TIMING DIAGRAM
IDT™ / ICS™ LVDS CLOCK GENERATOR
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5 V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θ
96°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
3.135
3.3
55
3.465
V
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
1.37
-0.3
VDD + 0.3
0.7
V
VIL
IIH
Input Low Voltage
V
Input High Current MR, F_SEL
Input Low Current MR, F_SEL
VDD = VIN = 3.465V
150
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-5
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum
Typical
Maximum Units
CLK
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
V
nCLK
CLK
V
-5
IIL
Input Low Current
nCLK
VDD= 3.465V, VIN = 0V
-150
0.15
VPP
Peak-to-Peak Input Voltage
1.3
Common Mode Input Voltage;
NOTE 1
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
350
470
540
50
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.1
1.25
1.4
50
Δ VOS
VOS Magnitude Change
mV
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
fCLK
Clock Input Frequency
1
GHz
Propagation Delay;
NOTE 1
tPD
CLK to Q (Dif)
1.0
1.7
500
ns
tsk(pp)
tJIT
Part-to-Part Skew; NOTE 2, 3
ps
Additive Phase Noise, RMS;
refer to Additive Phase Jitter Section
155.52MHz, Integration
Range: 12kHz – 20MHz
0.17
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
150
43
500
57
ps
ꢀ
f
IN < 500MHz
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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ADDITIVE PHASE JITTER
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications.Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
Additive Phase Jitter @
155.52MHz (12kHz to 20MHz) = 0.17ps typical
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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PARAMETER MEASUREMENT INFORMATION
VDD
3.3V
SCOPE
nCLK
CLK
Qx
VDD
3.3V 5ꢀ
VPP
VCMR
Cross Points
POWER SUPPLY
+
Float GND –
LVDS
nQx
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
nQx
nCLK
CLK
Qx
PART 2
nQy
nQ
Q
Qy
tPD
tsk(pp)
PART-TO-PART SKEW
PROPAGATION DELAY
nQ
80ꢀ
tF
80ꢀ
Q
VSWING
20ꢀ
tPW
tPERIOD
Clock
20ꢀ
Outputs
tR
tPW
tPERIOD
odc =
x 100ꢀ
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
VDD
out
➤
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
out
VOS/Δ VOS
➤
out
➤
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
IDT™ / ICS™ LVDS CLOCK GENERATOR
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APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias DcDircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
HIPERCLOCKS LVHSTL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
nCLK
nCLK
HiPerClockS
HiPerClockS
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
IDT™ / ICS™ LVDS CLOCK GENERATOR
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LVDS DRIVER TERMINATION
input. For a multiple LVDS outputs buffer, if only partial outputs
are used, it is recommended to terminate the unused outputs.
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require
a matched load termination of 100Ω across near the receiver
3.3V
50Ω
3.3V
LVDS Driver
+
R1
100Ω
–
50Ω
100Ω Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS87421I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS87421I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
DD
•
Power_ = V
* I
= 3.465V * 55mA = 198.58mW
DD_MAX
MAX
DD_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 96°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.199W * 96°C/W = 104.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 8-PIN SOIC, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
96°C/W
87°C/W
82°C/W
IDT™ / ICS™ LVDS CLOCK GENERATOR
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RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
96°C/W
87°C/W
82°C/W
TRANSISTOR COUNT
The transistor count for ICS87421I is: 417
IDT™ / ICS™ LVDS CLOCK GENERATOR
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PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
Millimeters
MINIMUN MAXIMUM
SYMBOL
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document:JEDEC Publication 95, MS-012
IDT™ / ICS™ LVDS CLOCK GENERATOR
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TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS87421AMI
Marking
87421AMI
87421AMI
87421AIL
87421AIL
Package
8 lead SOIC
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS87421AMI
8 lead SOIC
2500 tape & reel
tube
ICS87421AMILF
ICS87421AMIFT
8 lead "Lead-Free" SOIC
8 lead "Lead-Free" SOIC
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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