87604GILFT [IDT]
Clock Generator, PDSO28;
| 型号： | 87604GILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PDSO28 光电二极管 |
| 文件： | 总11页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL
The ICS87604I is a 1:4 PCI/PCI-X Clock
ICS
Generator and a member of the HiPerClockSTM
family of high performance clock solutions from
ICS.The ICS87604I has a selectable REF_CLK
or crystal input. The REF_CLK input accepts
• 4 LVCMOS/LVTTL outputs, 15Ω typical output impedance
HiPerClockS™
• Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_IN clock input
LVCMOS or LVTTL input levels. The ICS87604I has a fully
integrated PLL along with frequency configurable clock and
feedback outputs for multiplying and regenerating clocks with
“zero delay”. The PLL’s VCO has an operating range of
250MHz-500MHz, allowing this device to be used in a variety
of general purpose clocking applications. For PCI/PCI-X
applications in particular, the VCO frequency should be set to
400MHz.This can be accomplished by supplying 33.33MHz,
25MHz, 20MHz, or 16.66MHz on the reference clock or crystal
input and by selecting ÷12, ÷16, ÷20, or ÷24, respectively as
the feedback divide value.The divider on the output bank can
then be configured to generate 33.33MHz (÷12), 66.66MHz
(÷6), 100MHz (÷4), or 133.33MHz (÷3).
• Maximum output frequency: 166.67MHz
• Maximum crystal input frequency: 38MHz
• Maximum REF_IN input frequency: 41.67MHz
• Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz
• Separate feedback control for generating PCI / PCI-X
frequencies from a 16.66MHz or 20MHz crystal, or 25MHz
or 33.33MHz reference frequency
• VCO range: 250MHz to 500MHz
• Cycle-to-cycle jitter: 120ps (maximum)
• Period jitter, RMS: 20ps (maximum)
• Output skew: 65ps (maximum)
The ICS87604I is characterized to operate with its core supply
at 3.3V and the bank supply at 3.3V or 2.5V.The ICS87604I is
packaged in a small 6.1mm x 9.7mm TSSOP body, making it
ideal for use in space-constrained applications.
• Static phase offset: 160ps 160ps
• Voltage Supply Modes:
VDD/VDDA/VDDO
3.3/3.3/3.3
3.3/3.3/2.5
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
BLOCK DIAGRAM
DIV_SEL0
DIV_SEL1
PIN ASSIGNMENT
XTAL_SEL
1
2
3
4
VDD
FB_IN
GND
28
27
26
25
FBDIV_SEL1
FBDIV_SEL0
DIV_SEL1
Q0
Q1
Q2
Q3
0
0
1
0
1
0
÷3
÷4
REF_IN
FB_OUT
REF_OUT
VDDO
DIV_SEL0
nc
0
1
0
1
24
23
22
21
20
19
5
6
7
8
XTAL_IN
÷6
MR
nc
OSC
÷12
1
1
Q3
XTAL_OUT
PLL
Q2
GND
GND
nc
GND
Q1
Q0
9
FB_IN
10
11
12
13
18
17
16
15
REF_IN
XTAL_OUT
XTAL_IN
VDDO
PLL_SEL
VDDA
÷12
÷16
÷20
0
0
1
0
1
0
PLL_SEL
REF_OUT
FB_OUT
14
XTAL_SEL
÷24
1
1
ICS87604I
28-Lead TSSOP, 240-MIL
6.1mm x 9.7mm x 0.92mm
body package
FBDIV_SEL1
FBDIV_SEL0
MR
G Package
TopView
87604AGI
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REV. A APRIL 12, 2005
1
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDD
Power
Input
Core supply pin.
Feedback input to phase detector for generating clocks with
"zero delay". LVCMOS / LVTTL interface levels.
2
FB_IN
Pulldown
3, 9, 20, 21
GND
FB_OUT
REF_OUT
VDDO
Power
Output
Output
Power
Power supply ground.
4
5
Feedback output. Connect to FB_IN. LVCMOS / LVTTL interface levels.
Reference clock output. LVCMOS / LVTTL interface levels.
Output supply pin
6, 12
7, 8,
10, 11
Q3, Q2,
Q1, Q0
Clock outputs. 15Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
13
14
PLL_SEL
VDDA
Input
Pullup
Pullup
Power
Analog supply pin. See Applications Note for filtering.
Selects between crystal oscillator or reference clock as the PLL
reference source. Selects XTAL inputs when HIGH. Selects REF_IN
when LOW. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
15
XTAL_SEL
Input
16,
17
XTAL_IN,
XTAL_OUT
Input
18
REF_IN
nc
Input
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
No connect.
19, 22, 24
Unused
Active HIGH Master Reset. When logic HIGH, the internal dividers
Pulldown are reset causing the outputs go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS / LVTTL interface levels.
23
MR
Input
25,
26
27,
28
DIV_SEL0,
DIV_SEL1
FBDIV_SEL0,
FBDIV_SEL1
Selects divide value for clock outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
Selects divide value for reference clock output and feedback output.
LVCMOS / LVTTL interface levels.
Input
Input
Pulldown
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
pF
pF
Ω
RPULLUP
51
51
9
RPULLDOWN Input Pulldown Resistor
VDD, VDDA, VDDO = 3.465V
Power Dissipation Capacitance
(per output); NOTE 1
CPD
V
DD, VDDA = 3.465V; VDDO = 2.625V
11
ROUT
Output Impedance
15
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REV. A APRIL 12, 2005
2
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 3A. OUTPUT CONTROL PIN FUNCTION TABLE
Inputs
Outputs
MR
1
Q0:Q3
LOW
FB_OUT, REF_OUT
LOW
0
Active
Active
TABLE 3C. PLL INPUT FUNCTION TABLE
Inputs
TABLE 3B. OPERATING MODE FUNCTION TABLE
Inputs
Operating Mode
PLL_SEL
XTAL_SEL
PLL Input
REF_IN
0
1
Bypass
PLL
0
1
XTAL Oscillator
TABLE 3D. CONTROL FUNCTION TABLE
Outputs
Frequency
Inputs
PLL_SEL=1
Reference
Frequency
Range (MHz)
FB_OUT
(MHz)
FBDIV_SEL1 FBDIV_SEL0 DIV_SEL1 DIV_SEL0
Q0:Q3
Q0:Q3 (MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
10 - 25
x 4
x 3
66.68 - 166.68
50 - 125
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
16.67 - 41.67
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
12.5 - 31.25
10 - 25
x 2
33.34 - 83.34
16.67 - 41.67
66.63 - 166.56
50 - 125
x 1
x 5.33
x 4
x 2.667
x 1.33
x 6.667
x 5
33.34 - 83.34
16.63 - 41.56
66.67 - 166.68
50 - 125
10 - 25
10 - 25
10 - 25
x 3.33
x 1.66
x 8
33.30 - 83.25
16.60 - 41.50
66.64 - 166.64
50 - 125
10 - 25
10 - 25
10 - 25
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
8.33 - 20.83
x 6
x 4
33.32 - 83.32
16.66 - 41.66
x 2
NOTE: VCO frequency range for all configurations above is 250MHz to 500MHz.
87604AGI
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REV. A APRIL 12, 2005
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ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, VDD
Inputs, VI
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
Outputs, VO
PackageThermal Impedance, θJA 49.8°C/W (0 lfpm)
StorageTemperature, TSTG -65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
185
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
15
20
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
MR, DIV_ SEL0, DIV_SEL1,
FBDIV_SEL0, FBDIV_SEL1,
XTAL_SEL, FB_IN, PLL_SEL
2
VDD + 0.3
V
V
Input
VIH
High Voltage
REF_IN
2
V
DD + 0.3
0.8
MR, DIV_ SEL0, DIV_SEL1,
FBDIV_SEL0, FBDIV_SEL1,
XTAL_SEL, FB_IN, PLL_SEL
-0.3
-0.3
V
Input
VIL
Low Voltage
REF_IN
1.3
V
DIV_ SEL0, DIV_SEL1,
FBDIV_SEL0, FBDIV_SEL1,
MR, FB_IN
V
DD = VIN = 3.465V
150
5
µA
µA
µA
Input
IIH
High Current
XTAL_SEL, PLL_SEL
VDD = VIN = 3.465V
DIV_ SEL0, DIV_SEL1,
FBDIV_SEL0, FBDIV_SEL1,
MR, FB_IN
V
DD = 3.465V,
VIN = 0V
-5
Input
IIL
Low Current
VDD = 3.465V,
VIN = 0V
XTAL_SEL, PLL_SEL
-150
µA
V
DD = VIN = 3.465V
2.6
1.8
V
V
V
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDD = VIN = 2.625V
0.5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
87604AGI
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REV. A APRIL 12, 2005
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ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
10
38
50
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
7
pF
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, VDD = VDDA =VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fREF Reference Frequency
8.33
41.67
MHz
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
fMAX
Output Frequency
166.67
325
65
MHz
ps
t(Ø)
Static Phase Offset; NOTE 1
Output Skew; NOTE 2, 5
Cycle-to-Cycle Jitter; 5
Period Jitter, RMS; NOTE 3, 5, 6
Slew Rate
FREF = 25MHz
0
160
tsk(o)
tjit(cc)
tjit(per)
tsl(o)
tL
ps
120
20
ps
ps
1
4
V/ns
ms
ps
PLL Lock Time
10
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle; NOTE 4
20ꢀ to 80ꢀ
200
48
700
52
ꢀ
All parameters measured with feedback and output dividers set to DIV by 12 unless otherwise noted.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal when the
PLL is locked and the input reference frequency is stable. Measured at VDD/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Jitter performance using LVCMOS inputs.
NOTE 4: Measured using REF_IN. For XTAL input, refer to Application Note.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: This parameter is defined as an RMS value.
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
fMAX
Output Frequency
166.67
160
50
MHz
ps
t(Ø)
Static Phase Offset; NOTE 1
Output Skew; NOTE 2, 5
Cycle-to-Cycle Jitter; 5
Period Jitter, RMS; NOTE 3, 5, 6
Slew Rate
FREF = 25MHz
-365
-105
tsk(o)
tjit(cc)
tjit(per)
tsl(o)
tL
ps
170
20
ps
ps
1
4
V/ns
ms
ps
PLL Lock Time
10
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle; NOTE 4
20ꢀ to 80ꢀ
200
48
700
52
ꢀ
See Table 7A for notes.
87604AGI
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REV. A APRIL 12, 2005
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ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
2.05V 5ꢀ
SCOPE
SCOPE
V
,
VDD
VDDA
,
VDDDDA,VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDDO
VDDO
2
VDDO
2
VDDO
2
Qx
2
Qx
➤
➤
tcycle n
tcycle n+1
➤
➤
VDDO
Qy
2
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
tsk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
VDD
80ꢀ
tF
80ꢀ
2
REF_IN
FB_IN
20ꢀ
20ꢀ
Clock
Outputs
VDD
2
tR
➤
➤
t(Ø)
OUTPUT RISE/FALL TIME
STATIC PHASE OFFSET
VDDO
2
VDDO
VDDO
2
2
Qx,
FB_OUT,
tPW
REF_OUT
tPERIOD
tPW
tPERIOD
odc =
OUTPUT PULSE WIDTH/PULSE WIDTH PERIOD
87604AGI
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REV. A APRIL 12, 2005
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ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS87604I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS87604I has been characterized with 18pF parallel resonant crystal and were chosen to minimize the frequency
resonant crystals. The capacitor values, C1 and C2, shown in ppm error. The optimum C1 and C2 values can be slightly ad-
Figure 2 below were determined using a 25MHz, 18pF parallel justed for optimum frequency accuracy.
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
87604AGI
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REV. A APRIL 12, 2005
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ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 28 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
68.7°C/W
43.9°C/W
500
60.5°C/W
41.2°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
82.9°C/W
49.8°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87604I is: 5495
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REV. A APRIL 12, 2005
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ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 28 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
28
--
1.20
0.15
1.05
0.30
0.20
9.80
A1
A2
b
0.05
0.80
0.19
0.09
9.60
c
D
E
8.10 BASIC
0.65 BASIC
E1
e
6.00
6.20
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
87604AGI
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REV. A APRIL 12, 2005
9
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS87604AGI
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS87604AGI
ICS87604AGI
28 Lead TSSOP
ICS87604AGIT
ICS87604AGILF
ICS87604AGILFT
28 Lead TSSOP
1000 tape & reel
tube
ICS87604AGILF
ICS87604AGILF
28 Lead "Lead-Free" TSSOP
28 Lead "Lead-Free" TSSOP
1000 tape & reel
NOTE: Parts that are with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
87604AGI
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REV. A APRIL 12, 2005
10
ICS87604I
LOW VOLTAGE/LOW SKEW, 1:4 PCI/PCI-X
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
A
Table
Page
5
Description of Change
Date
T7A & T7B
10
AC Characteristics Tables - corrected note sequence.
Ordering Information Table - added marking.
3/18/05
4/12/05
A
10
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REV. A APRIL 12, 2005
11
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AMPHENOL
87606-304
Board Connector, 8 Contact(s), 2 Row(s), Female, Straight, 0.1 inch Pitch, Solder Terminal, Locking, Blue Insulator, Receptacle
AMPHENOL
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