87949AYI-147LFT [IDT]
Clock Driver, PQFP52;
| 型号： | 87949AYI-147LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver, PQFP52 |
| 文件： | 总12页 (文件大小：287K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS87949I-147 is a low skew, ÷1, ÷2 • 15 single ended LVCMOS/LVTTL outputs,
ICS
LVCMOS/LVTTL Clock Generator and a member
of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS87949I-147
has selectable single ended clock or LVPECL
7Ω typical output impedance
HiPerClockS™
• Selectable LVCMOS/LVTTL or LVPECL clock inputs
• CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
clock inputs.The single ended clock input accepts LVCMOS
or LVTTL input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The low impedance
LVCMOS/LVTTL outputs are designed to drive 50Ω series or
parallel terminated transmission lines.The effective fanout can
be increased from 15 to 30 by utilizing the ability of the out-
puts to drive two series terminated lines.
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum input frequency: 250MHz
• Output skew: 250ps (maximum)
• Part-to-part skew: 1.0ns (maximum)
• Bank skew: 65ps (maximum)
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
• 3.3V or 2.5V supply voltage
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
The ICS87949I-147 is characterized at 3.3V and 2.5V. Guaran-
teed output and part-to-part skew characteristics make the
ICS87949I-147 ideal for those clock distribution applications
demanding well defined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
0
1
CLK0
CLK1
÷1
÷2
0
1
52 51 50 49 48 47 46 45 44 43 42 41 40
1
nc
MR/nOE
CLK_SEL
VDD
39
38
37
36
35
34
33
32
31
30
29
28
27
2
GND
QC0
VDDC
QC1
GND
QC2
VDDC
QC3
GND
GND
QD5
nc
R
PCLK
nPCLK
3
0
1
4
CLK0
QA0:QA1
QB0:QB2
QC0:QC3
PCLK_SEL
DIV_SELA
5
CLK1
6
PCLK
7
ICS87949I-147
nPCLK
0
1
8
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
9
10
11
12
13
DIV_SELB
DIV_SELC
0
1
14 15 16 17 18 19 20 21 22 23 24 25 26
0
1
QD0:QD5
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y Package
DIV_SELD
MR/nOE
TopView
87949AYI-147
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REV. C JUNE 13, 2005
1
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
Active High Master Reset. Active Low output enable. When logic
HIGH, the internal dividers are reset and the outputs are tri-stated
(HiZ). When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1. When LOW,
selects CLK0. LVCMOS / LVTTL interface levels.
1
MR/nOE
Input
Input
2
CLK_SEL
Pulldown
Pullup
3
4, 5
6
VDD
CLK0, CLK1
PCLK
Power
Input
Input
Input
Core supply pin.
LVCMOS / LVTTL clock inputs.
Pulldown Non-inverting differential LVPECL clock input.
Pullup Inverting differential LVPECL clock input.
7
nPCLK
PCLK select input. When HIGH, selects LVPECL clock input.
Pulldown When LOW, selects single ended clock input.
LVCMOS / LVTTL interface levels.
8
PCLK_SEL
Input
Controls frequency division for Bank A outputs.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank B outputs.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank C outputs.
LVCMOS / LVTTL interface levels.
Controls frequency division for Bank D outputs.
LVCMOS / LVTTL interface levels.
9
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
Input
Input
Input
Input
Pulldown
10
11
12
Pulldown
Pulldown
Pulldown
13, 15, 19, 23,
29, 30, 34, 38,
43, 47, 48, 52
14, 26,
27, 39, 40
16, 18,
GND
Power
Unused
Output
Power supply ground.
No connect.
nc
QD0, QD1,
QD2, QD3,
QD4, QD5
Bank D outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
20, 22,
24, 28
17, 21, 25
VDDD
Power
Output
Positive supply pins for Bank D outputs.
31, 33,
35, 37
QC3, QC2,
QC1, QC0
Bank C outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
32, 36
41, 45
VDDC
VDDB
Power
Power
Positive supply pins for Bank C outputs.
Positive supply pins for Bank B outputs.
42, 44,
46
QB2, QB1,
QB0
Bank B outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
Output
Bank A outputs. LVCMOS / LVTTL interface levels.
7Ω typical output impedance.
49, 51
50
QA1, QA0
VDDA
Output
Power
Positive supply pin for Bank A outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
87949AYI-147
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REV. C JUNE 13, 2005
2
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
pF
pF
Ω
RPULLUP
51
51
23
16
7
RPULLDOWN Input Pulldown Resistor
3.47V
CPD
Power Dissipation Capacitance (per output)
Output Impedance
2.625V
ROUT
5
12
TABLE 3. FUNCTION TABLE
Inputs
Outputs
MR/nOE
DIV_SELA
DIV_SELB
DIV_SELC DIV_SELD
QA0, QA1
QB0:QB2
Hi Z
QC0:QC3
QD0:QD5
Hi Z
1
0
0
0
0
0
0
0
0
X
0
X
X
X
0
X
X
X
X
X
0
X
X
X
X
X
X
X
0
Hi Z
fIN/1
Hi Z
Active
Active
Active
Active
fIN/1
Active
Active
fIN/1
Active
Active
Active
Active
Active
Active
fIN/1
1
fIN/2
X
X
X
X
X
X
Active
Active
Active
Active
Active
Active
1
fIN/2
X
X
X
X
Active
Active
Active
Active
1
fIN/2
X
X
Active
Active
1
fIN/2
87949AYI-147
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REV. C JUNE 13, 2005
3
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW, ÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V toVDD + 0.5 V
-0.5V to VDD + 0.5V
42.3°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature,T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
60
V
VDDx
IDD
Output Supply Voltage; NOTE 1
Core Power Supply Current
V
mA
mA
IDDx
Output Power Supply Current; NOTE 2
20
NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD
.
NOTE 2: IDDx denotes the sum of IDDA, IDDB, IDDC, IDDD
.
TABLE 4B. DC CHARACTERISTICS, VDD = VDDX = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
VIH
Input High Voltage
2
VDD + 0.3
V
DIV_SELA:DIV_SELD,
PCLK_SEL, CLK_SEL,
MR/nOE
-0.3
0.8
V
Input
Low Voltage
VIL
CLK0, CLK1
-0.3
0.3
1.3
1
V
V
V
VPP
Peak-to-Peak Input Voltage
VCMR
Common Mode Input Voltage; NOTE 1, 2
DIV_SELA:DIV_SELD,
GND + 1.5
VDD
CLK_SEL, PCLK_SEL,
MR/nOE
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
CLK0, CLK1
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
VDD = 3.465V, VIN = 0V
-5
Input
Low Current
IIL
CLK0, CLK1
VDD = 3.465V, VIN = 0V
IOH = -20mA
-150
2.5
µA
V
VOH
VOL
Output High Voltage
Output Low Voltage
IOL = 20mA
0.4
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
87949AYI-147
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REV. C JUNE 13, 2005
4
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Core Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
60
V
VDDx
IDD
Output Supply Voltage; NOTE 1
Core Power Supply Current
V
mA
mA
IDDx
Output Power Supply Current; NOTE 2
20
NOTE 1: VDDx denotes VDDA, VDDB, VDDC, VDDD
.
NOTE 2: IDDx denotes the sum of IDDA, IDDB, IDDC, IDDD
.
TABLE 4D. DC CHARACTERISTICS, VDD = VDDX = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
VIH
Input High Voltage
2
VDD + 0.3
V
DIV_SELA:DIV_SELD,
PCLK_SEL, CLK_SEL,
MR/nOE
-0.3
0.8
V
Input
Low Voltage
VIL
CLK0, CLK1
-0.3
0.3
1.3
1
V
V
V
VPP
Peak-to-Peak Input Voltage
VCMR
Common Mode Input Voltage; NOTE 1, 2
DIV_SELA:DIV_SELD,
GND + 1.5
VDD
CLK_SEL, PCLK_SEL,
MR/nOE
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
CLK0, CLK1
DIV_SELA:DIV_SELD,
CLK_SEL, PCLK_SEL,
MR/nOE
VDD = 3.465V, VIN = 0V
-5
Input
Low Current
IIL
CLK0, CLK1
VDD = 3.465V, VIN = 0V
IOH = -20mA
-150
1.8
µA
V
VOH
VOL
Output High Voltage
Output Low Voltage
IOL = 20mA
0.4
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
87949AYI-147
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REV. C JUNE 13, 2005
5
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, VDD = VDDX = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
fMAX Input Frequency
Test Conditions
Minimum Typical Maximum Units
200
4.2
5
MHz
ns
PCLK, nPCLK
CLK0, CLK1
2.1
2.1
Propagation Delay;
NOTE 1
tPD
ns
Measured on the rising edge
at VDDx/2
tsk(b)
tsk(o)
tsk(pp)
Bank Skew: NOTE 2
65
300
1
ps
ps
ns
Measured on the rising edge
at VDDx/2
Output Skew; NOTE 3, 6
Measured on the rising edge
at VDDx/2
Part-to-Part Skew; NOTE 4, 6
tR
Output Rise Time
Output Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
400
400
40
950
950
60
5
ps
ps
ꢀ
tF
odc
t
t
PZL, tPZH Output Enable Time; NOTE 5
PLZ, tPHZ Output Disable Time; NOTE 5
ns
ns
5
NOTE 1: Measured from the VDD/2 or crosspoint of the input to VDDx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at VDDx/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDX = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fMAX Input Frequency
tPD
Test Conditions
Minimum Typical Maximum Units
250
5.2
MHz
ns
Propagation Delay; NOTE 1
Bank Skew: NOTE 2
2.5
Measured on the rising edge
at VDDx/2
tsk(b)
tsk(o)
tsk(pp)
55
250
1.5
ps
ps
ns
Measured on the rising edge
at VDDx/2
Output Skew; NOTE 3, 6
Measured on the rising edge
at VDDx/2
Part-to-Part Skew; NOTE 4, 6
tR
Output Rise Time
Output Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
400
400
40
950
950
60
5
ps
ps
ꢀ
tF
odc
tPZL, tPZH Output Enable Time; NOTE 5
tPLZ, tPHZ Output Disable Time; NOTE 5
ns
ns
5
NOTE 1: Measured from the VDD/2 or crosspoint of the input to VDDx/2 of the output.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
Measured at VDDx/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
87949AYI-147
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REV. C JUNE 13, 2005
6
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V
1.25V 5ꢀ
SCOPE
SCOPE
VDD
VDDx
,
VDD
VDDx
,
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.165V 0.15V
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
VDDx
Qx
2
nPCLK
VPP
VCMR
Cross Points
VDDx
PCLK
Qy
2
tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
PART 1
VDDx
80ꢀ
tF
80ꢀ
tR
Qx
2
VOD
Clock
Outputs
20ꢀ
20ꢀ
PART 2
VDDx
Qy
2
tsk(pp)
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME
VDDx
2
VDD
2
CLK0, CLK1
QAx, QBx,
QCx, QDx
tPW
tPERIOD
nPCLK
PCLK
tPW
tPERIOD
x 100ꢀ
odc =
VDDx
2
QAx,QBx,
QCx, QDx
➤
tPD
➤
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
87949AYI-147
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REV. C JUNE 13, 2005
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ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver ter-
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 1A to 1F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by mination requirements.
the most common driver types.The input interfaces suggested
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
R1
100
nPCLK
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 1A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 1B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
R4
R3
84
R4
84
125
125
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
FIGURE 1C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 1D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
1K
R4
1K
R3
120
R4
120
C1
C2
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 1E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 1F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
87949AYI-147
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REV. C JUNE 13, 2005
8
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 52 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
47.1°C/W
36.4°C/W
500
42.0°C/W
34.0°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
58.0°C/W
42.3°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87949I-147 is: 1545
Pin compatible to the MPC949
87949AYI-147
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REV. C JUNE 13, 2005
9
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
PACKAGE OUTLINE - Y SUFFIX FOR 52 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
52
--
--
1.60
0.15
1.45
0.38
0.33
A1
A2
b
0.05
1.35
0.22
0.22
--
1.40
0.32
b1
D
0.30
12.00 BASIC
10.00 BASIC
12.00 BASIC
10.00 BASIC
0.65 BASIC
--
D1
E
E1
e
ccc
ddd
0.45
--
0.10
0.13
--
Reference Document: JEDEC Publication 95, MS-026
87949AYI-147
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REV. C JUNE 13, 2005
10
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS87949AYI-147
Marking
Package
Shipping Packaging
tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
7949AI147
7949AI147
TBD
52 Lead LQFP
ICS87949AYI-147T
ICS87949AYI-147LF
ICS87949AYI-147LFT
52 Lead LQFP
500 tape & reel
tray
52 Lead "Lead-Free" LQFP
52 Lead "Lead-Free" LQFP
TBD
500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
87949AYI-147
www.icst.com/products/hiperclocks.html
REV. C JUNE 13, 2005
11
ICS87949I-147
Integrated
Circuit
Systems, Inc.
LOW SKEW,
÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
1
Page
2
Description of Change
Pin Description Table - revised MR/nOE description.
Date
4A, 4B, 5A
4, 5
In 3.3V DC and AC tables, changed VDD = VDDx from
3.3V 5ꢀ to 3.3V 0.3V.
B
08/27/02
4B, 4D
4, 6
In 3.3V & 2.5V DC Characteristics tables - VIL row, spec input controls
separately from input clocks.
7
9
3.3V Output Load Test Circuit Diagram, changed VDD equation to read
1.65V 0.15V from 1.65V 5ꢀ.
Revised and replaced Package Outline diagram to correspond with
Package Dimensions table.
T1
2
Pin Description Table - changed VDD description to read Core supply pin from
Positive supply pin.
B
11/21/02
T4A, T4C
4, 5
Power Supply Characteristics table - changed VDD description to read
Core Supply Voltage from Positive Supply Voltage.
Listed Bank Skew in Features Section.
1
2
3
T1
T2
Updated MR/nOE description.
C
C
09/15/03
6/13/05
Pin Characteristics Table - change CIN to read 4pF typ. from 4pF max.
ROUT added 5Ω min. and 12Ω max.
AC Characteristics Tables, added Bank Skew entries.
Features Section - added Lead-Free bullet.
Added LVPECL Clock Input Interface section.
Ordering Information Table - added Lead-Free part number.
T5A, T5B
T8
6
1
8
11
87949AYI-147
www.icst.com/products/hiperclocks.html
REV. C JUNE 13, 2005
12
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