889474AKLFT [IDT]

2:1 LVDS Multiplexer With 1:2 Fanout and Internal Termination;


型号：	889474AKLFT
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	2:1 LVDS Multiplexer With 1:2 Fanout and Internal Termination 驱动逻辑集成电路
文件：	总16页 (文件大小：216K)
中文：	中文翻译
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2:1 LVDS Multiplexer With 1:2 Fanout

and Internal Termination

889474

DATA SHEET

GENERAL DESCRIPTION

FEATURES

The 889474 is a high speed 2-to-1 differential multiplexer

with integrated 2 output LVDS fanout buffer and internal

termination and is a member of the family of high performance

clock solutions from IDT. The 889474 is optimized for

high speed and very low output skew, making it suitable

for use in demanding applications such as SONET,

1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel.The internally

terminated differential input andV^REF_AC pins allow other differential

signal families such as LVPECL, LVDS, LVHSTL and CML to be easily

interfaced to the input with minimal use of external components.The

889474 is packaged in a small 4mm x 4mm 24-pinVFQFN package

which makes it ideal for use in space-constrained applications.

• Two differential LVDS outputs

• INx, nINx pair can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, CML

• 50Ω internal input termination to V

• Maximum output frequency: 2GHz (maximum)

• Additive phase jitter, RMS: 0.06ps (typical)

• Output skew: 20ps (maximum)

• Propagation delay: 700ps (maximum)

• 2.5V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free RoHS-complaint package

BLOCK DIAGRAM

PIN ASSIGNMENT

IN0

50Ω

24 23 22 21 20 19

50Ω

nQ0

nIN0

VDD

nIN0

GND

MUX

REF_AC0

IN1

V^REF_AC0

50Ω

VT0

IN0

V^DD

15 SEL

14 GND

nQ1

nIN1

V^DD

REF_AC1

10 11 12

SEL

889474

24-Lead VFQFN

4mm x 4mm x 0.925mm package body

K Package

Top View

889474 REVISION A 11/11/15

889474 DATA SHEET

TABLE 1. PIN DESCRIPTIONS

Number

Name

Type

Description

1, 6, 9, 10,

13, 19, 24

Power

Positive supply pins.

2, 20

nIN0, nIN1

Input

Inverting differential clock inputs. 50Ω internal input termination to V .

V^REF_AC0,

Output

Reference voltage for AC-coupled applications.

REF_AC1

4, 22

5, 23

7, 8

V V

Input

Termination inputs.

T0,

IN0, IN1

Q0, nQ0

Q1, nQ1

GND

Non-inverting differential clock inputs. 50Ω internal input termination to V .

Output

Power

Input

Differential output pair. LVDS interface levels.

Power supply ground.

11, 12

14, 17, 18

SEL

Pullup Input select pin. LVCMOS/LVTTL interface levels.

No connect.

Unused

NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

TABLE 2. PIN CHARACTERISTICS

Symbol Parameter

Input Pullup Resistor

Test Conditions

Minimum

Typical

Maximum

Units

kΩ

PULLUP

TABLE 3.TRUTH TABLE

Inputs

Outputs

IN0

nIN0

IN1

nIN1

SEL

Q0:Q1

nQ0:nQ1

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

REVISION A 11/11/15

889474 DATA SHEET

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

4.6V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress speciﬁcations only. Functional

operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

Inputs, V

-0.5V to V + 0.5 V

Outputs, I (LVDS)

Continuous Current

Surge Current

10mA

15mA

Input Current, INx, nINx

V Current, I

50mA

100mA

Input Sink/Source, I

0.5mA

REF_AC

Operating Temperature Range, T

-40°C to +85°C

-65°C to 150°C

49.5°C/W (0 mps)

Storage Temperature, T

STG

Package Thermal Impedance, θ

(Junction-to-Ambient)

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V = 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum Units

Positive Supply Voltage

Power Supply Current

2.375

2.5

2.625

TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V = 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum Typical Maximum Units

Input High Voltage

1.7

+ 0.3

Input Low Voltage

Input High Current

Input Low Current

0.7

= V = 2.625V

µA

= 2.625V, V = 0V

-150

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V = 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Test Conditions

Minimum

Typical Maximum Units

Input Resistance

IN-to-V

IN-to-VT

1.2

Differential Input Resistance

Input High Voltage

INx, nINx

100

110

DIFF_IN

Input Low Voltage

V – 0.1

Input Voltage Swing

0.1

Differential

Input Voltage Swing

INx, nINx

0.2

DIFF_IN

IN-to-V

1.28

T_IN

Output Reference Voltage

– 1.4

– 1.3

V – 1.2

REF_AC

REVISION B 11/11/15

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

889474 DATA SHEET

TABLE 4D. LVDS DC CHARACTERISTICS, V = 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol Parameter

Output Voltage Swing

Test Conditions

Minimum

340

Typical

400

Maximum Units

OUT

Differential Output Voltage Swing

Output Common Mode Voltage

Change in Common Mode Voltage

680

800

DIFF_OUT

1.10

1.35

OCM

-50

Δ V

OCM

TABLE 5. AC CHARACTERISTICS, V = 2.5V 5ꢀ% TA = -40°C TO 85°C

Symbol

Parameter

Condition

Minimum Typical Maximum Units

Gpbs

GHz

Output Frequency

MAX

Q0:1/nQ0:1

IN-to-Q

400

250

700

600

Propagation Delay,

(Differential)% NOTE 1

SEL-to-Q

tsk(o)

Output Skew% NOTE 2, 4

tsk(pp)

Part-to-Part Skew% NOTE 3, 4

200

Buffer Additive Phase Jitter, RMS%

Refer to Additive Phase Jitter Section,

NOTE 5

155.52MHz,

tjit

0.06

12kHz – 20MHz

MUX_

Mux Isolation

ISOLATION

t /t

Output Rise/Fall Time

20ꢀ to 80ꢀ

220

NOTE: All parameters are characterized at ≤ 1GHz unless otherwise noted.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Deﬁned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the output differential cross points.

NOTE 3: Deﬁned as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at the differential cross points.

NOTE 4: This parameter is deﬁned in accordance with JEDEC Standard 65.

NOTE 5: Driving only one input clock.

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

REVISION A 11/11/15

889474 DATA SHEET

ADDITIVE PHASE JITTER

(dBm) or a ratio of the power in the 1Hz band to the power in the

fundamental.When the required offset is speciﬁed, the phase noise

is called a dBc value, which simply means dBm at a speciﬁed offset

from the fundamental.By investigating jitter in the frequency domain,

we get a better understanding of its effects on the desired application

over the entire time record of the signal.It is mathematically possible

to calculate an expected bit error rate given a phase noise plot.

The spectral purity in a band at a speciﬁc offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the speciﬁed plot in many applications. Phase

noise is deﬁned as the ratio of the noise power present in a 1Hz

band at a speciﬁed offset from the fundamental frequency to the

power value of the fundamental.This ratio is expressed in decibels

Additive Phase Jitter @ 155.52MHz

(12kHz to 20MHz)

= 0.06ps typical

OFFSET FROM CARRIER FREQUENCY (HZ)

As with most timing speciﬁcations, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

ﬂoor of the equipment is higher than the noise ﬂoor of the device.

This is illustrated above. The device meets the noise ﬂoor of what

is shown, but can actually be lower.The phase noise is dependent

on the input source and measurement equipment.

REVISION B 11/11/15

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

889474 DATA SHEET

PARAMETER MEASUREMENT INFORMATION

OUTPUT LOAD AC TEST CIRCUIT

DIFFERENTIAL INPUT LEVEL

PART-TO-PART SKEW

OUTPUT SKEW

OUTPUT RISE/FALL TIME

PROPAGATION DELAY

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

REVISION A 11/11/15

889474 DATA SHEET

SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING

OFFSET VOLTAGE SETUP

DIFFERENTIAL OUTPUT VOLTAGE SETUP

REVISION B 11/11/15

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

889474 DATA SHEET

APPLICATION INFORMATION

LVPECL INPUT WITH BUILT-IN 50Ω TERMINATIONS INTERFACE

The IN /nIN with built-in 50Ω terminations accepts LVDS,

input interfaces suggested here are examples only. If the driver is

from another vendor, use their termination recommendation.Please

consult with the vendor of the driver component to conﬁrm the driver

termination requirements.

LVPECL, CML and other differential signals. The signal must

meet the V and V input requirements. Figures 1A to 1E show

interface examples^CMfo^Rr the HiPerClockS IN/nIN input with built-in

50Ω terminations driven by the most common driver types. The

2.5V

3.3V or 2.5V

2.5V

Zo = 50 Ohm

nIN

Receiver

With

Receiver

With

Built-In

50 Ohm

2.5V LVPECL

LVDS

Built-In

50 Ohm

FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH

FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER

BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER

2.5V

Zo = 50 Ohm

nIN

Receiver

With

CML - Built-in 50 Ohm Pull-up

CML - Open Collector

Built-In

50 Ohm

Built-In

50 Ohm

FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH

FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY A CML DRIVER

WITH BUILT-IN 50Ω PULLUP

BUILT-IN 50Ω DRIVEN BY A CML DRIVER

FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH

BUILT-IN 50Ω DRIVEN BY AN SSTL DRIVER

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

REVISION A 11/11/15

889474 DATA SHEET

RECOMMENDATIONS FOR UNUSED OUTPUT PINS

INPUTS:

OUTPUTS:

IN/nIN INPUTS

LVDS OUTPUTS

For applications not requiring the use of the differential input, both IN

and nIN can be left ﬂoating.Though not required, but for additional

protection, a 1kΩ resistor can be tied from IN to ground.

All unused LVDS output pairs can be either left ﬂoating or terminated

with 100Ω across. If they are left ﬂoating, there should be no trace

attached.

2.5V LVDS DRIVER TERMINATION

transmission line environment. For buffer with multiple LVDS

driver, it is recommended to terminate the unused outputs.

Figure 2 shows a typical termination for LVDS driver in

characteristic impedance of 100Ω differential (50Ω single)

2.5V

LVDS_Driver

100

100 Ohm Differential Transmission Line

100Ω Differential Transmission Line

FIGURE 2.TYPICAL LVDS DRIVER TERMINATION

2.5V DIFFERENTIAL INPUT WITH BUILT-IN 50Ω TERMINATION UNUSED INPUT HANDLING

To prevent oscillation and to reduce noise, it is recommended

to have pull up and pull down connect to true and compliment

of the unused input as shown in Figure 3.

2.5V

680

nIN

Receiver

with

Built-In

50 Ohm

680

FIGURE 3. UNUSED INPUT HANDLING

REVISION B 11/11/15

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

889474 DATA SHEET

VFQFN EPAD THERMAL RELEASE PATH

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on

the package, as shown in Figure 4.The solderable area on the PCB,

as deﬁned by the solder mask, should be at least the same size/

shape as the exposed pad/slug area on the package to maximize

the thermal/electrical performance. Sufﬁcient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

speciﬁc and dependent upon the package power dissipation as well

as electrical conductivity requirements.Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern.

It is recommended to use as many vias connected to ground as

possible.It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This

is desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land.Precautions should be taken

to eliminate any solder voids between the exposed heat slug and

the land pattern.Note:These recommendations are to be used as a

guideline only. For further information, refer to the Application Note

on the Surface Mount Assembly of Amkor’s Thermally/Electrically

Enhance Leadfame Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern

must be connected to ground through these vias. The vias act as

“heat pipes”. The number of vias (i.e. “heat pipes”) are application

FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

REVISION A 11/11/15

889474 DATA SHEET

POWER CONSIDERATIONS

This section provides information on power dissipation and junction temperature for the 889474.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 889474 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V = 2.625V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

Power (core) = V

* I

= 2.625V * 80mA = 210mW

DD_MAX

MAX

DD_MAX

Power Dissipation at built-in terminations: Assume the input is driven by a 2.5V SSTL driver as shown in Figure 1E and

estimated approximately 1.75V drop across IN and nIN.

Total Power Dissipation for the two 50Ω built-in terminations is: (1.75V) / (50Ω + 50Ω) = 30.6mW

Input pair for both inputs is 2 * 30.6mW = 61.2mW

Total Power

(2.625V, with all outputs switching) = 210mW + 61.2mW = 271.2mW

_MAX

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the

device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + T

Tj = Junction Temperature

JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ^JAmust be used. Assuming no air ﬂow

and a multi-layer board, the appropriate value is 49.5°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:

85°C + 0.271W * 49.5°C/W = 98.4°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air ﬂow,

and the type of board (single layer or multi-layer).

TABLE 6.THERMAL RESISTANCE θ_JAFOR 24-PIN VFQFN, FORCED CONVECTION

θ_JAvs. 0 Velocity (Meters per Second)

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

49.5°C/W

43.3°C/W

38.8°C/W

REVISION B 11/11/15

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

889474 DATA SHEET

RELIABILITY INFORMATION

TABLE 7. θ VS. AIR FLOW TABLE FOR 24 LEAD VFQFN

θ_JAvs. 0 Velocity (Meters per Second)

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

49.5°C/W

43.3°C/W

38.8°C/W

TRANSISTOR COUNT

The transistor count for 889474 is: 367

Pin compatible with SY89474U

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

REVISION A 11/11/15

889474 DATA SHEET

PACKAGE OUTLINE - K SUFFIX FOR 24 LEAD VFQFN

NOTE: The following package mechanical drawing is a generic

drawing that applies to any pin countVFQFN package.This drawing

is not intended to convey the actual pin count or pin layout of this

device. The pin count and pinout are shown on the front page. The

package dimensions are in Table 8 below.

T^ABLE8. PACKAGE DIMENSIONS

JEDEC VARIATION

ALL DIMENSIONS IN MILLIMETERS

SYMBOL

MINIMUM

MAXIMUM

0.80

1.0

0.05

0.25 Reference

0.18

0.30

0.50 BASIC

2.30

2.55

2.30

0.30

2.55

0.50

Reference Document: JEDEC Publication 95, MO-220

REVISION B 11/11/15

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

889474 DATA SHEET

TABLE 9. ORDERING INFORMATION

Part/Order Number

889474AKLF

Marking

Package

Shipping Packaging Temperature

9474AL

24 Lead VFQFN “Lead-Free”

tube

-40°C to 85°C

889474AKLFT

tape & reel

NOTE: Parts that are ordered with an “LF” sufﬁx to the part number are the Pb-Free conﬁguration and are RoHS compliant.

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

REVISION A 11/11/15

889474 DATA SHEET

REVISION HISTORY SHEET

Rev

Table

Page

Description of Change

Date

Ordering Information - removed leaded devices.

Updated data sheet format.

11/11/15

REVISION B 11/11/15

2:1 LVDS MULTIPLEXER WITH 1:2 FANOUT

AND INTERNAL TERMINATION

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, California 95138

Sales

800-345-7015 or +408-284-8200

Fax: 408-284-2775

www.IDT.com

Technical Support

email: clocks@idt.com

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or speciﬁcations described herein at any time and at IDT’s sole discretion. All information in

this document, including descriptions of product features and performance, is subject to change without notice. Performance speciﬁcations and the operating parameters of the described products are determined

in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, wheth-

er express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others.

This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reason-

ably expected to signiﬁcantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or

their respective third party owners.

889474AKLFT [IDT]

相关型号：

889474AKT

88948

88948-102

88948-102LF

88948-112

88948-112LF

88948-202

88948-202LF

88948-212

88948-212LF

88948-302

88948-302LF